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\n  \n 2016\n \n \n (1)\n \n \n
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\n \n\n \n \n \n \n \n \n Efficient and Scalable Runtime Monitoring for Cyber–Physical System.\n \n \n \n \n\n\n \n Zheng, X.; Julien, C.; Podorozhny, R.; Cassez, F.; and Rakotoarivelo, T.\n\n\n \n\n\n\n IEEE Systems Journal, 99: 1–12. October 2016.\n \n\n\n\n
\n\n\n\n \n \n \"EfficientPaper\n  \n \n \n \"Efficient link\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n  \n \n abstract \n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n \n \n \n \n\n\n\n
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@article{ieee-16,\n  title={Efficient and Scalable Runtime Monitoring for Cyber--Physical System},\n  author={Zheng, Xi and Christine Julien and {Rodion M.} Podorozhny  and Franck Cassez and Thierry Rakotoarivelo},\n  journal={IEEE Systems Journal},\n  year={2016},\n  volume=99,\n  pages={1--12},\n  publisher={IEEE},\n  doi={10.1109/JSYST.2016.2614599},\n  ISSN={1932-8184},\n  urlpaper={papers/ieee-systems-2016.pdf},\n  url_link={http://ieeexplore.ieee.org/document/7605519/},\n  month=oct,\n  show = {},\n  keywords = {wcet, timed automata},\n\n  abstract={Our reliance on cyber–physical systems (CPSs) is increasingly widespread, but scalable methods for the analysis of such systems remain a significant challenge. Runtime verification of CPSs provides a reasonable middle ground between formal verification and simulation approaches, but it comes with its own challenges. A runtime verification system must run directly on the deployed application. In the CPS domain, it is therefore critical that a runtime verification system exhibits low overhead and good scalability so that the verification does not interfere with the analyzed CPS application. In this paper, we introduce Brace, a runtime verification system whose focus is on ensuring these performance qualities for applications in the CPS domain. Brace strives to bound the computation overhead for CPS runtime verification while preserving a high level of monitoring accuracy in terms of the number of false positive and false negative reports. Brace is particularly suitable to systems in which scheduling is distributed across networked CPS components. We evaluate Brace to determine how effectively and efficiently it can detect injected errors in two existing real-life CPS applications with distributed scheduling. Our results demonstrate that Brace efficiently detects those errors and a few true bugs and is able to bound both the memory and computation overhead even in systems with large numbers of observed events.},\n  Type = {A - Journal},\n\n}\n\n
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\n\n\n
\n Our reliance on cyber–physical systems (CPSs) is increasingly widespread, but scalable methods for the analysis of such systems remain a significant challenge. Runtime verification of CPSs provides a reasonable middle ground between formal verification and simulation approaches, but it comes with its own challenges. A runtime verification system must run directly on the deployed application. In the CPS domain, it is therefore critical that a runtime verification system exhibits low overhead and good scalability so that the verification does not interfere with the analyzed CPS application. In this paper, we introduce Brace, a runtime verification system whose focus is on ensuring these performance qualities for applications in the CPS domain. Brace strives to bound the computation overhead for CPS runtime verification while preserving a high level of monitoring accuracy in terms of the number of false positive and false negative reports. Brace is particularly suitable to systems in which scheduling is distributed across networked CPS components. We evaluate Brace to determine how effectively and efficiently it can detect injected errors in two existing real-life CPS applications with distributed scheduling. Our results demonstrate that Brace efficiently detects those errors and a few true bugs and is able to bound both the memory and computation overhead even in systems with large numbers of observed events.\n
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\n  \n 2015\n \n \n (2)\n \n \n
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\n \n\n \n \n \n \n \n \n BraceAssertion: Runtime Verification of Cyber-Physical Systems.\n \n \n \n \n\n\n \n Zheng, X.; Julien, C.; Podorozhny, R.; and Cassez, F.\n\n\n \n\n\n\n In 12th IEEE International Conference on Mobile Ad Hoc and Sensor Systems, MASS 2015, Dallas, TX, USA, October 19-22, 2015, pages 298–306, 2015. \n \n\n\n\n
\n\n\n\n \n \n \"BraceAssertion:Paper\n  \n \n \n \"BraceAssertion: link\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n  \n \n abstract \n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n \n \n \n \n\n\n\n
\n
@inproceedings{mass-Zheng-15,\n  author    = {Xi Zheng and\n               Christine Julien and\n               {Rodion M.} Podorozhny and\n               Franck Cassez},\n  title     = {BraceAssertion: Runtime Verification of Cyber-Physical Systems},\n  booktitle = {12th {IEEE} International Conference on Mobile Ad Hoc and Sensor Systems,\n               {MASS} 2015, Dallas, TX, USA, October 19-22, 2015},\n  pages     = {298--306},\n  year      = {2015},\n  urlpaper = {papers/mass-2015.pdf},\n  url_link       = {http://dx.doi.org/10.1109/MASS.2015.15},\n  doi       = {10.1109/MASS.2015.15},\n  timestamp = {Fri, 06 May 2016 13:36:43 +0200},\n  biburl    = {http://dblp.uni-trier.de/rec/bib/conf/mass/ZhengJPC15},\n  bibsource = {dblp computer science bibliography, http://dblp.org},\n  show = {},\n  keywords = {wcet, timed automata},\n\n  abstract={Cyber-Physical Systems (CPS) have gained wide popularity, however, developing and debugging CPS remain significant challenges. Many bugs are detectable only at runtime under deployment conditions that may be unpredictable or at least unexpected at development time. The current state of the practice of debugging CPS is generally ad hoc, involving trial and error in a real deployment. For increased rigor, it is appealing to bring formal methods to CPS verification. However developers often eschew formal approaches due to complexity and lack of efficiency. This paper presents Brace Assertion, a specification framework based on natural language queries that are automatically converted to a determinitic class of timed automata used for runtime monitoring. To reduce runtime overhead and support properties that reference predicate logic, we use a second monitor automaton to create filtered traces on which to run the analysis using the specification monitor. We evaluate the Brace Assertion framework using a real CPS case study and show that the framework is able to minimize runtime overhead with an increasing number of monitors.},\n  Type = {B - International Conferences},\n\n}\n\n
\n
\n\n\n
\n Cyber-Physical Systems (CPS) have gained wide popularity, however, developing and debugging CPS remain significant challenges. Many bugs are detectable only at runtime under deployment conditions that may be unpredictable or at least unexpected at development time. The current state of the practice of debugging CPS is generally ad hoc, involving trial and error in a real deployment. For increased rigor, it is appealing to bring formal methods to CPS verification. However developers often eschew formal approaches due to complexity and lack of efficiency. This paper presents Brace Assertion, a specification framework based on natural language queries that are automatically converted to a determinitic class of timed automata used for runtime monitoring. To reduce runtime overhead and support properties that reference predicate logic, we use a second monitor automaton to create filtered traces on which to run the analysis using the specification monitor. We evaluate the Brace Assertion framework using a real CPS case study and show that the framework is able to minimize runtime overhead with an increasing number of monitors.\n
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\n \n\n \n \n \n \n \n \n Timed Automata for Modelling Caches and Pipelines.\n \n \n \n \n\n\n \n Cassez, F.; and de Aledo Marugán, P. G.\n\n\n \n\n\n\n In van Glabbeek, R. J.; Groote, J. F.; and Höfner, P., editor(s), Proceedings Workshop on Models for Formal Analysis of Real Systems, MARS 2015, Suva, Fiji, November 23, 2015., volume 196, of EPTCS, pages 37–45, 2015. \n \n\n\n\n
\n\n\n\n \n \n \"Timed link\n  \n \n \n \"TimedSlides\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n  \n \n abstract \n \n\n \n  \n \n 1 download\n \n \n\n \n \n \n \n \n \n \n\n  \n \n \n \n \n \n \n\n\n\n
\n
@inproceedings{cassez-mars-2015,\n  author    = {Franck Cassez and\n               Pablo Gonz{\\'{a}}lez de Aledo Marug{\\'{a}}n},\n  title     = {Timed Automata for Modelling Caches and Pipelines},\n  booktitle = {Proceedings Workshop on Models for Formal Analysis of Real Systems,\n               {MARS} 2015, Suva, Fiji, November 23, 2015.},\n  pages     = {37--45},\n  year      = {2015},\n   editor    = {Rob J. van Glabbeek and\n               Jan Friso Groote and\n               Peter H{\\"{o}}fner},\n                series    = {{EPTCS}},\n  volume    = {196},\n  year      = {2015},\n  url_link       = {http://dx.doi.org/10.4204/EPTCS.196.4},\n    urlslides = {papers/slides-mars-2015.pdf},\n  doi       = {10.4204/EPTCS.196.4},\n  category= {wcet},\n  mywebpage = {wcet},\n  show = {},\n  keywords = {wcet, timed automata},\n  abstract = {\n  In this paper, we focus on modelling the timing aspects of binary programs running on architectures featuring caches and pipelines. The objective is to obtain a timed automaton model to compute tight bounds for the worst-case execution time (WCET) of the programs using model-checking techniques.\n  },\n  Type = {B - International Conferences},\n}\n\n
\n
\n\n\n
\n In this paper, we focus on modelling the timing aspects of binary programs running on architectures featuring caches and pipelines. The objective is to obtain a timed automaton model to compute tight bounds for the worst-case execution time (WCET) of the programs using model-checking techniques. \n
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\n  \n 2013\n \n \n (1)\n \n \n
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\n \n\n \n \n \n \n \n \n Timing Analysis of Binary Programs with UPPAAL.\n \n \n \n \n\n\n \n Cassez, F.; and Béchennec, J.\n\n\n \n\n\n\n In 13th International Conference on Application of Concurrency to System Design, ACSD 2013, pages 41-50, July 2013. IEEE Computer Society\n \n\n\n\n
\n\n\n\n \n \n \"TimingPaper\n  \n \n \n \"TimingSlides\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n  \n \n abstract \n \n\n \n  \n \n 3 downloads\n \n \n\n \n \n \n \n \n \n \n\n  \n \n \n \n \n \n \n\n\n\n
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@inproceedings{cassez-acsd-13,\n  author    = {Franck Cassez and\n               {Jean-Luc} Béchennec},\n  title     = {Timing Analysis of Binary Programs with {UPPAAL}},\n  booktitle = {13th International Conference on Application of Concurrency\n               to System Design, ACSD 2013},\n  year      = {2013},\n  month = jul,\n  pages     = {41-50},\n    PUBLISHER = {IEEE Computer Society},\n  urlpaper = {papers/acsd-2013.pdf},\n  urlslides = {papers/slides-acsd-wcet-2013.pdf},\n  doi       = {http://dx.doi.org/10.1109/ACSD.2013.7},\n  mywebpage = {wcet},\n  show = {},\n  keywords = {wcet, timed automata},\n  abstract = {\n  We address the problem of computing accurate Worst-Case Execution Time (WCET). We propose a fully automatic and modular methodology based on program slicing and real-time model-checking. We have implemented our methodology and applied it to standard benchmarks. To further validate the approach, we also compare our results to the real execution times of the programs measured on a real board.\n  },\n      Type = {B - International Conferences},\n\n}\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n%%% 2012\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\n
\n
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\n We address the problem of computing accurate Worst-Case Execution Time (WCET). We propose a fully automatic and modular methodology based on program slicing and real-time model-checking. We have implemented our methodology and applied it to standard benchmarks. To further validate the approach, we also compare our results to the real execution times of the programs measured on a real board. \n
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\n  \n 2012\n \n \n (1)\n \n \n
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\n \n\n \n \n \n \n \n \n What is a Timing Anomaly?.\n \n \n \n \n\n\n \n Cassez, F.; Hansen, R. R.; and Olesen, M. C.\n\n\n \n\n\n\n In 12th International Workshop on Worst-Case Execution Time Analysis, WCET 2012, July 10, 2012, Pisa, Italy, volume 23, of OASICS, pages 1-12, 2012. Schloss Dagstuhl - Leibniz-Zentrum fuer Informatik\n \n\n\n\n
\n\n\n\n \n \n \"WhatPaper\n  \n \n \n \"What link\n  \n \n\n \n\n \n link\n  \n \n\n bibtex\n \n\n \n  \n \n abstract \n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n \n \n\n\n\n
\n
@inproceedings{wcet-12,\n  author    = {Franck Cassez and\n               René Rydhof Hansen and\n               Mads Chr. Olesen},\n  title     = {What is a Timing Anomaly?},\n  booktitle = {12th International Workshop on Worst-Case Execution Time\n               Analysis, WCET 2012, July 10, 2012, Pisa, Italy},\n  year      = {2012},\n  pages     = {1-12},\n  urlpaper = {papers/wcet-2012.pdf},\n  url_link        = {http://dx.doi.org/10.4230/OASIcs.WCET.2012.1},\n  abstract = {Timing anomalies make worst-case execution time analysis much harder, because the analysis will have to consider all local choices. It has been widely recognised that certain hardware features are timing anomalous, while others are not. However, defining formally what a timing anomaly is, has been difficult. We examine previous definitions of timing anomalies, and identify examples where they do not align with common observations. We then provide a definition for consistently slower hardware traces that can be used to define timing anomalies and aligns with common observations.},\n  category= {wcet},\n  mywebpage = {soft-verif,wcet},\n  keywords = {wcet},\n   publisher = {Schloss Dagstuhl - Leibniz-Zentrum fuer Informatik},\n  series    = {OASICS},\n  volume    = {23},\n        Type = {B - International Conferences},\n\n}\n\n\n
\n
\n\n\n
\n Timing anomalies make worst-case execution time analysis much harder, because the analysis will have to consider all local choices. It has been widely recognised that certain hardware features are timing anomalous, while others are not. However, defining formally what a timing anomaly is, has been difficult. We examine previous definitions of timing anomalies, and identify examples where they do not align with common observations. We then provide a definition for consistently slower hardware traces that can be used to define timing anomalies and aligns with common observations.\n
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\n  \n 2011\n \n \n (2)\n \n \n
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\n \n\n \n \n \n \n \n \n Timed Games for Computing WCET for Pipelined Processors with Caches.\n \n \n \n \n\n\n \n Cassez, F.\n\n\n \n\n\n\n In 11th International Conference on Application of Concurrency to System Design, ACSD 2011, Newcastle Upon Tyne, UK, 20-24 June, 2011, pages 195–204, 2011. IEEE\n \n\n\n\n
\n\n\n\n \n \n \"TimedPaper\n  \n \n \n \"TimedSlides\n  \n \n \n \"TimedLink\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n  \n \n abstract \n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n \n \n \n \n\n\n\n
\n
@inproceedings{cassez-acsd-2011,\n  author    = {Franck Cassez},\n  title     = {Timed Games for Computing {WCET} for Pipelined Processors with Caches},\n  booktitle = {11th International Conference on Application of Concurrency to System\n               Design, {ACSD} 2011, Newcastle Upon Tyne, UK, 20-24 June, 2011},\n  pages     = {195--204},\n  year      = {2011},\n  publisher = {{IEEE}},\n  url       = {http://doi.ieeecomputersociety.org/10.1109/ACSD.2011.15},\n  doi       = {10.1109/ACSD.2011.15},\n  timestamp = {Wed, 15 Feb 2012 09:59:43 +0100},\n  biburl    = {http://dblp.uni-trier.de/rec/bib/conf/acsd/Cassez11},\n  bibsource = {dblp computer science bibliography, http://dblp.org},\n   urlpaper = {papers/acsd-2011.pdf},\n  urlslides = {papers/slides-acsd-2011.pdf},\n  ABSTRACT = {In this paper we introduce a framework for computing upper bounds yet\naccurate WCET for hardware platforms with caches and pipelines. The methodology\nwe propose consists of 3 steps: 1) given a program to analyse, compute an\nequivalent (WCET-wise) abstract program; 2) build a timed game by composing\nthis abstract program with a network of timed automata modeling the\narchitecture; and 3) compute the WCET as the optimal time to reach a winning\nstate in this game. We demonstrate the applicability of our framework on\nstandard benchmarks for an ARM9 processor with instruction and data caches, and\ncompute the WCET with UPPAAL-TiGA. We also show that this framework can easily\nbe extended to take into account dynamic changes in the speed of the processor\nduring program execution.\n},\nee       = {http://dx.doi.org/10.1109/ACSD.2011.15},\n  keywords = {wcet, timed automata},\n  category = {wcet},\n  show = {},\n  category= {wcet},\n  mywebpage = {wcet},\n        Type = {B - International Conferences},\n\n}\n\n\n
\n
\n\n\n
\n In this paper we introduce a framework for computing upper bounds yet accurate WCET for hardware platforms with caches and pipelines. The methodology we propose consists of 3 steps: 1) given a program to analyse, compute an equivalent (WCET-wise) abstract program; 2) build a timed game by composing this abstract program with a network of timed automata modeling the architecture; and 3) compute the WCET as the optimal time to reach a winning state in this game. We demonstrate the applicability of our framework on standard benchmarks for an ARM9 processor with instruction and data caches, and compute the WCET with UPPAAL-TiGA. We also show that this framework can easily be extended to take into account dynamic changes in the speed of the processor during program execution. \n
\n\n\n
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\n \n\n \n \n \n \n \n \n Computation of WCET using Program Slicing and Real-Time Model-Checking.\n \n \n \n \n\n\n \n Béchennec, J.; and Cassez, F.\n\n\n \n\n\n\n CoRR, abs/1105.1633. 2011.\n \n\n\n\n
\n\n\n\n \n \n \"ComputationPaper\n  \n \n\n \n\n \n link\n  \n \n\n bibtex\n \n\n \n  \n \n abstract \n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n \n \n \n \n\n\n\n
\n
@article{bech-wcet-2011,\n  author    = {Jean{-}Luc B{\\'{e}}chennec and\n               Franck Cassez},\n  title     = {Computation of {WCET} using Program Slicing and Real-Time Model-Checking},\n  journal   = {CoRR},\n  Type = {E - Reports},\n  volume    = {abs/1105.1633},\n  year      = {2011},\n  urlpaper       = {http://arxiv.org/abs/1105.1633},\n  timestamp = {Mon, 05 Dec 2011 18:05:32 +0100},\n  biburl    = {http://dblp.uni-trier.de/rec/bib/journals/corr/abs-1105-1633},\n  bibsource = {dblp computer science bibliography, http://dblp.org},\n  ABSTRACT = { Computing accurate WCET on modern complex architectures is a challenging task. This problem has been devoted a lot of attention in the last decade but there are still some open issues. First, the control flow graph (CFG) of a binary program is needed to compute the WCET and this CFG is built using some internal knowledge of the compiler that generated the binary code; moreover once constructed the CFG has to be manually annotated with loop bounds. Second, the algorithms to compute the WCET (combining Abstract Interpretation and Integer Linear Programming) are tailored for specific architectures: changing the architecture (e.g. replacing an ARM7 by an ARM9) requires the design of a new ad hoc algorithm. Third, the tightness of the computed results (obtained using the available tools) are not compared to actual execution times measured on the real hardware. In this paper we address the above mentioned problems. We first describe a fully automatic method to compute a CFG based solely on the binary program to analyse. Second, we describe the model of the hardware as a product of timed automata, and this model is independent from the program description. The model of a program running on a hardware is obtained by synchronizing (the automaton of) the program with the (timed automata) model of the hardware. Computing the WCET is reduced to a reachability problem on the synchronised model and solved using the model-checker UPPAAL. Finally, we present a rigorous methodology that enables us to compare our computed results to actual execution times measured on a real platform, the ARM920T.},\n    category= {wcet},\n  keywords = {wcet, timed automata},\n  show = {},\n  mywebpage = {wcet}\n}\n\n
\n
\n\n\n
\n Computing accurate WCET on modern complex architectures is a challenging task. This problem has been devoted a lot of attention in the last decade but there are still some open issues. First, the control flow graph (CFG) of a binary program is needed to compute the WCET and this CFG is built using some internal knowledge of the compiler that generated the binary code; moreover once constructed the CFG has to be manually annotated with loop bounds. Second, the algorithms to compute the WCET (combining Abstract Interpretation and Integer Linear Programming) are tailored for specific architectures: changing the architecture (e.g. replacing an ARM7 by an ARM9) requires the design of a new ad hoc algorithm. Third, the tightness of the computed results (obtained using the available tools) are not compared to actual execution times measured on the real hardware. In this paper we address the above mentioned problems. We first describe a fully automatic method to compute a CFG based solely on the binary program to analyse. Second, we describe the model of the hardware as a product of timed automata, and this model is independent from the program description. The model of a program running on a hardware is obtained by synchronizing (the automaton of) the program with the (timed automata) model of the hardware. Computing the WCET is reduced to a reachability problem on the synchronised model and solved using the model-checker UPPAAL. Finally, we present a rigorous methodology that enables us to compare our computed results to actual execution times measured on a real platform, the ARM920T.\n
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\n  \n 2010\n \n \n (1)\n \n \n
\n
\n \n \n
\n \n\n \n \n \n \n \n \n Timed Games for Computing Worst-Case Execution-Times.\n \n \n \n \n\n\n \n Cassez, F.\n\n\n \n\n\n\n CoRR, abs/1006.1951. 2010.\n \n\n\n\n
\n\n\n\n \n \n \"TimedPaper\n  \n \n\n \n\n \n link\n  \n \n\n bibtex\n \n\n \n  \n \n abstract \n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n \n \n \n \n\n\n\n
\n
@article{DBLP:journals/corr/abs-1006-1951,\n  author    = {Franck Cassez},\n  title     = {Timed Games for Computing Worst-Case Execution-Times},\n  journal   = {CoRR},\n  Type = {E - Reports},\n  volume    = {abs/1006.1951},\n  year      = {2010},\n  url       = {http://arxiv.org/abs/1006.1951},\n  timestamp = {Mon, 05 Dec 2011 18:04:54 +0100},\n  biburl    = {http://dblp.uni-trier.de/rec/bib/journals/corr/abs-1006-1951},\n  bibsource = {dblp computer science bibliography, http://dblp.org},\n    keywords = {wcet, timed automata},\n\n  abstract= {In this paper we introduce a framework for computing upper bounds yet accurate WCET for hardware platforms with caches and pipelines. The methodology we propose consists of 3 steps: 1) given a program to analyse, compute an equivalent (WCET-wise) abstract program; 2) build a timed game by composing this abstract program with a network of timed automata modeling the architecture; and 3) compute the WCET as the optimal time to reach a winning state in this game. We demonstrate the applicability of our framework on standard benchmarks for an ARM9 processor with instruction and data caches, and compute the WCET with UPPAAL-TiGA. We also show that this framework can easily be extended to take into account dynamic changes in the speed of the processor during program execution.}\n}\n\n\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n%%% 2009\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\n
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\n In this paper we introduce a framework for computing upper bounds yet accurate WCET for hardware platforms with caches and pipelines. The methodology we propose consists of 3 steps: 1) given a program to analyse, compute an equivalent (WCET-wise) abstract program; 2) build a timed game by composing this abstract program with a network of timed automata modeling the architecture; and 3) compute the WCET as the optimal time to reach a winning state in this game. We demonstrate the applicability of our framework on standard benchmarks for an ARM9 processor with instruction and data caches, and compute the WCET with UPPAAL-TiGA. We also show that this framework can easily be extended to take into account dynamic changes in the speed of the processor during program execution.\n
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