Optimizing Stresses for Testing DRAM Cell Defects Using Electrical Simulation. Al-Ars, Z., van de Goor, A. J., Braun, J., & Richter, D. In DATE, pages 10484-10489, 2003. IEEE Computer Society.
Optimizing Stresses for Testing DRAM Cell Defects Using Electrical Simulation. [link]Link  Optimizing Stresses for Testing DRAM Cell Defects Using Electrical Simulation. [link]Paper  bibtex   
@inproceedings{conf/date/Al-ArsGBR03,
  added-at = {2023-03-24T00:00:00.000+0100},
  author = {Al-Ars, Zaid and van de Goor, Ad J. and Braun, Jens and Richter, Detlev},
  biburl = {https://www.bibsonomy.org/bibtex/24a97e14db00cc1dfac518c54c653ed5a/dblp},
  booktitle = {DATE},
  crossref = {conf/date/2003},
  ee = {http://dl.acm.org/citation.cfm?id=1022774},
  interhash = {f47b082e884122d97ce4c445bcef59aa},
  intrahash = {4a97e14db00cc1dfac518c54c653ed5a},
  isbn = {0-7695-1870-2},
  keywords = {dblp},
  pages = {10484-10489},
  publisher = {IEEE Computer Society},
  timestamp = {2024-04-10T06:54:02.000+0200},
  title = {Optimizing Stresses for Testing DRAM Cell Defects Using Electrical Simulation.},
  url = {http://dblp.uni-trier.de/db/conf/date/date2003.html#Al-ArsGBR03},
  year = 2003
}

Downloads: 0