Xpipes: A latency insensitive parameterized network-on-chip architecture for multi-processor SoCs. Dall'Osso, M., Biccari, G., Giovannini, L., Bertozzi, D., & Benini, L. In 30th International IEEE Conference on Computer Design, ICCD 2012, Montreal, QC, Canada, September 30 - Oct. 3, 2012, pages 45–48, 2012.
Xpipes: A latency insensitive parameterized network-on-chip architecture for multi-processor SoCs [link]Paper  doi  bibtex   
@inproceedings{DBLP:conf/iccd/DallOssoBGBB12,
  author    = {Matteo Dall'Osso and
               Gianluca Biccari and
               Luca Giovannini and
               Davide Bertozzi and
               Luca Benini},
  title     = {Xpipes: {A} latency insensitive parameterized network-on-chip architecture
               for multi-processor SoCs},
  booktitle = {30th International {IEEE} Conference on Computer Design, {ICCD} 2012,
               Montreal, QC, Canada, September 30 - Oct. 3, 2012},
  pages     = {45--48},
  year      = {2012},
  crossref  = {DBLP:conf/iccd/2012},
  url       = {http://dx.doi.org/10.1109/ICCD.2012.6378615},
  doi       = {10.1109/ICCD.2012.6378615},
  timestamp = {Mon, 22 Sep 2014 16:50:06 +0200},
  biburl    = {http://dblp.uni-trier.de/rec/bib/conf/iccd/DallOssoBGBB12},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}

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