A parallel parsing VLSI architecture for arbitrary context free grammars. Koulouris, A., Koziris, N., Andronikos, T., PapaKonstantinou, G., & Tsanakas, P. In Parallel and Distributed Systems, 1998. Proceedings. 1998 International Conference on, pages 783 – 790, dec, 1998.
doi  bibtex   
@InProceedings{koulouris_parallel_1998,
	title = {A parallel parsing {VLSI} architecture for arbitrary context free grammars},
	doi = {10.1109/ICPADS.1998.741168},
	booktitle = {Parallel and Distributed Systems, 1998. Proceedings. 1998 International Conference on},
	author = {Koulouris, A. and Koziris, N. and Andronikos, T. and {PapaKonstantinou}, G. and Tsanakas, P.},
	month = {dec},
	year = {1998},
	keywords = {{1D} array, arbitrary context free grammars, {CF} grammars, computational complexity, Computer architecture, Concurrent computing, context-free grammars, Delay, Dynamic programming, Earley algorithm, equivalent double nested loop, fixed size one dimensional {VLSI} architecture, Laboratories, loop carried dependencies, Natural languages, off the shelf processing elements, Parallel architectures, parallel parsing {VLSI} architecture, parallel programming, Partitioning algorithms, partitioning strategies, Pattern recognition, program control structures, Systolic arrays, time complexity, Very large scale integration, {VLSI}},
	pages = {783 -- 790}
}

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