Automatic hardware synthesis of nested loops using UET grids and VHDL. Koziris, N., Andronikos, T., Economakos, G., Papakonstantinou, G., & Tsanakas, P. In Hertzberger, B. & Sloot, P., editors, High-Performance Computing and Networking, volume 1225, of Lecture Notes in Computer Science, pages 888 -- 897. Springer Berlin Heidelberg, 1997.
Automatic hardware synthesis of nested loops using UET grids and VHDL [link]Paper  bibtex   
@InCollection{hertzberger_automatic_1997,
	series = {Lecture Notes in Computer Science},
	title = {Automatic hardware synthesis of nested loops using {UET} grids and {VHDL}},
	volume = {1225},
	isbn = {978-3-540-62898-9},
	url = {http://dx.doi.org/10.1007/BFb0031660},
	booktitle = {High-Performance Computing and Networking},
	publisher = {Springer Berlin Heidelberg},
	author = {Koziris, Nectarios and Andronikos, Theodore and Economakos, George and Papakonstantinou, George and Tsanakas, Panayotis},
	editor = {Hertzberger, Bob and Sloot, Peter},
	year = {1997},
	keywords = {number of systolic cells, optimal makespan, optimal mapping, {UET} grid index space, uniform unit dependence vectors, {VHDL} based design automation},
	pages = {888 -- 897}
}

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