Automatic hardware synthesis of nested loops using UET grids and VHDL. Koziris, N., Andronikos, T., Economakos, G., Papakonstantinou, G., & Tsanakas, P. In Hertzberger, B. & Sloot, P., editors, High-Performance Computing and Networking, volume 1225, of Lecture Notes in Computer Science, pages 888 – 897. Springer Berlin Heidelberg, 1997. Paper bibtex @InCollection{hertzberger_automatic_1997,
series = {Lecture Notes in Computer Science},
title = {Automatic hardware synthesis of nested loops using {UET} grids and {VHDL}},
volume = {1225},
isbn = {978-3-540-62898-9},
url = {http://dx.doi.org/10.1007/BFb0031660},
booktitle = {High-Performance Computing and Networking},
publisher = {Springer Berlin Heidelberg},
author = {Koziris, Nectarios and Andronikos, Theodore and Economakos, George and Papakonstantinou, George and Tsanakas, Panayotis},
editor = {Hertzberger, Bob and Sloot, Peter},
year = {1997},
keywords = {number of systolic cells, optimal makespan, optimal mapping, {UET} grid index space, uniform unit dependence vectors, {VHDL} based design automation},
pages = {888 -- 897}
}
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{"_id":{"_str":"538590720e577e1d6b00230f"},"__v":65,"authorIDs":["54658f19bc7d6a460d0005a8"],"author_short":["Koziris, N.","Andronikos, T.","Economakos, G.","Papakonstantinou, G.","Tsanakas, P."],"bibbaseid":"koziris-andronikos-economakos-papakonstantinou-tsanakas-automatichardwaresynthesisofnestedloopsusinguetgridsandvhdl-1997","bibdata":{"bibtype":"incollection","type":"incollection","series":"Lecture Notes in Computer Science","title":"Automatic hardware synthesis of nested loops using UET grids and VHDL","volume":"1225","isbn":"978-3-540-62898-9","url":"http://dx.doi.org/10.1007/BFb0031660","booktitle":"High-Performance Computing and Networking","publisher":"Springer Berlin Heidelberg","author":[{"propositions":[],"lastnames":["Koziris"],"firstnames":["Nectarios"],"suffixes":[]},{"propositions":[],"lastnames":["Andronikos"],"firstnames":["Theodore"],"suffixes":[]},{"propositions":[],"lastnames":["Economakos"],"firstnames":["George"],"suffixes":[]},{"propositions":[],"lastnames":["Papakonstantinou"],"firstnames":["George"],"suffixes":[]},{"propositions":[],"lastnames":["Tsanakas"],"firstnames":["Panayotis"],"suffixes":[]}],"editor":[{"propositions":[],"lastnames":["Hertzberger"],"firstnames":["Bob"],"suffixes":[]},{"propositions":[],"lastnames":["Sloot"],"firstnames":["Peter"],"suffixes":[]}],"year":"1997","keywords":"number of systolic cells, optimal makespan, optimal mapping, UET grid index space, uniform unit dependence vectors, VHDL based design automation","pages":"888 – 897","bibtex":"@InCollection{hertzberger_automatic_1997,\n\tseries = {Lecture Notes in Computer Science},\n\ttitle = {Automatic hardware synthesis of nested loops using {UET} grids and {VHDL}},\n\tvolume = {1225},\n\tisbn = {978-3-540-62898-9},\n\turl = {http://dx.doi.org/10.1007/BFb0031660},\n\tbooktitle = {High-Performance Computing and Networking},\n\tpublisher = {Springer Berlin Heidelberg},\n\tauthor = {Koziris, Nectarios and Andronikos, Theodore and Economakos, George and Papakonstantinou, George and Tsanakas, Panayotis},\n\teditor = {Hertzberger, Bob and Sloot, Peter},\n\tyear = {1997},\n\tkeywords = {number of systolic cells, optimal makespan, optimal mapping, {UET} grid index space, uniform unit dependence vectors, {VHDL} based design automation},\n\tpages = {888 -- 897}\n}\n\n","author_short":["Koziris, N.","Andronikos, T.","Economakos, G.","Papakonstantinou, G.","Tsanakas, P."],"editor_short":["Hertzberger, B.","Sloot, P."],"key":"hertzberger_automatic_1997","id":"hertzberger_automatic_1997","bibbaseid":"koziris-andronikos-economakos-papakonstantinou-tsanakas-automatichardwaresynthesisofnestedloopsusinguetgridsandvhdl-1997","role":"author","urls":{"Paper":"http://dx.doi.org/10.1007/BFb0031660"},"keyword":["number of systolic cells","optimal makespan","optimal mapping","UET grid index space","uniform unit dependence vectors","VHDL based design automation"],"metadata":{"authorlinks":{}}},"bibtype":"incollection","biburl":"http://www.ionio.gr/~andronikos/andron.bib","downloads":0,"keywords":["number of systolic cells","optimal makespan","optimal mapping","uet grid index space","uniform unit dependence vectors","vhdl based design automation"],"search_terms":["automatic","hardware","synthesis","nested","loops","using","uet","grids","vhdl","koziris","andronikos","economakos","papakonstantinou","tsanakas"],"title":"Automatic hardware synthesis of nested loops using UET grids and VHDL","year":1997,"dataSources":["gXaEZgfAnH6LvDp7P"]}