@InProceedings{koziris_optimal_1997,
	title = {Optimal automatic hardware synthesis for signal processing algorithms},
	volume = {2},
	doi = {10.1109/ICDSP.1997.628535},
	booktitle = {Digital Signal Processing Proceedings, 1997. {DSP} 97., 1997 13th International Conference on},
	author = {Koziris, N. and Economakos, G. and Andronikos, T. and {PapaKonstantinou}, G. and Tsanakas, P.},
	month = {jul},
	year = {1997},
	keywords = {Algorithm design and analysis, algorithmic specifications, circuit layout {CAD}, circuit optimisation, communication elements, computation elements, Computer architecture, Digital signal processing, digital signal processing chips, generalized {UET} grids, Hardware, hardware description languages, high level signal processing, integrated software package, low-level optimal implementation, nested loop, optimal automatic hardware synthesis, optimal layouts, optimal makespan, parallel algorithms, parallel design environment, Processor scheduling, scheduling policy, Signal design, Signal processing, Signal processing algorithms, Signal synthesis, software packages, Systolic arrays, systolic cells, unit uniform loop carried dependencies, utility program, Very large scale integration, {VHDL}, {VLSI}, {VLSI} architectures},
	pages = {1011 -- 1014 vol.2}
}

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