Static analysis for VHDL model evaluation. Stefanoni, M. In EURO-DAC, pages 586-591, 1994. IEEE Computer Society.
Static analysis for VHDL model evaluation. [link]Link  Static analysis for VHDL model evaluation. [link]Paper  bibtex   
@inproceedings{conf/eurodac/Stefanoni94,
  added-at = {2015-11-11T00:00:00.000+0100},
  author = {Stefanoni, Mario},
  biburl = {http://www.bibsonomy.org/bibtex/219406fd1a6dfbf2a21a008f9e5d2ef24/dblp},
  booktitle = {EURO-DAC},
  crossref = {conf/eurodac/1994},
  editor = {Mermet, Jean},
  ee = {http://dl.acm.org/citation.cfm?id=198333},
  interhash = {cb4b868e1773b0f6f69c70285599d48c},
  intrahash = {19406fd1a6dfbf2a21a008f9e5d2ef24},
  isbn = {0-89791-685-9},
  keywords = {dblp},
  pages = {586-591},
  publisher = {IEEE Computer Society},
  timestamp = {2015-11-13T11:50:31.000+0100},
  title = {Static analysis for VHDL model evaluation.},
  url = {http://dblp.uni-trier.de/db/conf/eurodac/euro-dac1994.html#Stefanoni94},
  year = 1994
}
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