@inproceedings{
 title = {Intensifying Challenge Obfuscation by Cascading RO-PUFs for Random Number Generation (Conditionally Accepted)},
 type = {inproceedings},
 year = {2020},
 pages = {6},
 id = {3c282cf8-f768-37c7-b32c-fa7923c3937f},
 created = {2019-11-02T03:28:48.629Z},
 file_attached = {true},
 profile_id = {03d2ca17-6bde-3cfe-95de-fcbe4f21507b},
 last_modified = {2019-11-02T03:33:49.951Z},
 read = {false},
 starred = {false},
 authored = {true},
 confirmed = {false},
 hidden = {false},
 source_type = {Inproceedings},
 private_publication = {false},
 bibtype = {inproceedings},
 author = {Chauhan, Arjun Singh and Sahula, Vineet and Mandal, A S and Dutta, Abhigyan},
 booktitle = {IEEE 33rd International Conference on VLSI Design (Bengaluru, INDIA)}
}

@article{
 title = {An In-Depth Study on Electrical and Hydrogen Sensing Characteristics of ZnO Thin Film with Radio Frequency Sputtered Gold Schottky Contacts},
 type = {article},
 year = {2019},
 keywords = {Schottky diodes;Zinc oxide;Sensors;II-VI semiconductor materials;Hydrogen;Temperature;Gold;Electrical characteristics;Hydrogen sensing;Metal-semiconductor interface Palladium catalyst;Schottky diode;Zinc oxide (ZnO) thin film},
 pages = {1},
 volume = {19},
 websites = {https://ieeexplore.ieee.org/abstract/document/8616789},
 month = {5},
 id = {dbfac907-686c-3482-9b80-41f920138738},
 created = {2019-11-02T03:28:48.497Z},
 file_attached = {false},
 profile_id = {03d2ca17-6bde-3cfe-95de-fcbe4f21507b},
 last_modified = {2019-11-02T03:29:22.539Z},
 read = {false},
 starred = {false},
 authored = {true},
 confirmed = {false},
 hidden = {false},
 source_type = {Article},
 private_publication = {false},
 abstract = {Electrical and hydrogen sensing characteristics of radio frequency sputtered Au/ZnO thin film Schottky diodes on n-silicon substrate have been investigated over a wide temperature range. Current-voltage characterizations of the device in the temperature range of 25°C to 200°C confirm its excellent rectifying property with forward to reverse current ratio of 1610 at an external bias of 5 V. Ideality factor in the range of 4.12 to 2.98 is obtained for Au/ZnO Schottky diode in the aforementioned temperature range, at atmospheric conditions. On exposing diode to hydrogen, a reduction in ideality factor is observed which makes thermionic emission more prominent. The proposed device has proven to be hydrogen sensitive, on account of the lateral shift observed in I –V characteristics at different hydrogen concentrations (50 ppm-1000 ppm). Maximum barrier height variation of 99 meV and sensitivity of 144% have been observed at 1000 ppm hydrogen at 200°C. A Detailed perusal of the steady-state reaction kinetics of the sensor using I – V characteristics affirmed that the atomistic hydrogen adsorption at Au/ZnO interface is accountable for the barrier height modulation. The studied sensor depicts remarkable performance for high-temperature detection.},
 bibtype = {article},
 author = {Rajan, L and Periasamy, C and Sahula, V},
 doi = {https://doi.org/10.1109/JSEN.2019.2893025},
 journal = {IEEE Sensors Journal},
 number = {9}
}

Electrical and hydrogen sensing characteristics of radio frequency sputtered Au/ZnO thin film Schottky diodes on n-silicon substrate have been investigated over a wide temperature range. Current-voltage characterizations of the device in the temperature range of 25°C to 200°C confirm its excellent rectifying property with forward to reverse current ratio of 1610 at an external bias of 5 V. Ideality factor in the range of 4.12 to 2.98 is obtained for Au/ZnO Schottky diode in the aforementioned temperature range, at atmospheric conditions. On exposing diode to hydrogen, a reduction in ideality factor is observed which makes thermionic emission more prominent. The proposed device has proven to be hydrogen sensitive, on account of the lateral shift observed in I –V characteristics at different hydrogen concentrations (50 ppm-1000 ppm). Maximum barrier height variation of 99 meV and sensitivity of 144% have been observed at 1000 ppm hydrogen at 200°C. A Detailed perusal of the steady-state reaction kinetics of the sensor using I – V characteristics affirmed that the atomistic hydrogen adsorption at Au/ZnO interface is accountable for the barrier height modulation. The studied sensor depicts remarkable performance for high-temperature detection.

@article{
 title = {Energy Efficient Lightweight Cryptography Algorithms for IoT Devices (Accepted)},
 type = {article},
 year = {2019},
 pages = {16},
 volume = {66},
 websites = {https://doi.org/10.1080/03772063.2019.1670103},
 id = {0bfc5feb-6fa2-3fb2-b995-7d042d11620b},
 created = {2019-11-02T03:28:48.506Z},
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 starred = {false},
 authored = {true},
 confirmed = {false},
 hidden = {false},
 source_type = {Article},
 private_publication = {false},
 bibtype = {article},
 author = {Goyal, Tarun and Sahula, Vineet and Kumawat, Deepak},
 doi = {10.1080/03772063.2019.1670103},
 journal = {IETE Journal of Research}
}

@article{
 title = {Equipartitioning Frequency Groups & Randomized Placement for Enhanced Uniqueness and Robustness in an FPGA-ROPUF based Random Sequence Generator (in Review)},
 type = {article},
 year = {2019},
 id = {5614a560-62e0-3327-bd0d-ea025b10aee4},
 created = {2019-11-02T03:28:48.572Z},
 file_attached = {false},
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 starred = {false},
 authored = {true},
 confirmed = {false},
 hidden = {false},
 source_type = {Article},
 private_publication = {false},
 bibtype = {article},
 author = {Chauhan, Arjun Singh and Sahula, Vineet and Mandal, Atanendu Shekhar},
 journal = {ACM Transactions on Reconfigurable Technology & Systems}
}

@article{
 title = {Novel Randomized Placement For FPGA Based Robust ROPUF with Improved Uniqueness},
 type = {article},
 year = {2019},
 volume = {35},
 websites = {https://link.springer.com/journal/10836},
 month = {10},
 id = {61751507-2b5c-3986-a32c-8299bc1384d2},
 created = {2019-11-02T03:28:48.619Z},
 file_attached = {true},
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 starred = {false},
 authored = {true},
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 source_type = {Article},
 private_publication = {false},
 bibtype = {article},
 author = {Chauhan, Arjun Singh and Sahula, Vineet and Mandal, A S},
 doi = {10.1007/s10836-019-05829-5},
 journal = {Springer's Journal of Electronic Testing: Theory and Applications},
 number = {5}
}

@inproceedings{
 title = {Novel randomized & biased placement for FPGA based robust random number generator with enhanced uniqueness},
 type = {inproceedings},
 year = {2019},
 keywords = {Biased Placement,FPGA,Index Terms—Hardware Security,NIST Statistical Test,PUF,Random Number Generator,Ring Oscillator},
 id = {15dfc505-5b31-3d01-a95a-bfa50dc4e3e9},
 created = {2019-06-17T23:59:00.000Z},
 file_attached = {false},
 profile_id = {03d2ca17-6bde-3cfe-95de-fcbe4f21507b},
 last_modified = {2020-12-25T10:46:28.549Z},
 read = {false},
 starred = {false},
 authored = {true},
 confirmed = {false},
 hidden = {false},
 private_publication = {false},
 abstract = {© 2019 IEEE. The physical unclonable functions (PUF) have widely been used to provide software as well as hardware security for the cyber-physical systems. They are used for performing significant cryptography tasks such as generating keys, device authentication and securing against IP piracy. They have also been used to produce the root of trust. However, they lack in reliability metric. We present a novel approach for improving the uniqueness as well as the reliability of field programmable gated arrays (FPGAs) based ring oscillator PUF and derive a random number, consuming a very small area concerning look up tables (LUTs). We use profiling method for observing frequency variations in ring oscillators (RO), spatially placed across the FPGA floor, and are able to spot the suitable locations for RO mapping, which leads to enhanced ROPUF reliability. We have implemented proposed methodology on Xilinx -7 series FPGAs and tested the robustness against environmental variations e.g. temperature and supply voltage variations. The proposed approach achieves 6% higher uniqueness of 49.83% along with the reliability of 99.35%, which as a group of PUF characteristics, is a significant improvement as compared to characteristics provided by existing ROPUF methods. The random number generator so realized passes all applicable nine tests of NIST uniformity statistical test suite.},
 bibtype = {inproceedings},
 author = {Chauhan, A.S. and Sahula, V. and Mandal, A.S.},
 doi = {10.1109/VLSID.2019.00079},
 booktitle = {Proceedings - 32nd International Conference on VLSI Design, VLSID 2019 - Held concurrently with 18th International Conference on Embedded Systems, ES 2019}
}

© 2019 IEEE. The physical unclonable functions (PUF) have widely been used to provide software as well as hardware security for the cyber-physical systems. They are used for performing significant cryptography tasks such as generating keys, device authentication and securing against IP piracy. They have also been used to produce the root of trust. However, they lack in reliability metric. We present a novel approach for improving the uniqueness as well as the reliability of field programmable gated arrays (FPGAs) based ring oscillator PUF and derive a random number, consuming a very small area concerning look up tables (LUTs). We use profiling method for observing frequency variations in ring oscillators (RO), spatially placed across the FPGA floor, and are able to spot the suitable locations for RO mapping, which leads to enhanced ROPUF reliability. We have implemented proposed methodology on Xilinx -7 series FPGAs and tested the robustness against environmental variations e.g. temperature and supply voltage variations. The proposed approach achieves 6% higher uniqueness of 49.83% along with the reliability of 99.35%, which as a group of PUF characteristics, is a significant improvement as compared to characteristics provided by existing ROPUF methods. The random number generator so realized passes all applicable nine tests of NIST uniformity statistical test suite.

@article{
 title = {Correction to: Novel Randomized Placement for FPGA Based Robust ROPUF with Improved Uniqueness (Journal of Electronic Testing, (2019), 35, 5, (581-601), 10.1007/s10836-019-05829-5)},
 type = {article},
 year = {2019},
 volume = {35},
 id = {7468db7f-520f-3dca-9181-55d798a8b11d},
 created = {2019-12-30T23:59:00.000Z},
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 read = {false},
 starred = {false},
 authored = {true},
 confirmed = {false},
 hidden = {false},
 private_publication = {true},
 abstract = {© 2019, Springer Science+Business Media, LLC, part of Springer Nature. The original article unfortunately contained a mistake. Corrections provided in a list form were not carried out.},
 bibtype = {article},
 author = {Chauhan, A.S. and Sahula, V. and Mandal, A.S.},
 doi = {10.1007/s10836-019-05849-1},
 journal = {Journal of Electronic Testing: Theory and Applications (JETTA)},
 number = {5}
}

© 2019, Springer Science+Business Media, LLC, part of Springer Nature. The original article unfortunately contained a mistake. Corrections provided in a list form were not carried out.

@inproceedings{
 title = {Device Design Space Exploration of Thin Film Hydrogen Sensor Based on Macro-model Generated Using Machine Learning},
 type = {inproceedings},
 year = {2019},
 volume = {2019-Octob},
 id = {14c695d1-f925-3807-9fe7-7b906a89f37b},
 created = {2020-02-06T23:59:00.000Z},
 file_attached = {false},
 profile_id = {03d2ca17-6bde-3cfe-95de-fcbe4f21507b},
 last_modified = {2021-03-06T09:07:58.644Z},
 read = {false},
 starred = {false},
 authored = {true},
 confirmed = {false},
 hidden = {false},
 private_publication = {true},
 abstract = {© 2019 IEEE. An efficient attempt has been performed towards device design optimization, using machine learning approach for exploration of design space of zinc oxide (ZnO) thin film Schottky diode based hydrogen sensor. We have adopted Least Square Support Vector Machine (LS-SVM) to build the regression model to predict the output behavior of ZnO thin film Schottky diode based hydrogen sensors. ATLAS package from SILVACO international has been used for generating data set, that is required to train the machine learning model. The hydrogen induced barrier height variations (Δφb) at a wide range of temperature (300 K to 575 K) and wide range of ZnO thin film thickness (5 nm to 300 nm) have been calculated, which was used used for training the regression model. It has been observed that the proposed modeling scheme can serve a guide for fabrication of ZnO thin film based Schottky diode for hydrogen sensing applications.},
 bibtype = {inproceedings},
 author = {Rajan, L. and Varghese, A. and Periasamy, C. and Sahula, V.},
 doi = {10.1109/SENSORS43011.2019.8956628},
 booktitle = {Proceedings of IEEE Sensors}
}

© 2019 IEEE. An efficient attempt has been performed towards device design optimization, using machine learning approach for exploration of design space of zinc oxide (ZnO) thin film Schottky diode based hydrogen sensor. We have adopted Least Square Support Vector Machine (LS-SVM) to build the regression model to predict the output behavior of ZnO thin film Schottky diode based hydrogen sensors. ATLAS package from SILVACO international has been used for generating data set, that is required to train the machine learning model. The hydrogen induced barrier height variations (Δφb) at a wide range of temperature (300 K to 575 K) and wide range of ZnO thin film thickness (5 nm to 300 nm) have been calculated, which was used used for training the regression model. It has been observed that the proposed modeling scheme can serve a guide for fabrication of ZnO thin film based Schottky diode for hydrogen sensing applications.

@inproceedings{
 title = {Novel Variability Aware Path Selection for Self-Referencing Based Hardware Trojan Detection},
 type = {inproceedings},
 year = {2018},
 keywords = {Hardware Trojan detection,Path delay,Process variation,Self-referencing},
 volume = {2018-Janua},
 city = {Pune, India},
 id = {604a2f39-710d-3f20-8d76-73148f1b7342},
 created = {2018-08-05T03:34:05.699Z},
 file_attached = {true},
 profile_id = {03d2ca17-6bde-3cfe-95de-fcbe4f21507b},
 last_modified = {2018-08-05T03:34:31.065Z},
 read = {false},
 starred = {false},
 authored = {true},
 confirmed = {true},
 hidden = {false},
 citation_key = {Ramakrishna2018},
 private_publication = {false},
 abstract = {© 2018 IEEE. Hardware Trojans can be inserted by an adversary at untrusted third-party fabrication houses. Many Side-channel analysis based detection techniques have been proposed in past to detect such Trojans. However, their efficiency is highly affected by process variations. Hardware Trojan (HT) inserted in an IC affects the path delays within the IC. In this work, we exploit the fact that the path delays of topologically symmetric paths in an IC will be affected similarly by process variations. We tend to choose paths that are minimally affected by process variations. In this paper, we propose a path selection technique for delay based HT detection technique. We further use the concept of self-referencing to improve detection accuracy as well as to eliminate the requirement of golden ICs. Simulations performed using ISCAS-85 benchmarks establish that the proposed method is achieving a true positive rate of 100% with a false positive rate less than 5%. We have considered maximum of 10% intra-die and 15% inter-die variations in threshold voltage (Vth).},
 bibtype = {inproceedings},
 author = {Ramakrishna, Vaikuntapu and Bhargava, Lava and Sahula, Vineet},
 doi = {10.1109/VLSID.2018.41},
 booktitle = {31st IEEE International Conference on VLSI Design}
}

© 2018 IEEE. Hardware Trojans can be inserted by an adversary at untrusted third-party fabrication houses. Many Side-channel analysis based detection techniques have been proposed in past to detect such Trojans. However, their efficiency is highly affected by process variations. Hardware Trojan (HT) inserted in an IC affects the path delays within the IC. In this work, we exploit the fact that the path delays of topologically symmetric paths in an IC will be affected similarly by process variations. We tend to choose paths that are minimally affected by process variations. In this paper, we propose a path selection technique for delay based HT detection technique. We further use the concept of self-referencing to improve detection accuracy as well as to eliminate the requirement of golden ICs. Simulations performed using ISCAS-85 benchmarks establish that the proposed method is achieving a true positive rate of 100% with a false positive rate less than 5%. We have considered maximum of 10% intra-die and 15% inter-die variations in threshold voltage (Vth).

@inproceedings{
 title = {Neural Machine Translation for English to Hindi},
 type = {inproceedings},
 year = {2018},
 institution = {Kota Kinabalu, Malaysia},
 id = {e2661ce1-66b7-321d-ab9f-718127f66e26},
 created = {2018-08-05T03:34:05.913Z},
 file_attached = {true},
 profile_id = {03d2ca17-6bde-3cfe-95de-fcbe4f21507b},
 last_modified = {2018-08-05T03:34:42.155Z},
 read = {false},
 starred = {false},
 authored = {true},
 confirmed = {true},
 hidden = {false},
 citation_key = {saini2018neural},
 source_type = {inproceedings},
 private_publication = {false},
 bibtype = {inproceedings},
 author = {Saini, Sandeep and Sahula, Vineet},
 booktitle = {2018 FOURTH IEEE INTERNATIONAL CONFERENCE ON INFORMATION RETRIEVAL AND KNOWLEDGE MANAGEMENT (CAMP)}
}

@inproceedings{
 title = {Low power Lightweight cryptosystems for Internet of Things Devices},
 type = {inproceedings},
 year = {2018},
 pages = {Pune--INDIA},
 issue = {Designer/User track},
 institution = {IEEE},
 id = {31c209ef-80ef-39cf-8238-203087bd41f7},
 created = {2018-08-05T03:34:05.914Z},
 file_attached = {false},
 profile_id = {03d2ca17-6bde-3cfe-95de-fcbe4f21507b},
 last_modified = {2018-08-05T03:34:05.914Z},
 read = {false},
 starred = {false},
 authored = {true},
 confirmed = {true},
 hidden = {false},
 citation_key = {goyal2018low},
 source_type = {inproceedings},
 private_publication = {false},
 bibtype = {inproceedings},
 author = {Goyal, Tarun Kumar and Sahula, Vineet},
 booktitle = {IEEE 31st International Conference on VLSI Design (and 17th International Conference on Embedded Systems)}
}

@inproceedings{
 title = {Spatial Biasing For Realizing Highly Reliable Physical Unclonable Functions on FPGA},
 type = {inproceedings},
 year = {2018},
 pages = {1-6},
 issue = {(Bengaluru)},
 institution = {IEEE},
 id = {8b6ad311-9a4d-3cfd-a3b1-90cbb53b25ef},
 created = {2018-08-05T03:34:05.918Z},
 file_attached = {false},
 profile_id = {03d2ca17-6bde-3cfe-95de-fcbe4f21507b},
 last_modified = {2018-08-05T03:34:05.918Z},
 read = {false},
 starred = {false},
 authored = {true},
 confirmed = {true},
 hidden = {false},
 citation_key = {chauhan2018spatial},
 source_type = {inproceedings},
 private_publication = {false},
 bibtype = {inproceedings},
 author = {Chauhan, Arjun Singh and Sahula, Vineet},
 booktitle = {IEEE International Conference on Electronics, Computing and Communications, IC-CONECCT}
}

@article{
 title = {Sequential Adaptive Memory Model based English-Hindi Machine Translation System},
 type = {article},
 year = {2018},
 keywords = {centre de recherche en,de reprodução animal e,departamento,machado,mariana,portela,radiologia veterinária,universidade estadual paulista,université de montréal,valério},
 pages = {1-10},
 id = {81b4727a-41d0-3454-9e19-2da52b730664},
 created = {2018-08-05T03:34:05.936Z},
 file_attached = {true},
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 last_modified = {2018-08-09T15:05:52.459Z},
 read = {false},
 starred = {false},
 authored = {true},
 confirmed = {true},
 hidden = {false},
 citation_key = {SandeepSaini2018},
 private_publication = {false},
 bibtype = {article},
 author = {Sandeep Saini, Vineet Sahula},
 journal = {IEEE Transaction on Cognitive Development Systems},
 number = {Submitted}
}

@article{
 title = {Language Learnability Analysis of Hindi: A Comparison with Ideal and Constrained Learning Approaches},
 type = {article},
 year = {2018},
 websites = {https://link.springer.com/article/10.1007%2Fs10936-019-09641-2},
 id = {0671c204-4a4c-3c80-a5df-934012d3915c},
 created = {2019-11-02T03:28:48.568Z},
 file_attached = {true},
 profile_id = {03d2ca17-6bde-3cfe-95de-fcbe4f21507b},
 last_modified = {2019-11-02T03:32:17.220Z},
 read = {false},
 starred = {false},
 authored = {true},
 confirmed = {false},
 hidden = {false},
 source_type = {Article},
 private_publication = {false},
 bibtype = {article},
 author = {Saini, Sandeep and Sahula, Vineet},
 doi = {https://doi.org/10.1007/s10936-019-09641-2},
 journal = {Spriner's Journal of Psycholinguistic Research}
}

@inproceedings{
 title = {If-Conversion To Reduce Worst Case Execution Time},
 type = {inproceedings},
 year = {2017},
 keywords = {compiler optimization,if-conversion,wcet},
 pages = {1-2},
 city = {Hsinchu, Taiwan},
 id = {626524cd-6b20-3051-b3ce-b771f02e05d1},
 created = {2017-10-14T03:28:46.881Z},
 file_attached = {true},
 profile_id = {03d2ca17-6bde-3cfe-95de-fcbe4f21507b},
 last_modified = {2017-10-14T03:28:58.475Z},
 read = {false},
 starred = {false},
 authored = {true},
 confirmed = {true},
 hidden = {false},
 citation_key = {Ghosh2017},
 private_publication = {false},
 bibtype = {inproceedings},
 author = {Ghosh, Soma Niloy and Bhargava, Lava and Sahula, Vineet},
 booktitle = {23rd IEEE International Conference on Embedded and Real-Time Computing Systems and Applications}
}

@article{
 title = {An Investigation on Electrical and Hydrogen Sensing Characteristics of RF Sputtered ZnO Thin-Film with Palladium Schottky Contacts},
 type = {article},
 year = {2017},
 keywords = {Electrical characteristics,Schottky diode,hydrogen sensing,metal-semiconductor interface palladium catalyst,zinc oxide (ZnO) thin film},
 pages = {14-21},
 volume = {17},
 id = {bc71033f-ab5d-33c6-809f-5405c64de540},
 created = {2017-11-28T18:09:40.160Z},
 file_attached = {true},
 profile_id = {03d2ca17-6bde-3cfe-95de-fcbe4f21507b},
 last_modified = {2018-08-09T15:06:47.118Z},
 read = {false},
 starred = {false},
 authored = {true},
 confirmed = {false},
 hidden = {false},
 citation_key = {Rajan2017},
 folder_uuids = {eb474840-5125-4032-aab7-41ddd99e1ea7},
 private_publication = {false},
 abstract = {© 2001-2012 IEEE. Fabrication and characterizations of a hydrogen sensor with palladium Schottky contacts, grown on radio frequency sputtered zinc oxide thin film is reported. Temperature dependence performance analysis of the proposed sensor was carried out at different hydrogen concentrations (50-1000 ppm) and temperatures (25°C-200°C) using current-voltage (I-V) measurements. Lateral shifts have been observed in the Schottky diode I-V characteristic when the device was exposed to hydrogen, and this could be attributed to the reduction of Schottky barrier height (SBH). The optimum performance of the sensor was obtained at 150 °C with maximum SBH variation of 144 meV at 1000 ppm hydrogen. Transient sensor performance at optimum temperature has also been analyzed and sensitivities ranging from 224% to 1125% with a minimum response time of 55 s and a recovery time of 26 s have been obtained. The response of sensor toward methane and nitrogen dioxide is also discussed. The basic I-V and capacitance-voltage characteristics of Pd/ZnO thin film are also reported, which confirmed its excellent rectifying properties. The basic microstructure studies of ZnO thin film were also investigated using X-ray diffraction, scanning electron microscope, atomic force microscopy, energy dispersive X-ray spectroscopy, and photoluminescence measurements. The proposed sensor has proven to be economical, due to its high sensitivity and easy to fabricate structure with a limited number of processing steps.},
 bibtype = {article},
 author = {Rajan, Lintu and Chinnamuthan, Periasamy and Krishnasamy, Vijayakumar and Sahula, Vineet},
 doi = {10.1109/JSEN.2016.2620185},
 journal = {IEEE Sensors Journal},
 number = {1}
}

© 2001-2012 IEEE. Fabrication and characterizations of a hydrogen sensor with palladium Schottky contacts, grown on radio frequency sputtered zinc oxide thin film is reported. Temperature dependence performance analysis of the proposed sensor was carried out at different hydrogen concentrations (50-1000 ppm) and temperatures (25°C-200°C) using current-voltage (I-V) measurements. Lateral shifts have been observed in the Schottky diode I-V characteristic when the device was exposed to hydrogen, and this could be attributed to the reduction of Schottky barrier height (SBH). The optimum performance of the sensor was obtained at 150 °C with maximum SBH variation of 144 meV at 1000 ppm hydrogen. Transient sensor performance at optimum temperature has also been analyzed and sensitivities ranging from 224% to 1125% with a minimum response time of 55 s and a recovery time of 26 s have been obtained. The response of sensor toward methane and nitrogen dioxide is also discussed. The basic I-V and capacitance-voltage characteristics of Pd/ZnO thin film are also reported, which confirmed its excellent rectifying properties. The basic microstructure studies of ZnO thin film were also investigated using X-ray diffraction, scanning electron microscope, atomic force microscopy, energy dispersive X-ray spectroscopy, and photoluminescence measurements. The proposed sensor has proven to be economical, due to its high sensitivity and easy to fabricate structure with a limited number of processing steps.

@inproceedings{
 title = {Accurate and efficient Estimation of Dynamic Virtual Ground Voltage in Power Gated Circuits},
 type = {inproceedings},
 year = {2016},
 issue = {January},
 publisher = {IEEE Computer Society},
 city = {Kolkata},
 id = {063741bc-0663-325a-83db-ed5108818363},
 created = {2015-09-24T07:42:17.000Z},
 file_attached = {true},
 profile_id = {03d2ca17-6bde-3cfe-95de-fcbe4f21507b},
 last_modified = {2018-08-09T15:08:09.914Z},
 read = {true},
 starred = {false},
 authored = {true},
 confirmed = {true},
 hidden = {false},
 citation_key = {Garg2016},
 private_publication = {false},
 bibtype = {inproceedings},
 author = {Garg, Lokesh and Sahula, Vineet},
 booktitle = {29th IEEE/ACM International Conference on VLSI Design}
}

@article{
 title = {Comprehensive Study on Electrical and Hydrogen Gas Sensing Characteristics of Pt/ZnO Thin Film Based Schottky Diodes Grown on n-Si Substrates by RF sputtering},
 type = {article},
 year = {2016},
 keywords = {Electrical characteristics,Hydrogen,II-VI semiconductor materials,Schottky barriers,Schottky diodes,Sensors,Substrates,Zinc oxide,metal-semiconductor interface,schottky diode,zinc oxide (ZnO) thin film},
 pages = {1-1},
 volume = {PP},
 websites = {http://ieeexplore.ieee.org/lpdocs/epic03/wrapper.htm?arnumber=7370798},
 id = {ca227a4c-1a88-3239-8016-798cfd3b7ad1},
 created = {2016-01-12T12:18:33.000Z},
 accessed = {2016-01-12},
 file_attached = {true},
 profile_id = {03d2ca17-6bde-3cfe-95de-fcbe4f21507b},
 last_modified = {2017-03-14T01:22:09.162Z},
 read = {false},
 starred = {false},
 authored = {true},
 confirmed = {true},
 hidden = {false},
 citation_key = {Rajan2016},
 short_title = {Nanotechnology, IEEE Transactions on},
 private_publication = {false},
 abstract = {This paper presents a comprehensive study on the electrical characteristics of Pt/ZnO thin film Schottky contacts fabricated on n-Si substrates by RF sputtering, and its application as a Hydrogen sensor. The basic structural, surface morphological and optical properties of the ZnO thin film were also been explored. Pt/ZnO thin film junction was characterized using current–voltage (I-V) and capacitance–voltage (C-V) measurements at room temperature, exhibiting rectifying behavior with barrier height, ideality factor and series resistance of 0.71eV(I–V)/0.996eV(C–V), 2.5 and ~ 95Ω respectively. The lack of congruence between the values of Schottky barrier heights calculated from I–V and C–V measurements is interpreted. Cheung’s method and modified Norde’s functions were employed along with the conventional thermionic emission model, to incorporate the impact of series resistance in the calculation of diode parameters. We unveiled, the Hydrogen sensing characteristics displayed by the Pt/ZnO thin film based sensor to different concentrations (200-1000ppm) of Hydrogen at 350°C. The sensor has exhibited good recoverable transient characteristics under a series of Hydrogen exposure cycles with a maximum sensitivity of 57% at 1000ppm of Hydrogen.},
 bibtype = {article},
 author = {Rajan, Lintu and Periasamy, C. and Sahula, Vineet},
 doi = {10.1109/TNANO.2015.2513102},
 journal = {IEEE Transactions on Nanotechnology},
 number = {99}
}

This paper presents a comprehensive study on the electrical characteristics of Pt/ZnO thin film Schottky contacts fabricated on n-Si substrates by RF sputtering, and its application as a Hydrogen sensor. The basic structural, surface morphological and optical properties of the ZnO thin film were also been explored. Pt/ZnO thin film junction was characterized using current–voltage (I-V) and capacitance–voltage (C-V) measurements at room temperature, exhibiting rectifying behavior with barrier height, ideality factor and series resistance of 0.71eV(I–V)/0.996eV(C–V), 2.5 and ~ 95Ω respectively. The lack of congruence between the values of Schottky barrier heights calculated from I–V and C–V measurements is interpreted. Cheung’s method and modified Norde’s functions were employed along with the conventional thermionic emission model, to incorporate the impact of series resistance in the calculation of diode parameters. We unveiled, the Hydrogen sensing characteristics displayed by the Pt/ZnO thin film based sensor to different concentrations (200-1000ppm) of Hydrogen at 350°C. The sensor has exhibited good recoverable transient characteristics under a series of Hydrogen exposure cycles with a maximum sensitivity of 57% at 1000ppm of Hydrogen.

@inproceedings{
 title = {Golden IC free Methodology for Hardware Trojan Detection using Symmetric Path Delays},
 type = {inproceedings},
 year = {2016},
 keywords = {Hardware Trojan,Hardware security,Path delay,Process variation,Trojan detection},
 publisher = {IEEE},
 city = {Guwahati},
 id = {d053c008-5cec-36be-a885-049a0dde98c8},
 created = {2016-05-10T01:52:35.000Z},
 file_attached = {true},
 profile_id = {03d2ca17-6bde-3cfe-95de-fcbe4f21507b},
 last_modified = {2017-03-14T01:22:09.162Z},
 read = {false},
 starred = {false},
 authored = {true},
 confirmed = {true},
 hidden = {false},
 citation_key = {VaikuntapuRamakrishna;BhargavaLava;Sahula2016},
 private_publication = {false},
 abstract = {Hardware Trojans can be inserted by an adversary at any phase of IC manufacturing. In this paper, a methodology is proposed to detect Trojans inserted after design sign-off i.e the Trojan insertion occurs at layout level. In such attack models, golden IC are not always available in all cases, thus requiring golden IC free detection methodologies. This work exploits the concept of symmetric path delays to detect Trojans, considering the change in delays of symmetric pairs due to Trojan insertion. We propose detection metric (DM) of a suspect IC and compare the same with a detection threshold (DT) to decide whether IC under purview is Trojan free. Moreover, this method does not require any golden IC. Additionally, this method is robust enough against process variation effects. Simulation results establish that, a detection rate of 100% is achievable with maximum of 8% intra-die and 10% inter-die variation in both threshold voltage (Vth) and length (L), respectively.},
 bibtype = {inproceedings},
 author = {Vaikuntapu, Ramakrishna; Bhargava, Lava; Sahula, Vineet},
 booktitle = {IEEE VLSI Design & Test Symposium}
}

Hardware Trojans can be inserted by an adversary at any phase of IC manufacturing. In this paper, a methodology is proposed to detect Trojans inserted after design sign-off i.e the Trojan insertion occurs at layout level. In such attack models, golden IC are not always available in all cases, thus requiring golden IC free detection methodologies. This work exploits the concept of symmetric path delays to detect Trojans, considering the change in delays of symmetric pairs due to Trojan insertion. We propose detection metric (DM) of a suspect IC and compare the same with a detection threshold (DT) to decide whether IC under purview is Trojan free. Moreover, this method does not require any golden IC. Additionally, this method is robust enough against process variation effects. Simulation results establish that, a detection rate of 100% is achievable with maximum of 8% intra-die and 10% inter-die variation in both threshold voltage (Vth) and length (L), respectively.

@inproceedings{
 title = {Bayesian learner based language learnability analysis of Hindi},
 type = {inproceedings},
 year = {2016},
 websites = {http://ieeexplore.ieee.org/abstract/document/7732359/},
 id = {61926ab9-0714-3886-af6b-8c4e20806f38},
 created = {2016-11-08T13:33:16.000Z},
 file_attached = {true},
 profile_id = {03d2ca17-6bde-3cfe-95de-fcbe4f21507b},
 last_modified = {2018-08-09T15:06:20.521Z},
 read = {false},
 starred = {false},
 authored = {true},
 confirmed = {false},
 hidden = {false},
 citation_key = {SandeepSaini2016},
 private_publication = {false},
 bibtype = {inproceedings},
 author = {Sandeep Saini, Vineet Sahula},
 booktitle = {5th IEEE International Conference on Advances in Computing, Communications and Informatics (ICACCI)}
}

@inproceedings{
 title = {Lightweight security algorithm for low power IoT devices},
 type = {inproceedings},
 year = {2016},
 keywords = {Cryptography,ECC,ECDH,crypt-analysis,internet of things (IoT)},
 id = {215df1b8-f6a2-3b51-985a-9c3d6d504a0b},
 created = {2017-11-28T18:09:39.930Z},
 file_attached = {true},
 profile_id = {03d2ca17-6bde-3cfe-95de-fcbe4f21507b},
 last_modified = {2018-08-09T15:06:23.769Z},
 read = {false},
 starred = {false},
 authored = {true},
 confirmed = {false},
 hidden = {false},
 citation_key = {Goyal2016},
 private_publication = {false},
 abstract = {© 2016 IEEE. In today's technology, ever increasing number of electronics applications require secure communication, for example the Internet of things devices. Elliptic Curve Diffie Hellman (EC-DH) Algorithm has emerged as an attractive and effective public-key cryptosystem. Elliptic curves are widely used in various key exchange techniques that include the Diffie-Hellman Key agreement scheme. When contrasted with conventional cryptosystems like RSA, ECC offers equivalent security with smaller key sizes, which results in lower power consumption, speedier calculations, and also lower memory and transmission capacity (bandwidth) reserve. This is particularly valid and helpful for applications like IoT gadgets, which are regularly constrained regarding their CPU processing speed, power, and area. This work includes the software and hardware implementation of Diffie-Hellman, Elliptic Curve Diffie-Hellman (ECDH) Key agreement algorithm, and RSA algorithm. The proposed work also involves analysis of power, performance, area, and their comparisons thereof. The comparison is based on metrics obtained, after implementing the algorithms in synopsys using 90 nm UMC Faraday library. The ECDH algorithm is found to be better than others as far as power and area are concerned.},
 bibtype = {inproceedings},
 author = {Goyal, T.K. and Sahula, V.},
 doi = {10.1109/ICACCI.2016.7732296},
 booktitle = {5th IEEE International Conference on Advances in Computing, Communications and Informatics}
}

© 2016 IEEE. In today's technology, ever increasing number of electronics applications require secure communication, for example the Internet of things devices. Elliptic Curve Diffie Hellman (EC-DH) Algorithm has emerged as an attractive and effective public-key cryptosystem. Elliptic curves are widely used in various key exchange techniques that include the Diffie-Hellman Key agreement scheme. When contrasted with conventional cryptosystems like RSA, ECC offers equivalent security with smaller key sizes, which results in lower power consumption, speedier calculations, and also lower memory and transmission capacity (bandwidth) reserve. This is particularly valid and helpful for applications like IoT gadgets, which are regularly constrained regarding their CPU processing speed, power, and area. This work includes the software and hardware implementation of Diffie-Hellman, Elliptic Curve Diffie-Hellman (ECDH) Key agreement algorithm, and RSA algorithm. The proposed work also involves analysis of power, performance, area, and their comparisons thereof. The comparison is based on metrics obtained, after implementing the algorithms in synopsys using 90 nm UMC Faraday library. The ECDH algorithm is found to be better than others as far as power and area are concerned.

@inproceedings{
 title = {Structural and optical characteristics of RF sputtered ZnO thinfilm on Si substrate for device applications},
 type = {inproceedings},
 year = {2016},
 keywords = {AFM,Optical properties,PL,RF sputtering,SEM,Silicon,XRD,ZnO thin film},
 id = {a86c399b-b5f6-3e5c-9878-24840495eabd},
 created = {2017-11-28T18:09:40.056Z},
 file_attached = {false},
 profile_id = {03d2ca17-6bde-3cfe-95de-fcbe4f21507b},
 last_modified = {2018-02-12T15:32:52.927Z},
 read = {false},
 starred = {false},
 authored = {true},
 confirmed = {false},
 hidden = {false},
 citation_key = {Rajan2016},
 private_publication = {false},
 abstract = {© 2015 IEEE. In this paper, we have investigated the structural and optical characteristics of ZnO thin film grown through Radio frequency magnetron (RF) sputtering technique on n-Silicon substrate. The surface morphological characteristics of the sample have been investigated by using Scanning electron microscope (SEM) and Atomic force microscope (AFM), which confirms the growth of uniform and smooth ZnO film on the substrate. Crystallographic studies were conducted using X-Ray diffraction technique (XRD) which revealed the preferentially Caxis oriented growth of film with hexagonal Wurtzite structure. We have also calculated micro structural parameters such as particle size, lattice constants, lattice stress and strain, dislocation density etc. Photoluminescence (PL) spectra shows strong near-band edge emission, indicating excellent crystallinity of deposited film with optical band gap as 3.25 eV. UV visible spectra of the film displayed excellent transmittance in the visible region. All the results confirm that the fabricated Zinc Oxide thin film can be used for all typical device applications.},
 bibtype = {inproceedings},
 author = {Rajan, L. and Periasamy, C. and Sahula, V.},
 doi = {10.1109/INDICON.2015.7443410},
 booktitle = {12th IEEE International Conference Electronics, Energy, Environment, Communication, Computer, Control: (E3-C3), INDICON 2015}
}

© 2015 IEEE. In this paper, we have investigated the structural and optical characteristics of ZnO thin film grown through Radio frequency magnetron (RF) sputtering technique on n-Silicon substrate. The surface morphological characteristics of the sample have been investigated by using Scanning electron microscope (SEM) and Atomic force microscope (AFM), which confirms the growth of uniform and smooth ZnO film on the substrate. Crystallographic studies were conducted using X-Ray diffraction technique (XRD) which revealed the preferentially Caxis oriented growth of film with hexagonal Wurtzite structure. We have also calculated micro structural parameters such as particle size, lattice constants, lattice stress and strain, dislocation density etc. Photoluminescence (PL) spectra shows strong near-band edge emission, indicating excellent crystallinity of deposited film with optical band gap as 3.25 eV. UV visible spectra of the film displayed excellent transmittance in the visible region. All the results confirm that the fabricated Zinc Oxide thin film can be used for all typical device applications.

@article{
 title = {Influence of Temperature on the Sensitivity of ZnO-Based MEMS Acoustic Sensor},
 type = {article},
 year = {2016},
 keywords = {Bulk Micromachining,Dielectric Constant,MEMS Acoustic Sensor,Temperature,ZnO},
 pages = {122-126},
 volume = {14},
 publisher = {American Scientific Publishers},
 id = {d14b6362-5161-3071-bfa3-2e402ba141fe},
 created = {2018-08-05T03:34:06.103Z},
 file_attached = {false},
 profile_id = {03d2ca17-6bde-3cfe-95de-fcbe4f21507b},
 last_modified = {2018-08-05T03:34:09.326Z},
 read = {false},
 starred = {false},
 authored = {true},
 confirmed = {true},
 hidden = {false},
 citation_key = {prasad2016influence},
 source_type = {article},
 folder_uuids = {eb474840-5125-4032-aab7-41ddd99e1ea7},
 private_publication = {false},
 abstract = {Copyright © 2016 American Scientific Publishers All rights reserved. This study investigates the temperature dependence of the sensitivity of ZnO-based MEMS acoustic sensor. The structure contains a capacitor using ZnO dielectric layer, on a 25 m-thick silicon diaphragm. One micron-thick Al was used as top and bottom electrodes for the fabrication of capacitor. The value of dielectric constant of ZnO layer was found to be 12.5 by measuring the capacitance value at room temperature and 1 kHz frequency. The investigations showed that the value of dielectric constant of ZnO layer increases with temperature. A variation of 11 to 16.2 was observed in dielectric constant on changing the temperature of the device from 25 C to 120 C. The corresponding dielectric loss (tan) also increased from 0.03 to 0.1. This variation of capacitance and the corresponding loss affects the sensitivity of the device, which was found to decrease from 432 V/Pa at 25 C to 290 V/Pa at 120 C.},
 bibtype = {article},
 author = {Prasad, Mahanth and Sahula, Vineet and Khanna, Vinod Kumar V.K.},
 doi = {10.1166/sl.2016.3603},
 journal = {Sensor Letters},
 number = {2}
}

Copyright © 2016 American Scientific Publishers All rights reserved. This study investigates the temperature dependence of the sensitivity of ZnO-based MEMS acoustic sensor. The structure contains a capacitor using ZnO dielectric layer, on a 25 m-thick silicon diaphragm. One micron-thick Al was used as top and bottom electrodes for the fabrication of capacitor. The value of dielectric constant of ZnO layer was found to be 12.5 by measuring the capacitance value at room temperature and 1 kHz frequency. The investigations showed that the value of dielectric constant of ZnO layer increases with temperature. A variation of 11 to 16.2 was observed in dielectric constant on changing the temperature of the device from 25 C to 120 C. The corresponding dielectric loss (tan) also increased from 0.03 to 0.1. This variation of capacitance and the corresponding loss affects the sensitivity of the device, which was found to decrease from 432 V/Pa at 25 C to 290 V/Pa at 120 C.

@article{
 title = {Electrical Characterization of Au/ZnO Thin Film Schottky diode on silicon substrate},
 type = {article},
 year = {2016},
 keywords = {Electrical characterization,Gold,Schottky diode,Thin film,Zinc oxide},
 pages = {66-68},
 volume = {8},
 websites = {http://linkinghub.elsevier.com/retrieve/pii/S2213020916300118,http://dx.doi.org/10.1016/j.pisc.2016.03.011},
 publisher = {Urban & Fischer},
 id = {1dc34057-59ea-342c-8e22-b0f9651fafd6},
 created = {2018-08-09T15:05:51.591Z},
 accessed = {2016-08-14},
 file_attached = {true},
 profile_id = {03d2ca17-6bde-3cfe-95de-fcbe4f21507b},
 last_modified = {2018-08-09T15:06:56.868Z},
 read = {false},
 starred = {false},
 authored = {true},
 confirmed = {true},
 hidden = {false},
 citation_key = {Rajan2016a},
 source_type = {article},
 folder_uuids = {2e75317a-6021-4c24-9d76-92a4e1ad9cd4,eb474840-5125-4032-aab7-41ddd99e1ea7},
 private_publication = {false},
 abstract = {An array of Gold (Au) schottky contacts have been deposited on RF Sputtered nanocrystalline Zinc Oxide thin film. A systematic analysis on the electrical parameters of the Schottky diode with the help of current—voltage (I—V) and capacitance-voltage (C—V) measure-ments has been done, which confirmed its excellent rectifying characteristics. To incorporate the influence of series resistance in the determination of Schottky diode parameters (barrier height, ideality factor and saturation current), Cheung's method along with thermionic emis-sion model has also used. The discrepancy in the value of barrier height determined from C—V characteristics throws light into the presence of interface states.},
 bibtype = {article},
 author = {Rajan, Lintu and Periasamy, C. and Sahula, Vineet},
 doi = {10.1016/j.pisc.2016.03.011},
 journal = {Elsevier's Perspectives in Science, Science Direct}
}

An array of Gold (Au) schottky contacts have been deposited on RF Sputtered nanocrystalline Zinc Oxide thin film. A systematic analysis on the electrical parameters of the Schottky diode with the help of current—voltage (I—V) and capacitance-voltage (C—V) measure-ments has been done, which confirmed its excellent rectifying characteristics. To incorporate the influence of series resistance in the determination of Schottky diode parameters (barrier height, ideality factor and saturation current), Cheung's method along with thermionic emis-sion model has also used. The discrepancy in the value of barrier height determined from C—V characteristics throws light into the presence of interface states.

@article{
 title = {Macromodels for Static Virtual Ground Voltage Estimation in Power Gated Circuits},
 type = {article},
 year = {2015},
 keywords = {CMOS integrated circuits,Integrated circuit modeling,Leakage current,Logic circuits,Logic gates,Power gating,Semiconductor device modeling,Support Vector Machine (SVM),Support vector machines,Transistors},
 pages = {1-1},
 volume = {PP},
 websites = {http://ieeexplore.ieee.org/lpdocs/epic03/wrapper.htm?arnumber=7339471},
 id = {a8e9d039-bbed-309c-b0ef-3ff4113ab52c},
 created = {2015-12-15T06:02:04.000Z},
 accessed = {2015-12-08},
 file_attached = {true},
 profile_id = {03d2ca17-6bde-3cfe-95de-fcbe4f21507b},
 last_modified = {2017-03-14T01:22:09.162Z},
 read = {false},
 starred = {false},
 authored = {true},
 confirmed = {true},
 hidden = {false},
 citation_key = {Garg2015},
 short_title = {Circuits and Systems II: Express Briefs, IEEE Tran},
 private_publication = {false},
 abstract = {Static virtual ground voltage (V gnd) is an important parameter to be accurately and efficiently estimated for fine grained power gating in logic circuits. Previous work results in large error in Vgnd estimation due to conservative leakage models and inaccurate assumption of voltage conditions at the input of CMOS gates in power gated circuits. To overcome these problems, we propose Support Vector Machine (SVM) based macromodels to estimate leakage current of CMOS gates and thus achieve effective reduction of error in leakage model characterization. These models are then used in SVM classifier (SVC) and regressor (SVR) to formulate SVM regression based V gnd model. SVC results in 3 saving in data generation time compared to HSPICE simulation to develop final V gnd model. The proposed model results in <1% error and 23000 speedup than HSPICE for the largest benchmark circuit.},
 bibtype = {article},
 author = {Garg, Lokesh and Sahula, Vineet},
 doi = {10.1109/TCSII.2015.2504270},
 journal = {IEEE Transactions on Circuits and Systems II: Express Briefs},
 number = {99}
}

Static virtual ground voltage (V gnd) is an important parameter to be accurately and efficiently estimated for fine grained power gating in logic circuits. Previous work results in large error in Vgnd estimation due to conservative leakage models and inaccurate assumption of voltage conditions at the input of CMOS gates in power gated circuits. To overcome these problems, we propose Support Vector Machine (SVM) based macromodels to estimate leakage current of CMOS gates and thus achieve effective reduction of error in leakage model characterization. These models are then used in SVM classifier (SVC) and regressor (SVR) to formulate SVM regression based V gnd model. SVC results in 3 saving in data generation time compared to HSPICE simulation to develop final V gnd model. The proposed model results in <1% error and 23000 speedup than HSPICE for the largest benchmark circuit.

@inproceedings{
 title = {Modeling and synthesis of molecular memory},
 type = {inproceedings},
 year = {2015},
 keywords = {CAD tool,Computational modeling,HSPICE,Integrated circuit modeling,Nanoparticles,Nanoscale,Nanoscale devices,Reliability,SPICE,Solid modeling,Switches,electron-phenomena,logic CAD,logic devices,memory,molecular device,molecular electronics,molecular electronics research,molecules,nanocell,nanocell based molecular memory,nanoscale memory,organic molecules,probabilistic models,random-access storage,transient errors,uncertainty},
 pages = {1-2},
 websites = {http://ieeexplore.ieee.org/lpdocs/epic03/wrapper.htm?arnumber=7208081},
 month = {6},
 publisher = {IEEE},
 id = {e1b9f26e-11d9-3bd9-be46-ac102ed02dea},
 created = {2015-12-15T06:02:05.000Z},
 accessed = {2015-12-15},
 file_attached = {true},
 profile_id = {03d2ca17-6bde-3cfe-95de-fcbe4f21507b},
 last_modified = {2017-03-14T01:22:09.162Z},
 read = {false},
 starred = {false},
 authored = {true},
 confirmed = {true},
 hidden = {false},
 citation_key = {Kumawat2015a},
 short_title = {VLSI Design and Test (VDAT), 2015 19th Internation},
 private_publication = {false},
 abstract = {Performance and reliability of nanoscale memory and logic devices is determined by few electron-phenomena. In this context, the organic molecules may offer some advantages for future memory applications. Since, a molecule is the smallest component whose electrical properties can be engineered, it can be argued that the ultimate integrated circuit will be constructed at the molecular level. This fact has been the driving force behind molecular electronics research of recent times. This article investigates the aspects of modeling, synthesis and analysis of nanocell based molecular memory. In our work, we have developed the HSPICE as well as probabilistic models for nanocell based molecular memory. An attempt has been made to develop a CAD tool for synthesis of such molecular memories which are posing interesting and promising research challenges at futuristic cutting edge of technology spectrum.},
 bibtype = {inproceedings},
 author = {Kumawat, Renu and Sahula, Vineet and Gaur, Manoj Singh},
 doi = {10.1109/ISVDAT.2015.7208081},
 booktitle = {2015 19th International Symposium on VLSI Design and Test}
}

Performance and reliability of nanoscale memory and logic devices is determined by few electron-phenomena. In this context, the organic molecules may offer some advantages for future memory applications. Since, a molecule is the smallest component whose electrical properties can be engineered, it can be argued that the ultimate integrated circuit will be constructed at the molecular level. This fact has been the driving force behind molecular electronics research of recent times. This article investigates the aspects of modeling, synthesis and analysis of nanocell based molecular memory. In our work, we have developed the HSPICE as well as probabilistic models for nanocell based molecular memory. An attempt has been made to develop a CAD tool for synthesis of such molecular memories which are posing interesting and promising research challenges at futuristic cutting edge of technology spectrum.

@inproceedings{
 title = {Relative clause based text simplification for improved English to Hindi translation},
 type = {inproceedings},
 year = {2015},
 keywords = {Computational Intelligence,Computers,Engines,English-to-Hindi language translation,Google,Grammar,Machine Translation,Manuals,Natural languages,Relative Clause identification,Syntactics,Text Simplification,grammar structure,language translation,link parser based parsing techniques,machine translation,relative clause,text analysis,text simplification},
 pages = {1479-1484},
 websites = {http://ieeexplore.ieee.org/lpdocs/epic03/wrapper.htm?arnumber=7275821},
 month = {8},
 publisher = {IEEE},
 id = {32071357-ad74-3285-8c60-3ea0a2d488dd},
 created = {2016-04-21T16:39:33.000Z},
 accessed = {2015-09-29},
 file_attached = {true},
 profile_id = {03d2ca17-6bde-3cfe-95de-fcbe4f21507b},
 last_modified = {2017-03-14T01:22:09.162Z},
 read = {false},
 starred = {false},
 authored = {true},
 confirmed = {true},
 hidden = {false},
 citation_key = {Saini2015b},
 short_title = {Advances in Computing, Communications and Informat},
 folder_uuids = {172c4050-4c31-47ec-838e-087f593eb448},
 private_publication = {false},
 abstract = {Language translation is one of the most research and development oriented topic in today's world because of its increasing demand and application. Knowledge of grammar structure of source and target languages is must for translating one language to other. Clauses are an integral part of any language and helps in constructing complex sentences in different contexts. This complication leads to a low score of translation in almost every machine translation engine existing in the world. In this work, we are focusing on relative clause identification and extraction for text simplification. The generated simple sentences are then fed to the existing translation engines for translation. Link Parser based parsing techniques are used to parse the sentence tree. In this work we have focused on achieving better quality of English-Hindi translations. The proposed approach is tested manually on a sufficiently large dataset and shows promising and better translation score than the conventional approaches.},
 bibtype = {inproceedings},
 author = {Saini, Sandeep and Sehgal, Umang and Sahula, Vineet},
 doi = {10.1109/ICACCI.2015.7275821},
 booktitle = {2015 International Conference on Advances in Computing, Communications and Informatics (ICACCI)}
}

Language translation is one of the most research and development oriented topic in today's world because of its increasing demand and application. Knowledge of grammar structure of source and target languages is must for translating one language to other. Clauses are an integral part of any language and helps in constructing complex sentences in different contexts. This complication leads to a low score of translation in almost every machine translation engine existing in the world. In this work, we are focusing on relative clause identification and extraction for text simplification. The generated simple sentences are then fed to the existing translation engines for translation. Link Parser based parsing techniques are used to parse the sentence tree. In this work we have focused on achieving better quality of English-Hindi translations. The proposed approach is tested manually on a sufficiently large dataset and shows promising and better translation score than the conventional approaches.

@inproceedings{
 title = {A Survey of Machine Translation Techniques and Systems for Indian Languages},
 type = {inproceedings},
 year = {2015},
 keywords = {Dictionaries,Government,Grammar,Indian languages,Learning systems,MTS,Natural language processing,Natural languages,Pragmatics,Probability,Statistical Machine Translation,Training,automated computing,language translation,machine translation system,machine translation technique,natural language processing,natural language translation},
 pages = {676-681},
 websites = {http://ieeexplore.ieee.org/lpdocs/epic03/wrapper.htm?arnumber=7078789},
 month = {2},
 publisher = {IEEE},
 id = {bd3d7dd6-cdb0-3d66-8995-66c052fcc65e},
 created = {2016-04-21T16:39:33.000Z},
 accessed = {2015-09-29},
 file_attached = {true},
 profile_id = {03d2ca17-6bde-3cfe-95de-fcbe4f21507b},
 last_modified = {2017-03-14T01:22:09.162Z},
 read = {false},
 starred = {false},
 authored = {true},
 confirmed = {true},
 hidden = {false},
 citation_key = {Saini2015a},
 short_title = {Computational Intelligence & Communication Technol},
 private_publication = {false},
 abstract = {Machine Translation pertains to translation of one natural language to other by using automated computing. The main objective is to fill the language gap between two different languages speaking people, communities or countries. In India, we have multiple and hugely diverse languages and scripts, hence scope and need of language translation is immense. In this paper, we focus on the current scenario of research in machine translation in India. We have reviewed various important Machine Translation Systems (MTS) and presented preliminary comparison of the core methodology as used by them.},
 bibtype = {inproceedings},
 author = {Saini, Sandeep and Sahula, Vineet},
 doi = {10.1109/CICT.2015.123},
 booktitle = {2015 IEEE International Conference on Computational Intelligence & Communication Technology}
}

Machine Translation pertains to translation of one natural language to other by using automated computing. The main objective is to fill the language gap between two different languages speaking people, communities or countries. In India, we have multiple and hugely diverse languages and scripts, hence scope and need of language translation is immense. In this paper, we focus on the current scenario of research in machine translation in India. We have reviewed various important Machine Translation Systems (MTS) and presented preliminary comparison of the core methodology as used by them.

@inproceedings{
 title = {Cognitive Aspects in Relating Second Language Acquisition as a Language Translation Process},
 type = {inproceedings},
 year = {2015},
 city = {IIT Gandhinagar},
 id = {9a955d47-7ce1-36a3-9217-8cfe2af831f2},
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 author = {Saini, Sandeep (LNM-IIT Jaipur) and and Sahula, Vineet},
 booktitle = {3rd International Conference on Cognition, Brain and Computation 2015}
}

@inproceedings{
 title = {Modeling and Synthesis of Molecular Memory},
 type = {inproceedings},
 year = {2015},
 id = {d0406d8d-6db7-3b9d-9557-009d6db2aa14},
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 citation_key = {KUMAWATRENU;SAHULAVineet;Gaur2015},
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 bibtype = {inproceedings},
 author = {KUMAWAT, RENU ; SAHULA, Vineet; Gaur, M. S.},
 booktitle = {VLSI Design & Test Symposium}
}

@inproceedings{
 title = {High Density Impulsive Noise Removal Using Decision Based Iterated Conditional Modes},
 type = {inproceedings},
 year = {2015},
 websites = {http://www.scopus.com/inward/record.url?eid=2-s2.0-84963971201&partnerID=MN8TOARS},
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 starred = {false},
 authored = {true},
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 hidden = {false},
 citation_key = {Chauhan2015},
 private_publication = {false},
 bibtype = {inproceedings},
 author = {Chauhan, A S and Sahula, V},
 doi = {10.1109/ISPCC.2015.7374992},
 booktitle = {IEEE International Conference on Signal Processing, Computing and Control, ISPCC 2015}
}

@article{
 title = {Probabilistic model for nanocell reliability evaluation in presence of transient errors},
 type = {article},
 year = {2015},
 keywords = {HSPICE model,MATLAB,PERL,SPICE,but cannot be converted,e,extended continuous time birth-death model,files,for peer review,g,model representation,molecular electronics,movies,nanocell device reliability analysis,nanoelectronics,nanoparticles,negative differential resistor,note,online,pdf,probabilistic model,probability,reliability,resistors,self-assembled monolayer,submitted by the author,the following files were,to,transient error,you must view these},
 pages = {213-220},
 volume = {9},
 websites = {http://digital-library.theiet.org/content/journals/10.1049/iet-cdt.2014.0124},
 month = {7},
 day = {1},
 id = {3e93ea3d-8056-3994-a25b-dfbefca1d0b1},
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 authored = {true},
 confirmed = {true},
 hidden = {false},
 citation_key = {Kumawat2015},
 short_title = {Computers & Digital Techniques, IET},
 folder_uuids = {eb474840-5125-4032-aab7-41ddd99e1ea7},
 private_publication = {false},
 abstract = {In this study, the authors propose a novel extended continuous time birth-death model for reliability analysis of a nanocell device. A nanocell consists of conducting nanoparticles connected via randomly placed self-assembled monolayer of molecules. These molecules behave as a negative differential resistor. The mathematical expression for expected nanocell lifetime and its availability, in presence of transient errors is computed. On the basis of the model, an algorithm is developed and implemented in MATLAB, PERL and HSPICE, to automatically generate the proposed model representation for a given nanocell. It is used to estimate the success_ratio as well as the nanocell reliability, while considering the uncertainties induced by transient errors. The theoretical results for reliability are validated by simulating HSPICE model of nanocell in presence of varying defect rates. It is observed that the device reliability increases with increase in the number of nanoparticles and molecules. A lower and upper bounds for nanocell reliability are calculated in theory which is validated in simulations.},
 bibtype = {article},
 author = {Kumawat, Renu and Sahula, Vineet and Gaur, Manoj Singh},
 doi = {10.1049/iet-cdt.2014.0124},
 journal = {IET Computers & Digital Techniques},
 number = {4}
}

In this study, the authors propose a novel extended continuous time birth-death model for reliability analysis of a nanocell device. A nanocell consists of conducting nanoparticles connected via randomly placed self-assembled monolayer of molecules. These molecules behave as a negative differential resistor. The mathematical expression for expected nanocell lifetime and its availability, in presence of transient errors is computed. On the basis of the model, an algorithm is developed and implemented in MATLAB, PERL and HSPICE, to automatically generate the proposed model representation for a given nanocell. It is used to estimate the success_ratio as well as the nanocell reliability, while considering the uncertainties induced by transient errors. The theoretical results for reliability are validated by simulating HSPICE model of nanocell in presence of varying defect rates. It is observed that the device reliability increases with increase in the number of nanoparticles and molecules. A lower and upper bounds for nanocell reliability are calculated in theory which is validated in simulations.

@article{
 title = {Probabilistic model for nanocell reliability evaluation in presence of transient errors},
 type = {article},
 year = {2015},
 keywords = {HSPICE model,MATLAB,PERL,SPICE,but cannot be converted,e,extended continuous time birth-death model,files,for peer review,g,model representation,molecular electronics,movies,nanocell device reliability analysis,nanoelectronics,nanoparticles,negative differential resistor,note,online,pdf,probabilistic model,probability,reliability,resistors,self-assembled monolayer,submitted by the author,the following files were,to,transient error,you must view these},
 pages = {213-220},
 volume = {9},
 websites = {http://digital-library.theiet.org/content/journals/10.1049/iet-cdt.2014.0124},
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 short_title = {Computers & Digital Techniques, IET},
 folder_uuids = {eb474840-5125-4032-aab7-41ddd99e1ea7},
 private_publication = {false},
 abstract = {In this study, the authors propose a novel extended continuous time birth-death model for reliability analysis of a nanocell device. A nanocell consists of conducting nanoparticles connected via randomly placed self-assembled monolayer of molecules. These molecules behave as a negative differential resistor. The mathematical expression for expected nanocell lifetime and its availability, in presence of transient errors is computed. On the basis of the model, an algorithm is developed and implemented in MATLAB, PERL and HSPICE, to automatically generate the proposed model representation for a given nanocell. It is used to estimate the success_ratio as well as the nanocell reliability, while considering the uncertainties induced by transient errors. The theoretical results for reliability are validated by simulating HSPICE model of nanocell in presence of varying defect rates. It is observed that the device reliability increases with increase in the number of nanoparticles and molecules. A lower and upper bounds for nanocell reliability are calculated in theory which is validated in simulations.},
 bibtype = {article},
 author = {Kumawat, Renu and Sahula, Vineet and Gaur, Manoj Singh},
 doi = {10.1049/iet-cdt.2014.0124},
 journal = {IET Computers & Digital Techniques},
 number = {4}
}

In this study, the authors propose a novel extended continuous time birth-death model for reliability analysis of a nanocell device. A nanocell consists of conducting nanoparticles connected via randomly placed self-assembled monolayer of molecules. These molecules behave as a negative differential resistor. The mathematical expression for expected nanocell lifetime and its availability, in presence of transient errors is computed. On the basis of the model, an algorithm is developed and implemented in MATLAB, PERL and HSPICE, to automatically generate the proposed model representation for a given nanocell. It is used to estimate the success_ratio as well as the nanocell reliability, while considering the uncertainties induced by transient errors. The theoretical results for reliability are validated by simulating HSPICE model of nanocell in presence of varying defect rates. It is observed that the device reliability increases with increase in the number of nanoparticles and molecules. A lower and upper bounds for nanocell reliability are calculated in theory which is validated in simulations.

@article{
 title = {Probabilistic Modeling and Analysis of Molecular Memory},
 type = {article},
 year = {2014},
 id = {c7218910-ed45-3121-ab02-a18369fed79f},
 created = {2014-04-17T21:17:22.000Z},
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 author = {Kumawat, R and Sahula, V and Gaur, M S},
 journal = {ACM Journal on Emerging Technology for Computer Systems}
}

@article{
 title = {Hybrid image fusion scheme using self-fractional Fourier functions and multivariate empirical mode decomposition},
 type = {article},
 year = {2014},
 keywords = {Fractional Fourier transform,Image fusion,Multivariate empirical mode decomposition,Self-fractional Fourier functions},
 pages = {146-159},
 volume = {100},
 id = {e154cb6b-00c3-3229-84d5-41d980e94b80},
 created = {2014-06-15T16:15:16.000Z},
 file_attached = {true},
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 last_modified = {2017-03-14T01:22:09.162Z},
 read = {false},
 starred = {false},
 authored = {true},
 confirmed = {true},
 hidden = {false},
 citation_key = {Sharma2014},
 private_publication = {false},
 abstract = {Image fusion has emerged as a promising area of research and a bivariate empirical mode decomposition based fusion scheme has recently been proposed in the literature. In this paper, a hybrid fusion scheme combining self-fractional Fourier function (SFFF) decomposition and multivariate empirical mode decomposition is proposed. In the proposed image fusion technique, images to be fused are decomposed into SFFF images. The SFFF images are further decomposed into intrinsic mode functions (IMFs) using multivariate empirical mode decomposition (MEMD). Corresponding IMFs of same decomposition level of SFFF images are fused using local variance based adaptive weight fusion rule to obtain fused IMF images. The fused image is obtained by applying inverse transformation on fused IMF images. The proposed technique provides flexibility in the number of functions in the SFFF decomposition, transform before SFFF decomposition, and the types of source images (real and complex) to be fused. Simulations are performed for fusion of test images with different SFFF decomposition levels and the results are compared with other existing methods. It is seen that the simulation results are comparable to the existing schemes. ?? 2014 Elsevier B.V.},
 bibtype = {article},
 author = {Sharma, J. B. and Sharma, K. K. and Sahula, Vineet},
 doi = {10.1016/j.sigpro.2014.01.001},
 journal = {Signal Processing}
}

Image fusion has emerged as a promising area of research and a bivariate empirical mode decomposition based fusion scheme has recently been proposed in the literature. In this paper, a hybrid fusion scheme combining self-fractional Fourier function (SFFF) decomposition and multivariate empirical mode decomposition is proposed. In the proposed image fusion technique, images to be fused are decomposed into SFFF images. The SFFF images are further decomposed into intrinsic mode functions (IMFs) using multivariate empirical mode decomposition (MEMD). Corresponding IMFs of same decomposition level of SFFF images are fused using local variance based adaptive weight fusion rule to obtain fused IMF images. The fused image is obtained by applying inverse transformation on fused IMF images. The proposed technique provides flexibility in the number of functions in the SFFF decomposition, transform before SFFF decomposition, and the types of source images (real and complex) to be fused. Simulations are performed for fusion of test images with different SFFF decomposition levels and the results are compared with other existing methods. It is seen that the simulation results are comparable to the existing schemes. ?? 2014 Elsevier B.V.

@article{
 title = {Quick Estimation of Rectangular Patch Antenna Dimensions Based on Equivalent Design Concept},
 type = {article},
 year = {2014},
 pages = {1},
 volume = {PP},
 id = {764c4f3b-f4da-30d6-91ab-cdca9130479b},
 created = {2014-10-21T04:23:54.000Z},
 file_attached = {true},
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 last_modified = {2018-08-04T08:25:15.868Z},
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 starred = {false},
 authored = {true},
 confirmed = {true},
 hidden = {false},
 citation_key = {6847143},
 source_type = {article},
 folder_uuids = {eb474840-5125-4032-aab7-41ddd99e1ea7},
 private_publication = {false},
 abstract = {This paper presents a new method for quickly estimating the physical dimensions of a rectangular microstrip antenna (RMSA). This is based on the newly introduced concept of “Equivalence of Design” for RMSA. Two designs are said to be equivalent if they result in the same resonance frequency. This is an outcome of Bhatnagar’s postulate. It relates the classical extension in length L with the length and width of the patch apart from the substrate thickness. This paper emphasizes the importance of substrate thickness normalized with respect to guided wave length. This is termed as the ‘H’ parameter. For RMSA this is the key parameter rather than the individual parameters – Dielectric Constant ("r), Substrate Thickness (h) or Resonance Frequency (f0). A new parameter – the scaling factor ( ) has been introduced and defined. Based on these, transformation laws have been put forward. These can be used for quickly estimating the RMSA design parameters from a “known good design”. The laws have been verified by estimating physical parameters of RMSA and then calculating its resonance frequency. This has been repeated for several hundred designs. The matching has been excellent. Simulation and measurement results of a known good design (Design1) and one of the transformed designs (Design3) are also presented. The results of the transformed design are in good agreement with those of Design1 considering fabrication and measurement tolerances.},
 bibtype = {article},
 author = {Mathur, D and Bhatnagar, S K and Sahula, V},
 doi = {10.1109/LAWP.2014.2334362},
 journal = {Antennas and Wireless Propagation Letters, IEEE},
 number = {99}
}

This paper presents a new method for quickly estimating the physical dimensions of a rectangular microstrip antenna (RMSA). This is based on the newly introduced concept of “Equivalence of Design” for RMSA. Two designs are said to be equivalent if they result in the same resonance frequency. This is an outcome of Bhatnagar’s postulate. It relates the classical extension in length L with the length and width of the patch apart from the substrate thickness. This paper emphasizes the importance of substrate thickness normalized with respect to guided wave length. This is termed as the ‘H’ parameter. For RMSA this is the key parameter rather than the individual parameters – Dielectric Constant ("r), Substrate Thickness (h) or Resonance Frequency (f0). A new parameter – the scaling factor ( ) has been introduced and defined. Based on these, transformation laws have been put forward. These can be used for quickly estimating the RMSA design parameters from a “known good design”. The laws have been verified by estimating physical parameters of RMSA and then calculating its resonance frequency. This has been repeated for several hundred designs. The matching has been excellent. Simulation and measurement results of a known good design (Design1) and one of the transformed designs (Design3) are also presented. The results of the transformed design are in good agreement with those of Design1 considering fabrication and measurement tolerances.

@article{
 title = {ZnO Etching and Microtunnel Fabrication for High-Reliability MEMS Acoustic Sensor},
 type = {article},
 year = {2014},
 keywords = {Electrolytes,Electrolytic copper addition,II-VI semiconductors,MEMS acoustic sensor,Micromachining,Si-diaphragm,TMAH,ZnO,ZnO film,ZnO layer etching,aluminum metal,bulk micromachining,current 2.5 A,current 3.0 A,current 40 mA,electrical testing,electrolytically added copper ions,etchants,frequency 30 Hz to 8000 Hz,microfabrication,microsensors,microtunnel etching,microtunnel fabrication,photoresist SU8,photoresists,pressure compensation,reliability,silicon diaphragm,wide band gap semiconductors,zinc compounds},
 pages = {545-554},
 volume = {14},
 websites = {http://ieeexplore.ieee.org/lpdocs/epic03/wrapper.htm?arnumber=6547706},
 month = {3},
 id = {9cc7d428-8c1d-3a60-84bc-96c2402f7d96},
 created = {2015-12-15T06:02:07.000Z},
 accessed = {2015-12-15},
 file_attached = {true},
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 last_modified = {2018-08-04T08:25:18.239Z},
 read = {false},
 starred = {false},
 authored = {true},
 confirmed = {true},
 hidden = {false},
 citation_key = {Prasad2014a},
 short_title = {Device and Materials Reliability, IEEE Transaction},
 folder_uuids = {eb474840-5125-4032-aab7-41ddd99e1ea7},
 private_publication = {false},
 abstract = {This paper describes a technique for uniform step coverage of aluminum metal (Al) on ZnO film in the fabrication of MEMS acoustic sensor. The MEMS acoustic sensors were fabricated by etching ZnO layer in three different etchants: HCl, NH4Cl with electrolytically added copper ions, and NH4OH with electrolytically added copper ions. For the first time, a technique is reported, which uses aqueous NH4OH solution with electrolytically added copper ions for etching of ZnO layer. For reliable operation of the device, the electrical testing of Al step coverage on ZnO layer was performed. The maximum currents that can be drawn across Al-deposited ZnO edge etched by HCl, Cu-added NH4Cl, and Cu-added NH4OH were 40 mA, 2.5 A, and 3.0 A respectively, without any damage to the structures. The investigations show that uniform Al step coverage on ZnO layer is obtained in case of NH4OH with electrolytically added copper ions. During fabrication of the device, a novel technique for building a microtunnel for pressure compensation was also developed. This microtunnel is used to compensate the pressure applied on the silicon diaphragm by connecting the cavity to the atmosphere. To realize the smooth inlet of microtunnel in the cavity, photoresist SU8 was used for patterning the cavity after microtunnel etching. The developed technique for microtunnel fabrication reduces the process complexity, providing improved yield of the device. The packaged device performed satisfactorily in the sound pressure level (SPL) of 120-160 dB over a wide frequency range of 30-8000 Hz. The maximum sensitivity of the sensor was measured as 380 μV/Pa.},
 bibtype = {article},
 author = {Prasad, Mahanth and Sahula, Vineet and Khanna, Vinod Kumar},
 doi = {10.1109/TDMR.2013.2271245},
 journal = {IEEE Transactions on Device and Materials Reliability},
 number = {1}
}

This paper describes a technique for uniform step coverage of aluminum metal (Al) on ZnO film in the fabrication of MEMS acoustic sensor. The MEMS acoustic sensors were fabricated by etching ZnO layer in three different etchants: HCl, NH4Cl with electrolytically added copper ions, and NH4OH with electrolytically added copper ions. For the first time, a technique is reported, which uses aqueous NH4OH solution with electrolytically added copper ions for etching of ZnO layer. For reliable operation of the device, the electrical testing of Al step coverage on ZnO layer was performed. The maximum currents that can be drawn across Al-deposited ZnO edge etched by HCl, Cu-added NH4Cl, and Cu-added NH4OH were 40 mA, 2.5 A, and 3.0 A respectively, without any damage to the structures. The investigations show that uniform Al step coverage on ZnO layer is obtained in case of NH4OH with electrolytically added copper ions. During fabrication of the device, a novel technique for building a microtunnel for pressure compensation was also developed. This microtunnel is used to compensate the pressure applied on the silicon diaphragm by connecting the cavity to the atmosphere. To realize the smooth inlet of microtunnel in the cavity, photoresist SU8 was used for patterning the cavity after microtunnel etching. The developed technique for microtunnel fabrication reduces the process complexity, providing improved yield of the device. The packaged device performed satisfactorily in the sound pressure level (SPL) of 120-160 dB over a wide frequency range of 30-8000 Hz. The maximum sensitivity of the sensor was measured as 380 μV/Pa.

@article{
 title = {Long-Term Effects of Relative Humidity on the Performance of ZnO-Based MEMS Acoustic Sensors},
 type = {article},
 year = {2014},
 keywords = {Acoustic measurements,Acoustic sensors,Al,Capacitance,Etching,Humidity,Loss measurement,MEMS acoustic sensor,MEMS acoustic sensors,PECVD layer,PECVD silicon dioxide,Si,Zinc oxide,ZnO,acoustic sensor chip,aluminum electrodes,bulk micromachining,bulk micromachining technique,dissipation factor,etching,fabrication process,frequency response,humid environment conditions,humidity,micromachining,microsensors,passivating layer,passivation,plasma CVD,relative humidity,sensitivity response,silicon diaphragm,size 0.3 mum,size 25 mum,weak acid},
 pages = {778-780},
 volume = {14},
 websites = {http://ieeexplore.ieee.org/lpdocs/epic03/wrapper.htm?arnumber=6798753},
 month = {6},
 id = {347d8b64-c236-319a-b9ee-fd30ee88de20},
 created = {2015-12-15T06:02:07.000Z},
 accessed = {2015-12-15},
 file_attached = {false},
 profile_id = {03d2ca17-6bde-3cfe-95de-fcbe4f21507b},
 last_modified = {2018-08-04T08:25:18.847Z},
 read = {false},
 starred = {false},
 authored = {true},
 confirmed = {true},
 hidden = {false},
 citation_key = {Prasad2014},
 short_title = {Device and Materials Reliability, IEEE Transaction},
 folder_uuids = {eb474840-5125-4032-aab7-41ddd99e1ea7},
 private_publication = {false},
 abstract = {This paper investigates the long-term repercussions of relative humidity on capacitance and dissipation factor tan δ of ZnO-based MEMS acoustic sensors. During the fabrication process, a ZnO layer covered with a 0.3-μm-thick PECVD layer was sandwiched between two aluminum (Al) electrodes on a 25-μm-thick silicon diaphragm made by a bulk micromachining technique. The fabrication of an acoustic sensor chip was then completed by etching a ZnO layer in the presence of strong acid (HCl) and weak acid (NH4Cl with electrolytically added Cu ions), separately. Post fabrication, under the humid environment conditions prevailing over a long period of time, viz., 150 days, with relative humidity between 60% and 80%, the capacitance values were found to be 1.5 times higher than the original values in the case of strong acid. The corresponding losses tan δ increased from 0.03 to 0.06. However, under the same conditions, the capacitance values did not change for the acoustic chips fabricated using weak acid. The deterioration in frequency and sensitivity responses of the packaged device has been also observed in the case of etching using strong acid. The investigations showed that a 0.3-μm-thick PECVD silicon dioxide as a passivating layer could protect the sensors from ambient humidity over a long period of time, because of a positive slope of a ZnO edge. However, the response of the devices for a negative slope of a ZnO edge was affected due to nonuniform step coverage of a ZnO layer.},
 bibtype = {article},
 author = {Prasad, M. and Sahula, V. and Khanna, V.K.},
 doi = {10.1109/TDMR.2014.2317415},
 journal = {IEEE Transactions on Device and Materials Reliability},
 number = {2}
}

This paper investigates the long-term repercussions of relative humidity on capacitance and dissipation factor tan δ of ZnO-based MEMS acoustic sensors. During the fabrication process, a ZnO layer covered with a 0.3-μm-thick PECVD layer was sandwiched between two aluminum (Al) electrodes on a 25-μm-thick silicon diaphragm made by a bulk micromachining technique. The fabrication of an acoustic sensor chip was then completed by etching a ZnO layer in the presence of strong acid (HCl) and weak acid (NH4Cl with electrolytically added Cu ions), separately. Post fabrication, under the humid environment conditions prevailing over a long period of time, viz., 150 days, with relative humidity between 60% and 80%, the capacitance values were found to be 1.5 times higher than the original values in the case of strong acid. The corresponding losses tan δ increased from 0.03 to 0.06. However, under the same conditions, the capacitance values did not change for the acoustic chips fabricated using weak acid. The deterioration in frequency and sensitivity responses of the packaged device has been also observed in the case of etching using strong acid. The investigations showed that a 0.3-μm-thick PECVD silicon dioxide as a passivating layer could protect the sensors from ambient humidity over a long period of time, because of a positive slope of a ZnO edge. However, the response of the devices for a negative slope of a ZnO edge was affected due to nonuniform step coverage of a ZnO layer.

@article{
 title = {Quick Estimation of Rectangular Patch Antenna Dimensions Based on Equivalent Design Concept},
 type = {article},
 year = {2014},
 keywords = {Bhatnagar postulate,Dielectric constant,Estimation,Microstrip,Microstrip antennas,RMSA design parameters,Resonant frequency,Substrates,approximation method,approximation theory,dielectric constant,equivalence of design concept,microstrip antennas,patch antennas,permittivity,quick estimation,rectangular microstrip antenna,rectangular patch antenna dimensions,resonance frequency,scaling factor,substrate thickness,substrates},
 pages = {1469-1472},
 volume = {13},
 websites = {http://ieeexplore.ieee.org/lpdocs/epic03/wrapper.htm?arnumber=6847143},
 id = {21edf122-9a67-3675-8bd3-02f6bb028c72},
 created = {2016-04-21T16:39:29.000Z},
 accessed = {2015-12-15},
 file_attached = {true},
 profile_id = {03d2ca17-6bde-3cfe-95de-fcbe4f21507b},
 last_modified = {2017-03-14T01:22:09.162Z},
 read = {false},
 starred = {false},
 authored = {true},
 confirmed = {true},
 hidden = {false},
 citation_key = {6847143},
 source_type = {article},
 short_title = {Antennas and Wireless Propagation Letters, IEEE},
 private_publication = {false},
 abstract = {This letter presents a new method for quickly estimating the physical dimensions of a rectangular microstrip antenna (RMSA). This is based on the newly introduced concept of “Equivalence of Design” for RMSA. Two designs are said to be equivalent if they result in the same resonance frequency. This is an outcome of Bhatnagar's postulate. It relates the classical extension in length ΔL with the length and width of the patch apart from the substrate thickness. This letter emphasizes the importance of substrate thickness normalized with respect to guided wavelength. This is termed as the “H” parameter. For RMSA, this is the key parameter rather than the individual parameters-dielectric constant (εr), substrate thickness (h), or resonance frequency (f0). A new parameter-the scaling factor (Ψ)-has been introduced and defined. Based on these, transformation laws have been put forward. These can be used for quickly estimating the RMSA design parameters from a “known good design.” The laws have been verified by estimating physical parameters of RMSA and then calculating its resonance frequency. This has been repeated for several hundred designs. The matching has been excellent. Simulation and measurement results of a known good design (Design1) and one of the transformed designs (Design3) are also presented. The results of the transformed design are in good agreement with those of Design1 considering fabrication and measurement tolerances.},
 bibtype = {article},
 author = {Mathur, Dhirendra and Bhatnagar, S. K. and Sahula, Vineet},
 doi = {10.1109/LAWP.2014.2334362},
 journal = {Antennas and Wireless Propagation Letters, IEEE},
 number = {99}
}

This letter presents a new method for quickly estimating the physical dimensions of a rectangular microstrip antenna (RMSA). This is based on the newly introduced concept of “Equivalence of Design” for RMSA. Two designs are said to be equivalent if they result in the same resonance frequency. This is an outcome of Bhatnagar's postulate. It relates the classical extension in length ΔL with the length and width of the patch apart from the substrate thickness. This letter emphasizes the importance of substrate thickness normalized with respect to guided wavelength. This is termed as the “H” parameter. For RMSA, this is the key parameter rather than the individual parameters-dielectric constant (εr), substrate thickness (h), or resonance frequency (f0). A new parameter-the scaling factor (Ψ)-has been introduced and defined. Based on these, transformation laws have been put forward. These can be used for quickly estimating the RMSA design parameters from a “known good design.” The laws have been verified by estimating physical parameters of RMSA and then calculating its resonance frequency. This has been repeated for several hundred designs. The matching has been excellent. Simulation and measurement results of a known good design (Design1) and one of the transformed designs (Design3) are also presented. The results of the transformed design are in good agreement with those of Design1 considering fabrication and measurement tolerances.

@article{
 title = {Long-Term Effects of Relative Humidity on the Performance of ZnO-Based MEMS Acoustic Sensors},
 type = {article},
 year = {2014},
 keywords = {Acoustic measurements,Acoustic sensors,Al,Capacitance,Etching,Humidity,Loss measurement,MEMS acoustic sensor,MEMS acoustic sensors,PECVD layer,PECVD silicon dioxide,Si,Zinc oxide,ZnO,acoustic sensor chip,aluminum electrodes,bulk micromachining,bulk micromachining technique,dissipation factor,etching,fabrication process,frequency response,humid environment conditions,humidity,micromachining,microsensors,passivating layer,passivation,plasma CVD,relative humidity,sensitivity response,silicon diaphragm,size 0.3 mum,size 25 mum,weak acid},
 pages = {778-780},
 volume = {14},
 websites = {http://ieeexplore.ieee.org/lpdocs/epic03/wrapper.htm?arnumber=6798753},
 month = {6},
 id = {da4f4da5-5be9-3424-887d-d51a885cdb24},
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 accessed = {2015-12-15},
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 last_modified = {2018-08-09T15:07:49.701Z},
 read = {false},
 starred = {false},
 authored = {true},
 confirmed = {true},
 hidden = {false},
 citation_key = {prasad2013tdmr2},
 source_type = {article},
 short_title = {Device and Materials Reliability, IEEE Transaction},
 private_publication = {false},
 abstract = {This paper investigates the long-term repercussions of relative humidity on capacitance and dissipation factor tan δ of ZnO-based MEMS acoustic sensors. During the fabrication process, a ZnO layer covered with a 0.3-μm-thick PECVD layer was sandwiched between two aluminum (Al) electrodes on a 25-μm-thick silicon diaphragm made by a bulk micromachining technique. The fabrication of an acoustic sensor chip was then completed by etching a ZnO layer in the presence of strong acid (HCl) and weak acid (NH4Cl with electrolytically added Cu ions), separately. Post fabrication, under the humid environment conditions prevailing over a long period of time, viz., 150 days, with relative humidity between 60% and 80%, the capacitance values were found to be 1.5 times higher than the original values in the case of strong acid. The corresponding losses tan δ increased from 0.03 to 0.06. However, under the same conditions, the capacitance values did not change for the acoustic chips fabricated using weak acid. The deterioration in frequency and sensitivity responses of the packaged device has been also observed in the case of etching using strong acid. The investigations showed that a 0.3-μm-thick PECVD silicon dioxide as a passivating layer could protect the sensors from ambient humidity over a long period of time, because of a positive slope of a ZnO edge. However, the response of the devices for a negative slope of a ZnO edge was affected due to nonuniform step coverage of a ZnO layer.},
 bibtype = {article},
 author = {Prasad, M. and Sahula, V. and Khanna, V.K.},
 doi = {10.1109/TDMR.2014.2317415},
 journal = {IEEE Transactions on Device and Materials Reliability},
 number = {2}
}

This paper investigates the long-term repercussions of relative humidity on capacitance and dissipation factor tan δ of ZnO-based MEMS acoustic sensors. During the fabrication process, a ZnO layer covered with a 0.3-μm-thick PECVD layer was sandwiched between two aluminum (Al) electrodes on a 25-μm-thick silicon diaphragm made by a bulk micromachining technique. The fabrication of an acoustic sensor chip was then completed by etching a ZnO layer in the presence of strong acid (HCl) and weak acid (NH4Cl with electrolytically added Cu ions), separately. Post fabrication, under the humid environment conditions prevailing over a long period of time, viz., 150 days, with relative humidity between 60% and 80%, the capacitance values were found to be 1.5 times higher than the original values in the case of strong acid. The corresponding losses tan δ increased from 0.03 to 0.06. However, under the same conditions, the capacitance values did not change for the acoustic chips fabricated using weak acid. The deterioration in frequency and sensitivity responses of the packaged device has been also observed in the case of etching using strong acid. The investigations showed that a 0.3-μm-thick PECVD silicon dioxide as a passivating layer could protect the sensors from ambient humidity over a long period of time, because of a positive slope of a ZnO edge. However, the response of the devices for a negative slope of a ZnO edge was affected due to nonuniform step coverage of a ZnO layer.

@inproceedings{
 title = {A Weakly Fault Tolerant Design of Molecular Memory Cell},
 type = {inproceedings},
 year = {2013},
 pages = {1-4},
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 confirmed = {true},
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 private_publication = {false},
 bibtype = {inproceedings},
 author = {Kumawat, Renu and Sahula, Vineet and Gaur, M S},
 booktitle = {4th IEEE International Workshop on Reliability Aware System Design and Test (RASDAT)}
}

@inproceedings{
 title = {Application of Concept Algebra in making inferences and role of Machine Learning},
 type = {inproceedings},
 year = {2013},
 id = {f72ad4ef-31b7-3699-86a3-4cd859ed0e52},
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 hidden = {false},
 citation_key = {Lintu2013},
 private_publication = {false},
 bibtype = {inproceedings},
 author = {Lintu, Rajan and Sahula, Vineet},
 booktitle = {Workshop on Computational Intelligence & TAFD}
}

@article{
 title = {ZnO etching and microtunnel fabrication for high-reliability MEMS acoustic sensor},
 type = {article},
 year = {2013},
 publisher = {IEEE Early Access Articles},
 id = {d792b8c9-ead0-3ba0-bdcc-272d91a37b21},
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 starred = {false},
 authored = {true},
 confirmed = {true},
 hidden = {false},
 citation_key = {PRASAD2013},
 source_type = {article},
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 bibtype = {article},
 author = {PRASAD, M and Sahula, V and Khanna, V},
 journal = {IEEE Transactions on Device and Materials Reliability},
 number = {Digital Object Identifier: 10.1109/TDMR.2013.22712}
}

@article{
 title = {Features classification using geometrical deformation feature vector of support vector machine and active appearance algorithm for automatic facial expression recognition},
 type = {article},
 year = {2013},
 volume = {Early Acce},
 id = {76b4da00-76f0-3be5-a6c6-adf286494366},
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 authored = {true},
 confirmed = {true},
 hidden = {false},
 citation_key = {patil2013mva},
 source_type = {article},
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 bibtype = {article},
 author = {Patil R. A., undefined and Sahula V., undefined and Mandal, A S},
 journal = {Springer's Journal of Machine Vision and Application}
}

@inproceedings{
 title = {Design and fabrication of Si-diaphragm for ZnO-based MEMS acoustic sensor},
 type = {inproceedings},
 year = {2013},
 institution = {Springer CICCS},
 id = {c0d000ab-9815-3fa9-ba21-0ee170f2b5c2},
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 confirmed = {true},
 hidden = {false},
 citation_key = {MahanthPrasad2013},
 source_type = {inproceedings},
 private_publication = {false},
 bibtype = {inproceedings},
 author = {Prasad, Mahanth and Sahula, V and Khanna, V K},
 booktitle = {17th International Symposium on VLSI Design and Test, 2013}
}

@inproceedings{
 title = {Reliable circuit analysis and design using nanoscale devices},
 type = {inproceedings},
 year = {2013},
 pages = {87602C--87602C},
 publisher = {SPIE},
 institution = {International Society for Optics and Photonics},
 id = {a5e4a87a-fbb6-3ce2-aa73-63314d9b71c8},
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 citation_key = {kumawat2013reliable},
 source_type = {inproceedings},
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 bibtype = {inproceedings},
 author = {Kumawat, Renu and Sahula, Vineet and Gaur, M S},
 booktitle = {International Conference on Communication and Electronics System Design}
}

@article{
 title = {Digital image dual watermarking using self-fractional fourier functions, bivariate empirical mode decomposition and error correcting code},
 type = {article},
 year = {2013},
 pages = {1-14},
 publisher = {Springer-Verlag},
 id = {3ae3bf45-e40a-36a5-ac7a-94f95ac0f45b},
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 authored = {true},
 confirmed = {true},
 hidden = {false},
 citation_key = {sharma2013digital},
 source_type = {article},
 private_publication = {false},
 bibtype = {article},
 author = {Sharma, J B and Sharma, K K and Sahula, Vineet},
 journal = {Journal of Optics}
}

@inproceedings{
 title = {Architectural Level Models for Subthreshold Leakage Power Estimation of SRAM Arrays with its Peripherals},
 type = {inproceedings},
 year = {2013},
 institution = {Springer, CICCS},
 id = {1f9ff7a5-eaef-3955-afa3-382b29648a69},
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 citation_key = {NupurNavlakha2013},
 source_type = {inproceedings},
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 bibtype = {inproceedings},
 author = {Navlakha, Nupur and Garg, Lokesh and Boolchandani, Dharmendar and Sahula, Vineet},
 booktitle = {17th International Symposium on VLSI Design and Test, 2013}
}

@article{
 title = {Efficient CMOS subthreshold leakage analysis with improved stack based models in presence of parameter variations},
 type = {article},
 year = {2013},
 volume = {49},
 publisher = {IET},
 id = {40f0c718-62a6-38d7-9b54-e655c1baa6b0},
 created = {2014-04-17T21:17:22.000Z},
 file_attached = {true},
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 starred = {false},
 authored = {true},
 confirmed = {true},
 hidden = {false},
 citation_key = {garg2013efficient},
 source_type = {article},
 folder_uuids = {eb474840-5125-4032-aab7-41ddd99e1ea7},
 private_publication = {false},
 bibtype = {article},
 author = {Garg, Lokesh and Sahula, V},
 journal = {IET Electronic Letters},
 number = {10}
}

@inproceedings{
 title = {Zinc Oxide deposition and etching for MEMS acoustic sensor},
 type = {inproceedings},
 year = {2013},
 id = {ea47a74c-848e-3722-9817-202e57f2a56c},
 created = {2015-04-19T06:07:18.000Z},
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 authored = {true},
 confirmed = {true},
 hidden = {false},
 citation_key = {Prasad2013a},
 private_publication = {false},
 bibtype = {inproceedings},
 author = {Prasad, Mahanth and Sahula, Vineet (MNIT Jaipur) and Khanna, V. K.},
 booktitle = {Journal of Sensor Techniques & Applications}
}

@article{
 title = {Energy Aware Task Scheduling for Soft Real Time Systems using an Analytical Approach for Energy Estimation},
 type = {article},
 year = {2013},
 pages = {12},
 volume = {abs/1303.0},
 websites = {http://arxiv.org/abs/1303.0725},
 id = {ae73452b-f831-385e-bb4b-4e07779e8d67},
 created = {2016-04-21T15:37:49.000Z},
 file_attached = {true},
 profile_id = {03d2ca17-6bde-3cfe-95de-fcbe4f21507b},
 last_modified = {2017-03-14T01:22:09.162Z},
 read = {false},
 starred = {false},
 authored = {true},
 confirmed = {true},
 hidden = {false},
 citation_key = {Sharma2013},
 private_publication = {false},
 abstract = {Embedded systems have pervaded all walks of our life. With the increasing importance of mobile embedded systems and flexible applications, considerable progress in research has been made for power management. Power constraints are increasingly becoming the critical component of the design specifications of these systems. It helps in pre-determining the suitable hardware architecture for the target application. The aim of this paper is to present a technique to estimate 'pre-run time' and 'power' of a software mapped onto a hardware system; guaranteeing the compliance of temporal constraints while generating a schedule of tasks of software. Real time systems must handle several independent macro-tasks, each represented by a task graph, which includes communications and precedence constraints. We propose a novel approach for power estimation of embedded software using the Control Data Flow Graph (CDFG) or task graph model. This methodology uses an existing Hierarchical Concurrent Flow Graph (HCFG) technique for the power analysis of the CDFGs. We have evaluated our technique for energy efficient scheduling over various task graph benchmarks. The results obtained prove the utility and efficacy of our proposed approach for power analysis of embedded software. We also present a methodology to obtain an energy optimal voltage assignment and perform scheduling by taking advantage of the relaxation in execution time of tasks.},
 bibtype = {article},
 author = {Sharma, Namita and Sahula, Vineet and Ravikumar, C. P.},
 journal = {International Journal of Advanced Studies in Computers, Science and Engineering (IJASCSE)}
}

Embedded systems have pervaded all walks of our life. With the increasing importance of mobile embedded systems and flexible applications, considerable progress in research has been made for power management. Power constraints are increasingly becoming the critical component of the design specifications of these systems. It helps in pre-determining the suitable hardware architecture for the target application. The aim of this paper is to present a technique to estimate 'pre-run time' and 'power' of a software mapped onto a hardware system; guaranteeing the compliance of temporal constraints while generating a schedule of tasks of software. Real time systems must handle several independent macro-tasks, each represented by a task graph, which includes communications and precedence constraints. We propose a novel approach for power estimation of embedded software using the Control Data Flow Graph (CDFG) or task graph model. This methodology uses an existing Hierarchical Concurrent Flow Graph (HCFG) technique for the power analysis of the CDFGs. We have evaluated our technique for energy efficient scheduling over various task graph benchmarks. The results obtained prove the utility and efficacy of our proposed approach for power analysis of embedded software. We also present a methodology to obtain an energy optimal voltage assignment and perform scheduling by taking advantage of the relaxation in execution time of tasks.

@article{
 title = {Efficient CMOS subthreshold leakage analysis with improved stack based models in presence of parameter variations},
 type = {article},
 year = {2013},
 keywords = {CMOS gates,CMOS integrated circuits,CMOS subthreshold leakage analysis,electronic engineering computing,leakage power models,parallel transistor stacks,parameter variations,stack based models,support vector machine,support vector machines,transistor circuits},
 pages = {644-646},
 volume = {49},
 websites = {http://digital-library.theiet.org/content/journals/10.1049/el.2012.4311},
 month = {5},
 publisher = {IET},
 day = {9},
 id = {a66f7bc1-631b-3d1c-acf4-1016bbf2b029},
 created = {2016-04-21T16:39:29.000Z},
 accessed = {2015-12-15},
 file_attached = {true},
 profile_id = {03d2ca17-6bde-3cfe-95de-fcbe4f21507b},
 last_modified = {2017-03-14T01:22:09.162Z},
 read = {false},
 starred = {false},
 authored = {true},
 confirmed = {true},
 hidden = {false},
 citation_key = {garg2013efficient},
 source_type = {article},
 short_title = {Electronics Letters},
 private_publication = {false},
 abstract = {Presented is the error that occurs while estimating subthreshold leakage power of parallel transistor stacks in CMOS gates using leakage power models when there is no consideration of the manufacturing variations, i.e. device geometry related effects in width. For the purpose, efficient support vector machine based macromodels for characterising the transistor stacks of CMOS gates are reported, considering process parameter variations impacting e.g. length, threshold voltage, oxide thickness, supply voltage, temperature and width of the transistors. The experiments show that maximum error can go up to ~15% for AOI22 and OAI22 gate under nominal values of varying parameters without considering manufacturing variations in the width.},
 bibtype = {article},
 author = {Garg, Lokesh and Sahula, V.},
 doi = {10.1049/el.2012.4311},
 journal = {IET Electronic Letters},
 number = {10}
}

Presented is the error that occurs while estimating subthreshold leakage power of parallel transistor stacks in CMOS gates using leakage power models when there is no consideration of the manufacturing variations, i.e. device geometry related effects in width. For the purpose, efficient support vector machine based macromodels for characterising the transistor stacks of CMOS gates are reported, considering process parameter variations impacting e.g. length, threshold voltage, oxide thickness, supply voltage, temperature and width of the transistors. The experiments show that maximum error can go up to ~15% for AOI22 and OAI22 gate under nominal values of varying parameters without considering manufacturing variations in the width.

@article{
 title = {Design and fabrication of Si-diaphragm, ZnO piezoelectric film-based MEMS acoustic sensor using SOI wafers},
 type = {article},
 year = {2013},
 keywords = {ANSYS,Acoustic sensors,Al metallization,Cavity resonators,Diaphragm,Etching,Fabrication,MEMS acoustic sensor,PECVD SiO2,SOI wafer,Sensitivity,Si,Si-diaphragm,SiO2,Silicon,Zinc oxide,ZnO,acoustic pressure,aluminium,aluminum electrode,c-axis-oriented ZnO film,capacitor electrode,chemical vapour deposition,frequency 30 Hz to 8000 Hz,glass particle,microelectromechanical system,micromechanical devices,microtunnel blockage,piezoelectric thin film,piezoelectric thin films,piezoelectric zinc oxide,silicon particle,silicon-on-insulator,silicon-on-insulator (SOI) substrate,silicon-on-insulator wafer,size 0.2 micron,size 2.4 micron,size 25 micron,sound pressure level,sound pressure level (SPL),stress distribution,thin film,zinc compounds,zinc oxide (ZnO) film},
 pages = {233-241},
 volume = {26},
 websites = {http://ieeexplore.ieee.org/lpdocs/epic03/wrapper.htm?arnumber=6410046},
 month = {5},
 id = {f5557351-24b6-3534-80da-730baa1b6b12},
 created = {2016-04-21T16:39:30.000Z},
 accessed = {2015-12-15},
 file_attached = {true},
 profile_id = {03d2ca17-6bde-3cfe-95de-fcbe4f21507b},
 last_modified = {2017-03-14T01:22:09.162Z},
 read = {false},
 starred = {false},
 authored = {true},
 confirmed = {true},
 hidden = {false},
 citation_key = {Prasad2013},
 short_title = {Semiconductor Manufacturing, IEEE Transactions on},
 private_publication = {false},
 abstract = {This paper reports a simpler technique for fabricating an acoustic sensor based on a piezoelectric zinc oxide (ZnO) thin film, utilizing silicon-on-insulator wafers. A highly c-axis-oriented ZnO film of thickness 2.4 murm m, which is covered with 0.2-murm m-thick PECVD rm SiO2, is sandwiched between two aluminum electrodes on a 25- murm m-thick silicon diaphragm. This diaphragm thickness has been optimized to withstand sound pressure level range of 120160 dB. Stress distribution studies using ANSYS have been performed to determine the locations for placement of capacitor electrodes. This paper also reports a technique for the creation of a positive slope of the ZnO step to ensure proper coverage during Al metallization. In order to maximize yield, process steps have been developed to avoid the microtunnel blockage by silicon/glass particles. The packaged sensor is found to exhibit a sensitivity of 382 murm V/Pa (RMS) in the frequency range from 30 to 8000 Hz, under varying acoustic pressure.},
 bibtype = {article},
 author = {Prasad, Mahanth and Sahula, Vineet and Khanna, Vinod Kumar},
 doi = {10.1109/TSM.2013.2238956},
 journal = {IEEE Transactions on Semiconductor Manufacturing},
 number = {2}
}

This paper reports a simpler technique for fabricating an acoustic sensor based on a piezoelectric zinc oxide (ZnO) thin film, utilizing silicon-on-insulator wafers. A highly c-axis-oriented ZnO film of thickness 2.4 murm m, which is covered with 0.2-murm m-thick PECVD rm SiO2, is sandwiched between two aluminum electrodes on a 25- murm m-thick silicon diaphragm. This diaphragm thickness has been optimized to withstand sound pressure level range of 120160 dB. Stress distribution studies using ANSYS have been performed to determine the locations for placement of capacitor electrodes. This paper also reports a technique for the creation of a positive slope of the ZnO step to ensure proper coverage during Al metallization. In order to maximize yield, process steps have been developed to avoid the microtunnel blockage by silicon/glass particles. The packaged sensor is found to exhibit a sensitivity of 382 murm V/Pa (RMS) in the frequency range from 30 to 8000 Hz, under varying acoustic pressure.

@inproceedings{
 title = {Probabilistic Modeling Approaches for Nanoscale Devices},
 type = {inproceedings},
 year = {2013},
 keywords = {Analytical models,Bayesian Network,Complexity theory,Logic gates,Markov Random Field,Nanoscale devices,Probabilistic Decision Diagrams,Probabilistic Transfer Matrices,Probabilistic logic,Reliability,Switches,probabilistic modeling,reliability,soft transient errors},
 pages = {720-724},
 websites = {http://ieeexplore.ieee.org/lpdocs/epic03/wrapper.htm?arnumber=6528997},
 month = {3},
 publisher = {IEEE},
 id = {8efb4d48-abc2-3f3b-bb97-3fdcc9f47f2e},
 created = {2016-05-03T16:18:00.000Z},
 accessed = {2015-12-15},
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 read = {false},
 starred = {false},
 authored = {true},
 confirmed = {true},
 hidden = {false},
 citation_key = {kumawat2013iccpct},
 source_type = {inproceedings},
 short_title = {Circuits, Power and Computing Technologies (ICCPCT},
 private_publication = {false},
 abstract = {The continual downsizing of silicon technology to nanoscale has enabled the realization of ultra high density, low power chips. However, such devices are inherently unreliable, contingent and prone to soft transient errors. As the deterministic approaches fail to model their behavior, and estimate the effect of soft transient errors on nanoscale devices, many probabilistic approaches have been proposed in literatures. In this manuscript, a comparative study of many of these approaches is presented. A computational framework based on Markov Random Field, Probabilistic Transfer Matrices and Probabilistic Decision Diagram is developed using MATLAB for design and analysis of combinational circuits at nanoscale. It is observed that Bayesian Network and Probabilistic Decision Diagrams have least time complexity among these approaches. The Probabilistic Transfer Matrices and Markov Random Fields are difficult to scale as they require lot of memory and long simulation time. However, Probabilistic Transfer Matrices provide more accurate output error probability.},
 bibtype = {inproceedings},
 author = {Kumawat, Renu and Sahula, Vineet and Gaur, Manoj Singh},
 doi = {10.1109/ICCPCT.2013.6528997},
 booktitle = {IEEE International conference on circuit, power and computing technologies ICCPCT-2013}
}

The continual downsizing of silicon technology to nanoscale has enabled the realization of ultra high density, low power chips. However, such devices are inherently unreliable, contingent and prone to soft transient errors. As the deterministic approaches fail to model their behavior, and estimate the effect of soft transient errors on nanoscale devices, many probabilistic approaches have been proposed in literatures. In this manuscript, a comparative study of many of these approaches is presented. A computational framework based on Markov Random Field, Probabilistic Transfer Matrices and Probabilistic Decision Diagram is developed using MATLAB for design and analysis of combinational circuits at nanoscale. It is observed that Bayesian Network and Probabilistic Decision Diagrams have least time complexity among these approaches. The Probabilistic Transfer Matrices and Markov Random Fields are difficult to scale as they require lot of memory and long simulation time. However, Probabilistic Transfer Matrices provide more accurate output error probability.

@inproceedings{
 title = {Process Variation Tolerant SRAM Design for Ultra Low Power Applications},
 type = {inproceedings},
 year = {2013},
 keywords = {Low power SRAM,Low voltage/Subthreshold SRAM Design,Process variation,Schmitt trigger},
 pages = {242-248},
 volume = {382 CCIS},
 institution = {Springer CICCS},
 id = {4e7a66f5-e440-3b1d-b570-d16830505ede},
 created = {2016-05-10T02:54:42.000Z},
 file_attached = {true},
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 starred = {false},
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 confirmed = {true},
 hidden = {false},
 citation_key = {Sahula2013},
 source_type = {inproceedings},
 private_publication = {false},
 abstract = {Continued scaling of CMOS technologies has resulted in process variations emerging as a critical design concern. The power consumption requirement in portable devices is even more strictly constrained for extending the battery operating lifetime. In this work, we propose an asymmetrical Schmitt trigger based SRAM cell, suitable for ultra low power applications. It addresses the fundamental conflicting design requirement of read versus write operation of conventional 6T cell. A built-in feedback mechanism proposed for the cell, makes it more robust against process variations. Usually, a Schmitt trigger cell configuration has been used in literature for improving stability of inverter-pair. We propose asymmetrical cell-configuration as modification over this usual Schmitt-trigger based configuration so that the design becomes more tolerant of mismatch in neighboring transistors. Simulation results show that proposed bitcell operates on a very low leakage current and with much less power dissipation compared to 6T cell. © Springer-Verlag Berlin Heidelberg 2013.},
 bibtype = {inproceedings},
 author = {Cherukat, Saima and Sahula, V.},
 doi = {10.1007/978-3-642-42024-5_29},
 booktitle = {17th International Symposium on VLSI Design and Test, 2013}
}

Continued scaling of CMOS technologies has resulted in process variations emerging as a critical design concern. The power consumption requirement in portable devices is even more strictly constrained for extending the battery operating lifetime. In this work, we propose an asymmetrical Schmitt trigger based SRAM cell, suitable for ultra low power applications. It addresses the fundamental conflicting design requirement of read versus write operation of conventional 6T cell. A built-in feedback mechanism proposed for the cell, makes it more robust against process variations. Usually, a Schmitt trigger cell configuration has been used in literature for improving stability of inverter-pair. We propose asymmetrical cell-configuration as modification over this usual Schmitt-trigger based configuration so that the design becomes more tolerant of mismatch in neighboring transistors. Simulation results show that proposed bitcell operates on a very low leakage current and with much less power dissipation compared to 6T cell. © Springer-Verlag Berlin Heidelberg 2013.

@article{
 title = {Design and simulation of Pt-based microhotplate, and fabrication of suspended dielectric membrane by bulk micromachining},
 type = {article},
 year = {2012},
 pages = {3-4},
 websites = {http://proceedings.spiedigitallibrary.org/proceeding.aspx?articleid=1380899},
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 author = {Prasad, Mahanth and Yadav, RP},
 journal = {… on Physics of …}
}

@article{
 title = {Variability aware SVM macromodel based design centering of analog circuits},
 type = {article},
 year = {2012},
 pages = {77-87},
 volume = {73},
 publisher = {Springer},
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 citation_key = {boolchandani2012variability},
 source_type = {article},
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 bibtype = {article},
 author = {Boolchandani, D and Garg, Lokesh and Khandelwal, Sapna and Sahula, Vineet},
 journal = {Analog Integrated Circuits and Signal Processing},
 number = {1}
}

@article{
 title = {Features classification using support vector machine for a facial expression recognition system},
 type = {article},
 year = {2012},
 pages = {43001-43003},
 volume = {21},
 publisher = {International Society for Optics and Photonics},
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 bibtype = {article},
 author = {Patil, Rajesh A and Sahula, Vineet and Mandal, Atanendu S},
 journal = {Journal of Electronic Imaging},
 number = {4}
}

@article{
 title = {Energy Aware Task Scheduling for Soft Real Time Systems using an Analytical Approach for Energy Estimation},
 type = {article},
 year = {2012},
 pages = {33-39},
 volume = {1},
 publisher = {ISSN 2278-7917},
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 citation_key = {sharma2012energy},
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 folder_uuids = {eb474840-5125-4032-aab7-41ddd99e1ea7},
 private_publication = {false},
 bibtype = {article},
 author = {Sharma, Namita and Sahula, Vineet and Ravikumar, C P},
 journal = {International Journal of Advanced Studies in Computers, Science and Engineering},
 number = {4}
}

@inproceedings{
 title = {Reliability Evaluation of Redundancy based Fault Tolerant Techniques at Nanoscale},
 type = {inproceedings},
 year = {2012},
 id = {2bb1dfd0-eadc-3b73-8df9-189fdfd5efa5},
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 confirmed = {true},
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 citation_key = {soni2012rasdat},
 source_type = {inproceedings},
 private_publication = {false},
 bibtype = {inproceedings},
 author = {Soni, Mahesh and Kumawat, R and Sahula, V and Gaur, M S},
 booktitle = {3rd IEEE Workshop Reliability Aware System Design and Test}
}

@inproceedings{
 title = {Design and mathematical model of a ZnO-based MEMS acoustic sensor},
 type = {inproceedings},
 year = {2012},
 pages = {85491D--1},
 volume = {8549},
 institution = {Proc. of SPIE},
 id = {e1b95c51-1f05-34be-a9ef-fd6bcb2e4cc3},
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 starred = {false},
 authored = {true},
 confirmed = {true},
 hidden = {false},
 citation_key = {Prasad2012a},
 source_type = {inproceedings},
 private_publication = {false},
 bibtype = {inproceedings},
 author = {Prasad, Mahanth and Yadav, R P and Sahula, V and Khanna, V K},
 booktitle = {16th International Workshop on Physics of Semiconductor Devices}
}

@inproceedings{
 title = {Variability aware support vector machine based macromodels for statistical estimation of subthreshold leakage power},
 type = {inproceedings},
 year = {2012},
 keywords = {CMOS gates,CMOS logic circuits,Logic gates,MOS devices,MOSFET,Mathematical model,Monte Carlo methods,Monte Carlo simulations,NOR gate,Probability density function (pdf),Process variation,SPICE,SVM based models,Subthreshold leakage power,Support Vector Machine (SVM),Support vector machines,Training,Transistors,circuit analysis computing,integrated circuit modelling,logic gates,mean deviation estimation,size 45 nm to 200 nm,stack based macromodel,standard deviation estimation,statistical analysis,statistical estimation,statistical subthreshold leakage power characteriz,subthreshold leakage power,support vector machines,temperature 0 degC to 100 degC,transistor stacks,variability aware support vector machine based mac,voltage 0.6 V to 1.2 V},
 pages = {253-256},
 websites = {http://ieeexplore.ieee.org/lpdocs/epic03/wrapper.htm?arnumber=6339387},
 month = {9},
 publisher = {IEEE},
 id = {4e88b5ea-480f-3ecf-b74d-dc0646f86446},
 created = {2016-04-21T16:39:30.000Z},
 accessed = {2015-12-15},
 file_attached = {true},
 profile_id = {03d2ca17-6bde-3cfe-95de-fcbe4f21507b},
 last_modified = {2018-08-05T03:34:07.239Z},
 read = {false},
 starred = {false},
 authored = {true},
 confirmed = {true},
 hidden = {false},
 citation_key = {Garg2012a},
 short_title = {Synthesis, Modeling, Analysis and Simulation Metho},
 private_publication = {false},
 abstract = {In this paper, we present an accurate and efficient stack based macromodel for statistical subthreshold leakage power characterization of cmos gates. Our methodology is based on first characterizing the leakage power of basic stacks and then estimating the subthreshold leakage power of gates based on these stacks. We develop support vector machine (SVM) based macromodels to characterize the transistor stacks of cmos gates, while accounting the combined effect of process variation in length (L), threshold voltage (Vth), oxide thickness (Tox), supply voltage (0.6v-1.2v), temperature (0°C-100°C) and width (45nm-200nm) scalable at the same time. Our experiments show that we only need 30 stack models to predict the subthreshold leakage power of 7 basic gates across 58 input combinations. SVM based models have the ability to predict the leakage power with maximum average error of less than 0.634% in mean for 4 input NOR gate and maximum average error of 1.952% in standard deviation for 3 input NOR gate. Our results also show that there is on the average 17× improvement in runtime for estimating the mean and standard deviation of leakage power of a gate with 5000 Monte Carlo simulations.},
 bibtype = {inproceedings},
 author = {Garg, Lokesh and Sahula, Vineet},
 doi = {10.1109/SMACD.2012.6339387},
 booktitle = {IEEE International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)}
}

In this paper, we present an accurate and efficient stack based macromodel for statistical subthreshold leakage power characterization of cmos gates. Our methodology is based on first characterizing the leakage power of basic stacks and then estimating the subthreshold leakage power of gates based on these stacks. We develop support vector machine (SVM) based macromodels to characterize the transistor stacks of cmos gates, while accounting the combined effect of process variation in length (L), threshold voltage (Vth), oxide thickness (Tox), supply voltage (0.6v-1.2v), temperature (0°C-100°C) and width (45nm-200nm) scalable at the same time. Our experiments show that we only need 30 stack models to predict the subthreshold leakage power of 7 basic gates across 58 input combinations. SVM based models have the ability to predict the leakage power with maximum average error of less than 0.634% in mean for 4 input NOR gate and maximum average error of 1.952% in standard deviation for 3 input NOR gate. Our results also show that there is on the average 17× improvement in runtime for estimating the mean and standard deviation of leakage power of a gate with 5000 Monte Carlo simulations.

@article{
 title = {Controlled Chemical Etching of ZnO Film for Step Coverage in MEMS Acoustic Sensor},
 type = {article},
 year = {2012},
 keywords = {Aluminum,Copper,Electrodes,Electrolytic copper addition,Etching,Fabrication,II-VI semiconductors,MEMS acoustic sensor,RF magnetron sputtering film deposition,Si,Sputtering,Zinc oxide,ZnO,acoustic transducers,controlled chemical etching,electrochemical electrodes,electrolytical added copper ion,film electrode formation,hanging structure,microsensors,negative profile,piezoelectric ZnO film,piezoelectric semiconductors,positive slope,resistivity 10 ohmcm to 20 ohmcm,semiconductor thin films,size 1.3 mum to 3.4 mum,sputter deposition,sputter etching,step coverage,step coverage problem,wafer suspension,wet etching technique,wetting,wide band gap semiconductors,zinc compounds},
 pages = {517-519},
 volume = {21},
 websites = {http://ieeexplore.ieee.org/lpdocs/epic03/wrapper.htm?arnumber=6175094},
 month = {6},
 id = {743b00f9-e399-35e3-ab10-f8d2354ad5fa},
 created = {2016-04-21T16:39:30.000Z},
 accessed = {2015-12-15},
 file_attached = {true},
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 last_modified = {2017-03-14T01:22:09.162Z},
 read = {false},
 starred = {false},
 authored = {true},
 confirmed = {true},
 hidden = {false},
 citation_key = {6175094},
 source_type = {article},
 short_title = {Microelectromechanical Systems, Journal of},
 private_publication = {false},
 abstract = {In this letter, we report a novel wet etching technique of a c -axis-oriented ZnO film that solves the step coverage problem during formation of electrodes on this film. The negative profile or hanging structure of ZnO film deposited by RF magnetron sputtering was obtained during wet etching in HCl and NH4Cl solutions. The developed technique uses aqueous NH4Cl with electrolytically added copper ions. By suspending the wafer in the horizontal direction in a 20% NH4Cl solution, positive slope (more than 90 °) was obtained at the edge of the ZnO film. In this process, p-type 〈100〉 silicon wafers of 10-20-Ω·cm resistivity have been used. Al deposition was done to confirm the step coverage on ZnO film after getting the positive slope. The thickness of ZnO film was varied from 1.3 to 3.4 μm to observe the coverage of sidewall of ZnO film. The structure was also electrically tested and was found to function satisfactorily.},
 bibtype = {article},
 author = {Prasad, Mahanth and Yadav, R. P. and Sahula, V. and Khanna, V. K. and Shekhar, Chandra},
 doi = {10.1109/JMEMS.2012.2189362},
 journal = {IEEE Journal of Microelectromechanical Systems},
 number = {3}
}

In this letter, we report a novel wet etching technique of a c -axis-oriented ZnO film that solves the step coverage problem during formation of electrodes on this film. The negative profile or hanging structure of ZnO film deposited by RF magnetron sputtering was obtained during wet etching in HCl and NH4Cl solutions. The developed technique uses aqueous NH4Cl with electrolytically added copper ions. By suspending the wafer in the horizontal direction in a 20% NH4Cl solution, positive slope (more than 90 °) was obtained at the edge of the ZnO film. In this process, p-type 〈100〉 silicon wafers of 10-20-Ω·cm resistivity have been used. Al deposition was done to confirm the step coverage on ZnO film after getting the positive slope. The thickness of ZnO film was varied from 1.3 to 3.4 μm to observe the coverage of sidewall of ZnO film. The structure was also electrically tested and was found to function satisfactorily.

@inproceedings{
 title = {Power Aware Hardware Prototyping of Multiclass SVM Classifier Through Reconfiguration},
 type = {inproceedings},
 year = {2012},
 keywords = {Arrays,Cohn Kanade database,Dynamic partial reconfiguration,FPGA,Field programmable gate arrays,Hardware,SVM,Support vector machines,Systolic array,Training,Vectors,XILINX EDA tools,anger,complexity reduction,data transfer mechanisms,disgust,dynamic partial reconfiguration,emotion recognition,face recognition,facial expression recognition system,fear,field programmable gate arrays,image classification,memory management,multiclass SVM classifier,pair wise classifier classification,parameter extraction,partial reconfiguration schemes,power aware computing,power aware hardware prototyping,sad,smile,support vector machines,surprise,systolic array,systolic array architecture,systolic arrays,vector multiplication operation,vectors},
 pages = {62-67},
 websites = {http://ieeexplore.ieee.org/lpdocs/epic03/wrapper.htm?arnumber=6167729},
 month = {1},
 publisher = {IEEE},
 id = {218427d5-8a93-3fdc-bc49-d57deea469e3},
 created = {2016-04-21T16:39:31.000Z},
 accessed = {2015-12-15},
 file_attached = {true},
 profile_id = {03d2ca17-6bde-3cfe-95de-fcbe4f21507b},
 last_modified = {2017-03-14T01:22:09.162Z},
 read = {false},
 starred = {false},
 authored = {true},
 confirmed = {true},
 hidden = {false},
 citation_key = {Patil2012},
 short_title = {VLSI Design (VLSID), 2012 25th International Confe},
 private_publication = {false},
 abstract = {This paper presents power aware hardware implementation of multiclass Support Vector Machine on FPGA using systolic array architecture. It uses Partial reconfiguration schemes of XILINX for power optimal implementation of the design. Systolic array architecture provides efficient memory management, reduced complexity, and efficient data transfer mechanisms. Multiclass support vector machine is used as classifier for facial expression recognition system, which identifies one of six basic facial expressions such as smile, surprise, sad, anger, disgust, and fear. The extracted parameters from training phase of the SVM are used to implement testing phase of the SVM on the hardware. In the architecture, vector multiplication operation and classification of pair wise classifiers is designed. A data set of Cohn Kanade database in six different classes is used for training and testing of proposed SVM. This architecture is then partially reconfigured using difference based approach with the help of XILINX EDA tools. For feature classification power reduction is achieved using reconfiguration.},
 bibtype = {inproceedings},
 author = {Patil, Rajesh A. and Gupta, Gauri and Sahula, Vineet and Mandal, A.S. S.},
 doi = {10.1109/VLSID.2012.47},
 booktitle = {Proceedings of the IEEE International Conference on VLSI Design}
}

This paper presents power aware hardware implementation of multiclass Support Vector Machine on FPGA using systolic array architecture. It uses Partial reconfiguration schemes of XILINX for power optimal implementation of the design. Systolic array architecture provides efficient memory management, reduced complexity, and efficient data transfer mechanisms. Multiclass support vector machine is used as classifier for facial expression recognition system, which identifies one of six basic facial expressions such as smile, surprise, sad, anger, disgust, and fear. The extracted parameters from training phase of the SVM are used to implement testing phase of the SVM on the hardware. In the architecture, vector multiplication operation and classification of pair wise classifiers is designed. A data set of Cohn Kanade database in six different classes is used for training and testing of proposed SVM. This architecture is then partially reconfigured using difference based approach with the help of XILINX EDA tools. For feature classification power reduction is achieved using reconfiguration.

@article{
 title = {Controlled chemical etching of ZnO film for step coverage in MEMS acoustic sensor},
 type = {article},
 year = {2012},
 id = {2dd9870d-2919-3953-beb4-f27ab14ca784},
 created = {2017-10-14T03:12:09.169Z},
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@article{
 title = {FEM simulation of platinum-based microhotplate using different dielectric membranes for gas sensing applications},
 type = {article},
 year = {2012},
 pages = {59-65},
 volume = {32},
 publisher = {Emerald Group Publishing Limited},
 id = {c868a30a-829c-3e7d-b947-c0c365c31486},
 created = {2018-08-09T15:05:51.582Z},
 file_attached = {true},
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 last_modified = {2018-08-09T15:08:09.650Z},
 read = {false},
 starred = {false},
 authored = {true},
 confirmed = {true},
 hidden = {false},
 citation_key = {prasad2012fem},
 source_type = {article},
 folder_uuids = {eb474840-5125-4032-aab7-41ddd99e1ea7},
 private_publication = {false},
 abstract = {Purpose - The purpose of this paper is to help reduce power consumption by using platinum-based microhotplate with different dielectric membranes SiO2 and Si3N4 for gas sensing applications, and to develop platinum lift-off process using DC sputtering method for fabrication of platinum resistor. Design/methodology/approach - Semiconductor gas sensors normally require high power consumption because of their elevated operating temperature 300-600C. Considering the thermal resistant and sensitive characteristics of metal platinum as well as heat and electricity insulating characteristics of SiO2, Si3N4 and combination of both, a kind of the Si-substrate microhotplate was designed and simulated using ANSYS 10.0 tool. Thermal oxidation of Si wafer was carried out to get a 1.0?IT/ITm thick SiO2 layer. Pt deposition on oxidized silicon substrate by lift-off was carried out using DC sputtering technique. Findings - The platinum-based microhotplate requires 31.3-70.5?mW power to create the temperature 348-752C for gas sensing applications. The SiO2 membrane can operate the gas sensitive film at higher temperature than the Si3N4 and combination of both the membranes at same power consumption. The paper also presents the FEM simulation of different heating elements like nichrome and tantalum and its comparison to platinum for microhotplate applications. Originality/value - Both the simulation and experimental work provides the low cost, high yield and repeatability in realization of microhotplate. The design and simulation work provides the better selection of heating elements and dielectric membranes. The developed experimental process provides the easy fabrication of platinum resistors using DC sputtering technique. © 2012 Emerald Group Publishing Limited. All rights reserved.},
 bibtype = {article},
 author = {Prasad, Mahanth and Yadav, R.P. P and Sahula, V. and Khanna, V.K. K},
 doi = {10.1108/02602281211197152},
 journal = {Sensor Review},
 number = {1}
}

Purpose - The purpose of this paper is to help reduce power consumption by using platinum-based microhotplate with different dielectric membranes SiO2 and Si3N4 for gas sensing applications, and to develop platinum lift-off process using DC sputtering method for fabrication of platinum resistor. Design/methodology/approach - Semiconductor gas sensors normally require high power consumption because of their elevated operating temperature 300-600C. Considering the thermal resistant and sensitive characteristics of metal platinum as well as heat and electricity insulating characteristics of SiO2, Si3N4 and combination of both, a kind of the Si-substrate microhotplate was designed and simulated using ANSYS 10.0 tool. Thermal oxidation of Si wafer was carried out to get a 1.0?IT/ITm thick SiO2 layer. Pt deposition on oxidized silicon substrate by lift-off was carried out using DC sputtering technique. Findings - The platinum-based microhotplate requires 31.3-70.5?mW power to create the temperature 348-752C for gas sensing applications. The SiO2 membrane can operate the gas sensitive film at higher temperature than the Si3N4 and combination of both the membranes at same power consumption. The paper also presents the FEM simulation of different heating elements like nichrome and tantalum and its comparison to platinum for microhotplate applications. Originality/value - Both the simulation and experimental work provides the low cost, high yield and repeatability in realization of microhotplate. The design and simulation work provides the better selection of heating elements and dielectric membranes. The developed experimental process provides the easy fabrication of platinum resistors using DC sputtering technique. © 2012 Emerald Group Publishing Limited. All rights reserved.

@inproceedings{
 title = {LTCC Technology for Wireless System in Package Architecture: Issues & Challenges},
 type = {inproceedings},
 year = {2011},
 id = {032d4cf8-285d-3a37-9801-d6225697ab67},
 created = {2014-04-17T21:17:22.000Z},
 file_attached = {true},
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 starred = {false},
 authored = {true},
 confirmed = {true},
 hidden = {false},
 citation_key = {mathur2011ltcc},
 source_type = {inproceedings},
 private_publication = {false},
 bibtype = {inproceedings},
 author = {Mathur, D and Bhatnagar, S K and Sahula, V},
 booktitle = {IMAPS System-level package workshop}
}

@article{
 title = {Efficient kernel functions for support vector machine regression model for analog circuits’ performance evaluation},
 type = {article},
 year = {2011},
 pages = {117-128},
 volume = {66},
 publisher = {Springer},
 id = {9c0193d2-e7cc-313d-bc46-cd7b1130c646},
 created = {2014-04-17T21:17:22.000Z},
 file_attached = {true},
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 starred = {false},
 authored = {true},
 confirmed = {true},
 hidden = {false},
 citation_key = {boolchandani2011efficient},
 source_type = {article},
 folder_uuids = {eb474840-5125-4032-aab7-41ddd99e1ea7},
 private_publication = {false},
 bibtype = {article},
 author = {Boolchandani, Dharmendar and Ahmed, Abrar and Sahula, Vineet},
 journal = {Springer's Analog Integrated Circuits and Signal Processing},
 number = {1}
}

@article{
 title = {A Novel Design and Mathematical Model for Sensitivity of a MEMS based Piezoelectric Acoustic Sensor},
 type = {article},
 year = {2011},
 pages = {2211-2216},
 volume = {6},
 id = {97822aad-9b4b-3fe9-a508-7cb4841808cc},
 created = {2014-04-17T21:17:22.000Z},
 file_attached = {true},
 profile_id = {03d2ca17-6bde-3cfe-95de-fcbe4f21507b},
 last_modified = {2017-03-14T01:22:09.162Z},
 read = {false},
 starred = {false},
 authored = {true},
 confirmed = {true},
 hidden = {false},
 citation_key = {Prasad2011},
 source_type = {article},
 private_publication = {false},
 bibtype = {article},
 author = {Prasad, Mahanth and Bhateja, Robin and Yadav, R P and Sahula, V and Khanna, V K},
 journal = {International Journal of Applied Engineering Research},
 number = {18}
}

@article{
 title = {Exploring Efficient Kernel Functions for Support Vector Machine Based Feasibility Models for Analog Circuits},
 type = {article},
 year = {2011},
 volume = {1},
 id = {9e116056-addb-37c2-b9cd-581e23448d3f},
 created = {2014-04-17T21:17:22.000Z},
 file_attached = {true},
 profile_id = {03d2ca17-6bde-3cfe-95de-fcbe4f21507b},
 last_modified = {2017-03-14T01:22:09.162Z},
 read = {false},
 starred = {false},
 authored = {true},
 confirmed = {true},
 hidden = {false},
 citation_key = {boolchandani2011exploring},
 source_type = {article},
 private_publication = {false},
 bibtype = {article},
 author = {Boolchandani, D and Sahula, Vineet},
 journal = {Journal of Design, Analysis and Tools for Integrated Circuits and Systems (JDATICS)},
 number = {1}
}

@article{
 title = {Design and Simulation of Double-spiral Shape Micro-heater for Gas Sensing Applications},
 type = {article},
 year = {2011},
 pages = {135-141},
 volume = {129},
 id = {ce5980e2-26ca-34f7-b82c-09c97d5f1b27},
 created = {2014-04-17T21:17:22.000Z},
 file_attached = {true},
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 authored = {true},
 confirmed = {true},
 hidden = {false},
 citation_key = {mahanth2011design},
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 private_publication = {false},
 bibtype = {article},
 author = {Mahanth Prasad R. P. Yadav, V Sahula and Khanna, V K},
 journal = {Sensors & Transducers Journal},
 number = {6}
}

@article{
 title = {Design and simulation of double-spiral shape micro-heater for gas sensing applications},
 type = {article},
 year = {2011},
 keywords = {ANSYS simulation,Bulk-micromachining,Gas sensor,Microhotplate,Pt-heater},
 pages = {135-141},
 volume = {129},
 id = {23df6439-389e-33b0-8aa3-8c635ce14b20},
 created = {2015-12-27T16:51:05.000Z},
 file_attached = {false},
 profile_id = {03d2ca17-6bde-3cfe-95de-fcbe4f21507b},
 last_modified = {2018-08-04T08:25:26.136Z},
 read = {false},
 starred = {false},
 authored = {true},
 confirmed = {false},
 hidden = {false},
 citation_key = {Prasad2011a},
 folder_uuids = {eb474840-5125-4032-aab7-41ddd99e1ea7},
 private_publication = {false},
 abstract = {The paper presents the design and simulation of double spiral shape micro-heater using ANSYS 10.0 and MATLAB, which requires 12.5 mW-78.3 mW powers to create the temperature 181 °C-1002 °C for gas sensing applications. The results obtained from ANSYS simulation were verified using MATLAB Tool. A platinum-based bulk micro-machined hotplate of size 500 μm × 500 μm has been designed for fabrication as a multi-layer structure on a silicon substrate with thermal silicon dioxide as the supporting membrane, followed by LPCVD (Low pressure chemical vapor deposition) silicon nitride film. Gas sensing film (SnO2) will be deposited on the interdigitated Pt electrodes formed on the PECVD oxide layer. The temperature uniformity of microhotplate (as it is essential for better sensing mechanism) based on double spiral heater has been reported in this paper. To estimate the resistance of the Pt heater, a 2000 A° thick platinum film has been deposited by sputtering on silicon and its sheet resistance has been measured as 2.5 Ohm/□. We have used this value to calculate the resistance of Pt resistor, which was found 319 Ohm. © 2011 IFSA.},
 bibtype = {article},
 author = {Prasad, M. and Yadav, R.P. and Sahula, V. and Khanna, V.K.},
 journal = {Sensors and Transducers},
 number = {6}
}

The paper presents the design and simulation of double spiral shape micro-heater using ANSYS 10.0 and MATLAB, which requires 12.5 mW-78.3 mW powers to create the temperature 181 °C-1002 °C for gas sensing applications. The results obtained from ANSYS simulation were verified using MATLAB Tool. A platinum-based bulk micro-machined hotplate of size 500 μm × 500 μm has been designed for fabrication as a multi-layer structure on a silicon substrate with thermal silicon dioxide as the supporting membrane, followed by LPCVD (Low pressure chemical vapor deposition) silicon nitride film. Gas sensing film (SnO2) will be deposited on the interdigitated Pt electrodes formed on the PECVD oxide layer. The temperature uniformity of microhotplate (as it is essential for better sensing mechanism) based on double spiral heater has been reported in this paper. To estimate the resistance of the Pt heater, a 2000 A° thick platinum film has been deposited by sputtering on silicon and its sheet resistance has been measured as 2.5 Ohm/□. We have used this value to calculate the resistance of Pt resistor, which was found 319 Ohm. © 2011 IFSA.

@inproceedings{
 title = {Nondestructive method for measuring dielectric constant of sheet materials},
 type = {inproceedings},
 year = {2011},
 keywords = {Antenna measurements,Dielectric constant,Dielectric measurements,Frequency measurement,MUT,Microwave measurements,Substrates,aperture antennas,aperture coupled,aperture coupled microstrip antenna,dielectric constant measurement,dielectric materials,frequency 8.4 GHz,material under test,measurement,microstrip antennas,nondestructive method,nondestructive testing,on-line quality control,patch antenna,permittivity measurement,prefabricated antenna,sheet materials},
 pages = {1105-1109},
 websites = {http://ieeexplore.ieee.org/lpdocs/epic03/wrapper.htm?arnumber=6129282},
 month = {11},
 publisher = {IEEE},
 id = {cb497a2d-721d-373d-b6e7-251a5a2d1404},
 created = {2016-04-21T16:39:31.000Z},
 accessed = {2015-12-15},
 file_attached = {true},
 profile_id = {03d2ca17-6bde-3cfe-95de-fcbe4f21507b},
 last_modified = {2017-03-14T01:22:09.162Z},
 read = {false},
 starred = {false},
 authored = {true},
 confirmed = {true},
 hidden = {false},
 citation_key = {Mathur2011},
 short_title = {TENCON 2011 - 2011 IEEE Region 10 Conference},
 private_publication = {false},
 abstract = {In many applications including RF, Microwave dielectric constant (εr) of the material is a key design parameter. Present methods for measurement of εr are time-consuming and require a sample piece of the material on which some processing has to be done (destructive methods). This paper presents a nondestructive and simple method for determining εr of sheet dielectric materials. The method is nondestructive in the sense that cutting of the material or any processing on it is not required. In this method resonant frequency (fr) of a pre-fabricated antenna is first measured with a known material and then again measured with the Material Under Test (MUT) as dielectric part of the microstrip antenna. The parameter εr is then determined from the ratio of these resonant frequencies and the thickness of MUT. The experimentation is arranged so that errors due to measurement in patch dimensions and electrical connections to the feed line are eliminated. The method can be used for on-line quality control during production of dielectric sheets. An aperture coupled microstrip antenna has been designed and fabricated with fr = 8.4 GHz. A simple jig has been constructed to hold the antenna and connecting cable. It provides an easy means for changing the MUT and brings different areas under the patch. Measurements validate the design and simulation results.},
 bibtype = {inproceedings},
 author = {Mathur, Dhirendra and Bhatnagar, S. K. and Sahula, Vineet},
 doi = {10.1109/TENCON.2011.6129282},
 booktitle = {TENCON 2011 - 2011 IEEE Region 10 Conference}
}

In many applications including RF, Microwave dielectric constant (εr) of the material is a key design parameter. Present methods for measurement of εr are time-consuming and require a sample piece of the material on which some processing has to be done (destructive methods). This paper presents a nondestructive and simple method for determining εr of sheet dielectric materials. The method is nondestructive in the sense that cutting of the material or any processing on it is not required. In this method resonant frequency (fr) of a pre-fabricated antenna is first measured with a known material and then again measured with the Material Under Test (MUT) as dielectric part of the microstrip antenna. The parameter εr is then determined from the ratio of these resonant frequencies and the thickness of MUT. The experimentation is arranged so that errors due to measurement in patch dimensions and electrical connections to the feed line are eliminated. The method can be used for on-line quality control during production of dielectric sheets. An aperture coupled microstrip antenna has been designed and fabricated with fr = 8.4 GHz. A simple jig has been constructed to hold the antenna and connecting cable. It provides an easy means for changing the MUT and brings different areas under the patch. Measurements validate the design and simulation results.

@inproceedings{
 title = {Facial Expression Recognition in Image Sequences Using Active Shape Model and SVM},
 type = {inproceedings},
 year = {2011},
 keywords = {Adaptation models,Candide wire frame model,Computational modeling,Face,Image sequences,SVM,Support vector machines,Vectors,Wires,active appearance algorithm,active appearance model,active shape model,candide wire frame model,computational geometry,face recognition,facial expression intensity,facial expression recognition,geometrical displacement,image sequences,support vector machine,support vector machines,svm,video frames,video signal processing},
 pages = {168-173},
 volume = {0},
 websites = {http://ieeexplore.ieee.org/lpdocs/epic03/wrapper.htm?arnumber=6131234},
 month = {11},
 publisher = {IEEE},
 id = {6715abe8-8efe-3580-9ecf-6716d2c92be3},
 created = {2016-04-21T16:39:32.000Z},
 accessed = {2015-12-15},
 file_attached = {true},
 profile_id = {03d2ca17-6bde-3cfe-95de-fcbe4f21507b},
 last_modified = {2017-03-14T01:22:09.162Z},
 read = {false},
 starred = {false},
 authored = {true},
 confirmed = {true},
 hidden = {false},
 citation_key = {Patil2011b},
 short_title = {Computer Modeling and Simulation (EMS), 2011 Fifth},
 private_publication = {false},
 abstract = {This paper introduces a method for automatic facial expression recognition in image sequences, which make use of Candide wire frame model and active appearance algorithm for tracking, and support vector machine for classification. Candide wire frame model is adapted properly on the first frame of face image sequence. Facial features in subsequent frames of image sequence are tracked using active appearance algorithm. The algorithm adapts Candide wire frame model to the face in each of the frames and tracks the grid in consecutive video frames over time. Last frame of image sequence corresponds to greatest facial expression intensity. The geometrical displacement of Candide wire frame nodes, defined as the difference of the node coordinates between the first and the greatest facial expression intensity frame, is used as an input to the support vector machine, which classifies facial expression into one of the class such as happy, surprise, sad, anger, disgust and fear.},
 bibtype = {inproceedings},
 author = {Patil, Rajesh A. and Sahula, Vineet and Mandal, A.S. S},
 doi = {10.1109/EMS.2011.25},
 booktitle = {2011 UKSim 5th European Symposium on Computer Modeling and Simulation}
}

This paper introduces a method for automatic facial expression recognition in image sequences, which make use of Candide wire frame model and active appearance algorithm for tracking, and support vector machine for classification. Candide wire frame model is adapted properly on the first frame of face image sequence. Facial features in subsequent frames of image sequence are tracked using active appearance algorithm. The algorithm adapts Candide wire frame model to the face in each of the frames and tracks the grid in consecutive video frames over time. Last frame of image sequence corresponds to greatest facial expression intensity. The geometrical displacement of Candide wire frame nodes, defined as the difference of the node coordinates between the first and the greatest facial expression intensity frame, is used as an input to the support vector machine, which classifies facial expression into one of the class such as happy, surprise, sad, anger, disgust and fear.

@inproceedings{
 title = {Bayesian versus support vector machine based approaches for facial feature classification in image sequences},
 type = {inproceedings},
 year = {2011},
 keywords = {Adaptation models,Bayes methods,Bayesian classifier,Candide wire frame model,Computational modeling,Face,Feature recognition,Image sequences,SVM,Support vector machines,Training,Vectors,active appearance algorithm,automatic facial expression recognition,face recognition,facial expression intensity frame,facial feature classification,feature tracking,geometrical displacement,image classification,image sequences,support vector machine,support vector machines},
 pages = {174-179},
 websites = {http://ieeexplore.ieee.org/lpdocs/epic03/wrapper.htm?arnumber=6075168},
 month = {9},
 publisher = {Ieee},
 institution = {NIT Jaipur},
 id = {da468e43-df8b-3cc1-82f4-2f76ab3fd17f},
 created = {2016-04-21T16:39:32.000Z},
 accessed = {2015-12-15},
 file_attached = {true},
 profile_id = {03d2ca17-6bde-3cfe-95de-fcbe4f21507b},
 last_modified = {2017-03-14T01:22:09.162Z},
 read = {false},
 starred = {false},
 authored = {true},
 confirmed = {true},
 hidden = {false},
 citation_key = {Patil2011c},
 short_title = {Computer and Communication Technology (ICCCT), 201},
 private_publication = {false},
 abstract = {A method for automatic facial expression recognition in image sequences, is introduced which make use of Candide wire frame model and active appearance algorithm for tracking, and Bayesian classifier for classification. On the first frame of face image sequence, Candide wire frame model is adapted properly. In subsequent frames of image sequence, facial features are tracked using active appearance algorithm. The algorithm adapts Candide wire frame model to the face in each of the frames and tracks the grid in consecutive video frames over time. Last frame of image sequence corresponds to greatest facial expression intensity. The difference of the node coordinates between the first and the greatest facial expression intensity frame, called the geometrical displacement of Candide wire frame nodes is used as an input to a classifier, which classifies facial expression into one of the class such as happy, surprise, sad, anger, disgust and fear. The experimental results show that the proposed method is better in classification correctness in comparison with binary SVM tree classifier.},
 bibtype = {inproceedings},
 author = {Patil, Rajesh A. and Sahula, Vineet and Mandal, A. S.},
 doi = {10.1109/ICCCT.2011.6075168},
 booktitle = {2011 2nd International Conference on Computer and Communication Technology (ICCCT-2011)}
}

A method for automatic facial expression recognition in image sequences, is introduced which make use of Candide wire frame model and active appearance algorithm for tracking, and Bayesian classifier for classification. On the first frame of face image sequence, Candide wire frame model is adapted properly. In subsequent frames of image sequence, facial features are tracked using active appearance algorithm. The algorithm adapts Candide wire frame model to the face in each of the frames and tracks the grid in consecutive video frames over time. Last frame of image sequence corresponds to greatest facial expression intensity. The difference of the node coordinates between the first and the greatest facial expression intensity frame, called the geometrical displacement of Candide wire frame nodes is used as an input to a classifier, which classifies facial expression into one of the class such as happy, surprise, sad, anger, disgust and fear. The experimental results show that the proposed method is better in classification correctness in comparison with binary SVM tree classifier.

@inproceedings{
 title = {Automatic detection of facial feature points in image sequences},
 type = {inproceedings},
 year = {2011},
 keywords = {Bismuth,Cohn-Kanade database,Computational modeling,Databases,Face recognition,Feature detection,Image recognition,Normalization,Threshold,automatic facial feature point detection,binary image,eye region horizontal histograms,eyeball detection,face location,face recognition,facial image interpretation,feature extraction,image normalization,image sequence,image sequences,iris recognition,thresholding techniques},
 pages = {1-5},
 websites = {http://ieeexplore.ieee.org/lpdocs/epic03/wrapper.htm?arnumber=6108957},
 month = {11},
 publisher = {IEEE},
 id = {3361e4ae-6765-3a19-b7e7-ec0d6b444e6f},
 created = {2016-04-21T16:39:32.000Z},
 accessed = {2015-12-15},
 file_attached = {true},
 profile_id = {03d2ca17-6bde-3cfe-95de-fcbe4f21507b},
 last_modified = {2017-03-14T01:22:09.162Z},
 read = {false},
 starred = {false},
 authored = {true},
 confirmed = {true},
 hidden = {false},
 citation_key = {6108957},
 source_type = {inproceedings},
 short_title = {Image Information Processing (ICIIP), 2011 Interna},
 private_publication = {false},
 abstract = {Detection and location of the face as well as extraction of facial features from images is an important stage for numerous facial image interpretation tasks. Detection of facial feature points, such as corners of eyes, lip corners, nostrils from the images are crucial. In this paper a method for autormatic facial feature point detection in image sequences, is introduced. The method uses image normalization, and thresholding techniques to detect 14 facial feature points. Algorithm proposed by Wolf Kienzle is used for face recognition. The detected face region is then divided into 5 relevant regions of interest, each of which is examined separately, further to detect the location of the facial feature points. In each region image is normalized with respect to brightness. Suitable threshold is set for each region, using which image is converted into binary image. Then in each region extreme ends of binary image will locate the facial feature points. In the eye region horizontal and vertical histograms are analyzed to detect eyeballs. This method when tested on Cohn-Kanade database results in recognition rate of 86%. Moreover, when tested on Informatics and Mathematical Modeling (IMM) face database which consists of tilted faces around y axis, we achieved average recognition rate of 83%.},
 bibtype = {inproceedings},
 author = {Patil, Rajesh A and Sahula, Vineet and Mandal, A. S.},
 doi = {10.1109/ICIIP.2011.6108957},
 booktitle = {2011 IEEE International Conference on Image Information Processing (ICIIP),}
}

Detection and location of the face as well as extraction of facial features from images is an important stage for numerous facial image interpretation tasks. Detection of facial feature points, such as corners of eyes, lip corners, nostrils from the images are crucial. In this paper a method for autormatic facial feature point detection in image sequences, is introduced. The method uses image normalization, and thresholding techniques to detect 14 facial feature points. Algorithm proposed by Wolf Kienzle is used for face recognition. The detected face region is then divided into 5 relevant regions of interest, each of which is examined separately, further to detect the location of the facial feature points. In each region image is normalized with respect to brightness. Suitable threshold is set for each region, using which image is converted into binary image. Then in each region extreme ends of binary image will locate the facial feature points. In the eye region horizontal and vertical histograms are analyzed to detect eyeballs. This method when tested on Cohn-Kanade database results in recognition rate of 86%. Moreover, when tested on Informatics and Mathematical Modeling (IMM) face database which consists of tilted faces around y axis, we achieved average recognition rate of 83%.

@inproceedings{
 title = {Improved sampling methodology for variability aware sizing of analog circuits},
 type = {inproceedings},
 year = {2011},
 id = {e2a848b5-bd44-3b6c-9666-5e94f783a0d8},
 created = {2017-10-14T03:12:09.791Z},
 file_attached = {false},
 profile_id = {03d2ca17-6bde-3cfe-95de-fcbe4f21507b},
 last_modified = {2018-08-09T15:05:52.435Z},
 read = {false},
 starred = {false},
 authored = {true},
 confirmed = {false},
 hidden = {false},
 citation_key = {LokeshGargD.Boolchandani2011},
 private_publication = {false},
 bibtype = {inproceedings},
 author = {Lokesh Garg, D. Boolchandani, Vineet Sahula},
 booktitle = {National Conference on VLSI Design}
}

@inproceedings{
 title = {Modeling and Reliability Evaluation of logic Circuits at Nanoscale},
 type = {inproceedings},
 year = {2010},
 id = {4636f367-7516-36d1-9c8b-7cf2a2595930},
 created = {2014-04-17T21:17:22.000Z},
 file_attached = {false},
 profile_id = {03d2ca17-6bde-3cfe-95de-fcbe4f21507b},
 last_modified = {2017-03-14T01:22:09.162Z},
 read = {false},
 starred = {false},
 authored = {true},
 confirmed = {true},
 hidden = {false},
 citation_key = {kumawat2010rasdat},
 source_type = {inproceedings},
 private_publication = {false},
 bibtype = {inproceedings},
 author = {Kumawat, R. and Sahula, Vineet (MNIT Jaipur) and Gaur, M S and Laxmi, V},
 booktitle = {1st IEEE International Workshop on Reliability Aware System Design and Test}
}

@article{
 title = {Performance evaluation of Arbitration schemes of bus-based communication architectures based on Interactive Generalized Semi Markov Process Model (IGSMP)},
 type = {article},
 year = {2010},
 volume = {11},
 id = {267f4400-0ac2-3d00-957e-3824266d8095},
 created = {2014-04-17T21:17:22.000Z},
 file_attached = {true},
 profile_id = {03d2ca17-6bde-3cfe-95de-fcbe4f21507b},
 last_modified = {2017-03-14T01:22:09.162Z},
 read = {false},
 starred = {false},
 authored = {true},
 confirmed = {true},
 hidden = {false},
 citation_key = {sahula2010performance},
 source_type = {article},
 private_publication = {false},
 bibtype = {article},
 author = {Sahula, U Deshmukh and V., undefined},
 journal = {International Journal of Simulation- Systems, Science and Technology- IJSSST},
 number = {3}
}

@inproceedings{
 title = {Stochastic Automata Network Based Approach for Performance Evaluation of Network-on-Chip Communication Architecture},
 type = {inproceedings},
 year = {2010},
 keywords = {Automata,Computer architecture,Mathematical model,NoC,Routing,Stochastic automata network,Storage area networks,System-on-a-chip,Topology,Torus topology,butterfly Fat Tree topology,mesh topology,network-on-chip,network-on-chip communication architecture,performance evaluation,reconfigurable architectures,stochastic automata,stochastic automata network},
 pages = {351-356},
 websites = {http://ieeexplore.ieee.org/lpdocs/epic03/wrapper.htm?arnumber=5572800},
 month = {7},
 publisher = {IEEE},
 id = {870a6c49-4fce-35fd-b8b2-1656c5bc4d34},
 created = {2016-04-21T16:39:32.000Z},
 accessed = {2015-12-15},
 file_attached = {true},
 profile_id = {03d2ca17-6bde-3cfe-95de-fcbe4f21507b},
 last_modified = {2017-03-14T01:22:09.162Z},
 read = {false},
 starred = {false},
 authored = {true},
 confirmed = {true},
 hidden = {false},
 citation_key = {Deshmukh2010a},
 short_title = {VLSI (ISVLSI), 2010 IEEE Computer Society Annual S},
 private_publication = {false},
 abstract = {Concurrent communication architectures are essential in order to meet ever increasing demand for higher performance of modern-day System-on-Chip (SoC) applications. The behavior of such communication architectures is usually complex and difficult to model. This paper presents a formal modeling approach based on Stochastic Automata Network (SAN) for efficient performance evaluation of concurrent communication architectures. We use functional and synchronizing transitions of the SAN model to describe interaction among concurrent components of these architectures. We propose model for Network-on-Chip (NoC) architecture, and our modeling approach is able to provide evaluation of performance parameters viz. throughput and rate of accepted traffic for mesh, Torus and butterfly Fat Tree topologies. The proposed modeling approach is not only efficient and accurate but also requires lesser modeling efforts.},
 bibtype = {inproceedings},
 author = {Deshmukh, Ulhas and Sahula, Vineet},
 doi = {10.1109/ISVLSI.2010.97},
 booktitle = {2010 IEEE Computer Society Annual Symposium on VLSI}
}

Concurrent communication architectures are essential in order to meet ever increasing demand for higher performance of modern-day System-on-Chip (SoC) applications. The behavior of such communication architectures is usually complex and difficult to model. This paper presents a formal modeling approach based on Stochastic Automata Network (SAN) for efficient performance evaluation of concurrent communication architectures. We use functional and synchronizing transitions of the SAN model to describe interaction among concurrent components of these architectures. We propose model for Network-on-Chip (NoC) architecture, and our modeling approach is able to provide evaluation of performance parameters viz. throughput and rate of accepted traffic for mesh, Torus and butterfly Fat Tree topologies. The proposed modeling approach is not only efficient and accurate but also requires lesser modeling efforts.

@inproceedings{
 title = {Variability aware yield optimal sizing of analog circuits using SVM-genetic approach},
 type = {inproceedings},
 year = {2010},
 keywords = {Analog circuits,Design centering,Integrated circuit modeling,Kernel,Macromodels,Operational amplifiers,Process variability analysis,Regression,SVM-genetic approach,Support Vector Machine,Support vector machine,Support vector machines,Transistors,Voltage-controlled oscillators,Yield,analog circuits,analogue circuits,circuit simulation,design space exploration,power aware c,power aware computing,process variability analysis,support vector machine,support vector machines,variability aware yield optimal sizing},
 pages = {1-6},
 websites = {http://ieeexplore.ieee.org/lpdocs/epic03/wrapper.htm?arnumber=5672332},
 month = {10},
 publisher = {IEEE},
 id = {cdfce351-5556-371a-b683-ef479893165e},
 created = {2016-05-10T02:54:44.000Z},
 accessed = {2015-12-15},
 file_attached = {true},
 profile_id = {03d2ca17-6bde-3cfe-95de-fcbe4f21507b},
 last_modified = {2017-03-14T01:22:09.162Z},
 read = {false},
 starred = {false},
 authored = {true},
 confirmed = {true},
 hidden = {false},
 citation_key = {Boolchandani2010},
 source_type = {inproceedings},
 short_title = {Symbolic and Numerical Methods, Modeling and Appli},
 private_publication = {false},
 abstract = {During analog circuit synthesis in nanometer technology, process variability analysis is mandatory during design space exploration. This would ensure that the circuit will function as per specifications after fabrication even with impact of statistical variations in nanometer regimes. The methodology necessitates the evaluation of performance metrics of an analog circuit for different sizing instances of the transistors. Circuit simulation for performance evaluation is very time consuming and is seldom a choice while sizing a circuit for a chosen topology. The complexity of sizing methodology increases with the need to consider effects of variations in process and environment parameters. We employ macromodeling approach for analog circuits based on support vector machine (SVM), which enables efficient evaluation of performance of such circuits during sizing and yield optimization loops. The objective to improve evaluation efficiency has been the motivation behind efforts to develop performance macromodels, which should be as accurate as SPICE and at the same time have shorter evaluation time for use in the sizing of analog circuits, where they are used as substitutes for full circuit simulation during circuit sizing (synthesis). Process variability aware SVM macromodels are used in the multiobjective multivariate sizing method which is also yield optimal. Post design centering, the sized circuits will be able to provide functions as per specifications upon fabrication. Its application as process variability analysis tool is illustrated on two stage op amp and a voltage controlled oscillator using 90 nm BSIM4 models of transistors.},
 bibtype = {inproceedings},
 author = {Boolchandani, D. and Garg, Lokesh and Khandelwal, Sapna and Sahula, Vineet},
 doi = {10.1109/SM2ACD.2010.5672332},
 booktitle = {2010 XIth IEEE International Workshop on Symbolic and Numerical Methods, Modeling and Applications to Circuit Design (SM2ACD)}
}

During analog circuit synthesis in nanometer technology, process variability analysis is mandatory during design space exploration. This would ensure that the circuit will function as per specifications after fabrication even with impact of statistical variations in nanometer regimes. The methodology necessitates the evaluation of performance metrics of an analog circuit for different sizing instances of the transistors. Circuit simulation for performance evaluation is very time consuming and is seldom a choice while sizing a circuit for a chosen topology. The complexity of sizing methodology increases with the need to consider effects of variations in process and environment parameters. We employ macromodeling approach for analog circuits based on support vector machine (SVM), which enables efficient evaluation of performance of such circuits during sizing and yield optimization loops. The objective to improve evaluation efficiency has been the motivation behind efforts to develop performance macromodels, which should be as accurate as SPICE and at the same time have shorter evaluation time for use in the sizing of analog circuits, where they are used as substitutes for full circuit simulation during circuit sizing (synthesis). Process variability aware SVM macromodels are used in the multiobjective multivariate sizing method which is also yield optimal. Post design centering, the sized circuits will be able to provide functions as per specifications upon fabrication. Its application as process variability analysis tool is illustrated on two stage op amp and a voltage controlled oscillator using 90 nm BSIM4 models of transistors.

@inproceedings{
 title = {Omnipotent and mortal training of a nanocell model to emulate the functionality of a logic gate},
 type = {inproceedings},
 year = {2010},
 keywords = {Beyond CMOS,Genetic algorithm,Molecular electronics,Mortal,Nanocell,Negative differential resistance,Omnipotent,Programmability,SPICE,genetic algorithms,logic gates,molecular ele},
 pages = {1-6},
 websites = {http://ieeexplore.ieee.org/lpdocs/epic03/wrapper.htm?arnumber=5712699},
 month = {12},
 publisher = {IEEE},
 id = {84c7c87a-8dca-39ab-8cdc-39c68132bac8},
 created = {2016-05-10T02:54:44.000Z},
 accessed = {2015-12-15},
 file_attached = {true},
 profile_id = {03d2ca17-6bde-3cfe-95de-fcbe4f21507b},
 last_modified = {2017-03-14T01:22:09.162Z},
 read = {false},
 starred = {false},
 authored = {true},
 confirmed = {true},
 hidden = {false},
 citation_key = {5712699},
 source_type = {inproceedings},
 short_title = {India Conference (INDICON), 2010 Annual IEEE},
 private_publication = {false},
 abstract = {Various unavoidable constraints (viz. physical, technical and financial) curtail the possibility of achieving continuous improvement in the computing capabilities through scaling down of devices using the conventional silicon technology. Molecular electronics aims to use the bottom-up approach to build nanoscale devices from basic molecular unit and promises unforeseen levels of computing per dollar-watt-cm2. The programmability feature of molecules is exploited to circumvent the problem of addressability. The nanocell concept is predicated on the belief that a random distribution of self-assembled molecules can be programmed to perform a specific logic function. In this paper we present a novel approach to demonstrate plausibility of the idea of “creating functionality from disorder”. The experimental results vindicate the plausibility of training a nanocell to perform a logic operation. A negative differential resistance (NDR) circuit has been designed to emulate the Λ-type I-V characteristics of the molecular switches connected between any pair of nodes in the actual nanocell. A nanocell model is then constructed taking instances of this NDR circuit. As a primary exploration of the nanocell concept the omnipotent programming was considered. The results from HSPICE simulations are then fed to the genetic algorithm(GA) solver in MATLAB to provide us with the optimized configuration(or a combination of switch states) of the NDR circuits for which the nanocell model yields the functionality of one or multiple target logic devices. Finally mortal programming is also accomplished. The GA solver is used again to provide us with the voltages which ought to be applied on each of the exterior nodes (apart from the input and output nodes) of the nanocell to yield a response resembling a NAND gate.},
 bibtype = {inproceedings},
 author = {Jha, Pankaj Kumar and Sahula, Vineet},
 doi = {10.1109/INDCON.2010.5712699},
 booktitle = {2010 Annual IEEE India Conference (INDICON)}
}

Various unavoidable constraints (viz. physical, technical and financial) curtail the possibility of achieving continuous improvement in the computing capabilities through scaling down of devices using the conventional silicon technology. Molecular electronics aims to use the bottom-up approach to build nanoscale devices from basic molecular unit and promises unforeseen levels of computing per dollar-watt-cm2. The programmability feature of molecules is exploited to circumvent the problem of addressability. The nanocell concept is predicated on the belief that a random distribution of self-assembled molecules can be programmed to perform a specific logic function. In this paper we present a novel approach to demonstrate plausibility of the idea of “creating functionality from disorder”. The experimental results vindicate the plausibility of training a nanocell to perform a logic operation. A negative differential resistance (NDR) circuit has been designed to emulate the Λ-type I-V characteristics of the molecular switches connected between any pair of nodes in the actual nanocell. A nanocell model is then constructed taking instances of this NDR circuit. As a primary exploration of the nanocell concept the omnipotent programming was considered. The results from HSPICE simulations are then fed to the genetic algorithm(GA) solver in MATLAB to provide us with the optimized configuration(or a combination of switch states) of the NDR circuits for which the nanocell model yields the functionality of one or multiple target logic devices. Finally mortal programming is also accomplished. The GA solver is used again to provide us with the voltages which ought to be applied on each of the exterior nodes (apart from the input and output nodes) of the nanocell to yield a response resembling a NAND gate.

@inproceedings{
 title = {Automatic recognition of facial expressions in image sequences: A review},
 type = {inproceedings},
 year = {2010},
 keywords = {Face,Face recognition,Facial features,Feature extraction,Glass,Humans,Image sequences,automatic recognition,computer vision,data driven animation,expression. classification,face detection,face recognition,facial expression information,facial expression recognition,human computer interaction,image sequences},
 pages = {408-413},
 websites = {http://ieeexplore.ieee.org/lpdocs/epic03/wrapper.htm?arnumber=5578670},
 month = {7},
 publisher = {IEEE},
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 abstract = {For human beings, facial expression is one of the most powerful and natural way to communicate their emotions and intensions. A human being can detect facial expressions without effort, but for a machine it is very difficult. Automatic facial expression recognition is an interesting and challenging problem. Automatic facial expression recognition systems can be mainly used for human computer interaction and data driven animation. There are three sub problems while designing automatic facial expression recognition system, face detection, extraction of the facial expression information, and classification of the expression. A system that performs these operations more accurately and in real time would be crucial to achieve a human-like interaction between man and machine. This paper reviews the past work done in solving these problems for image sequences.},
 bibtype = {inproceedings},
 author = {Patil, R.A. A and Sahula, Vineet and Mandal, A.S. S.},
 doi = {10.1109/ICIINFS.2010.5578670},
 booktitle = {2010 5th International Conference on Industrial and Information Systems (ICIIS)}
}

For human beings, facial expression is one of the most powerful and natural way to communicate their emotions and intensions. A human being can detect facial expressions without effort, but for a machine it is very difficult. Automatic facial expression recognition is an interesting and challenging problem. Automatic facial expression recognition systems can be mainly used for human computer interaction and data driven animation. There are three sub problems while designing automatic facial expression recognition system, face detection, extraction of the facial expression information, and classification of the expression. A system that performs these operations more accurately and in real time would be crucial to achieve a human-like interaction between man and machine. This paper reviews the past work done in solving these problems for image sequences.

@article{
 title = {Exploring Arbitration Schemes Of Soc Bus Architectures Using Interacting Generalized Semi Markov Process Model.},
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@article{
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 journal = {Journal of Design, Analysis and Tools for Integrated Circuits and Systems (JDATICS)}
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@inproceedings{
 title = {LTCC: 3D Integration Multilayer Technology for Emerging Wireless Communication Micro-System Architectures},
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@inproceedings{
 title = {Evaluating generalized semi Markov process model of SoC bus architectures using HCFG},
 type = {inproceedings},
 year = {2009},
 keywords = {Markov processes,performance evaluation,system bus},
 pages = {1-6},
 websites = {http://ieeexplore.ieee.org/lpdocs/epic03/wrapper.htm?arnumber=5395938},
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 abstract = {This paper presents an efficient approach based on Hierarchical Concurrent Flow Graph (HCFG) for performance evaluation of single shared bus architecture and hierarchical bus bridge architecture. The formulation is based on generalized semi Markov process model of these architectures. In particular, we focus on building model for a single shared bus architecture and extend the approach to model architecture consisting of hierarchical buses connected through bus bridge. Our modeling approach provides early estimation of performance parameters viz. memory bandwidth, processor utilization, average queue length and average waiting time. We validate the proposed modeling and evaluation approach by comparing the results of evaluation against those that are obtained by SystemC simulation of the same communication architectures under consideration. The HCFG approach is not only time efficient but also provides much detailed evaluation of stochastic properties of performance parameters as compared to SystemC simulation. To illustrate the efficacy of the approach, we compare the results with the results available in the literature for some more examples.},
 bibtype = {inproceedings},
 author = {Deshmukh, Ulhas and Sahula, Vineet},
 doi = {10.1109/TENCON.2009.5395938},
 booktitle = {IEEE Region 10 Annual International Conference, Proceedings/TENCON}
}

This paper presents an efficient approach based on Hierarchical Concurrent Flow Graph (HCFG) for performance evaluation of single shared bus architecture and hierarchical bus bridge architecture. The formulation is based on generalized semi Markov process model of these architectures. In particular, we focus on building model for a single shared bus architecture and extend the approach to model architecture consisting of hierarchical buses connected through bus bridge. Our modeling approach provides early estimation of performance parameters viz. memory bandwidth, processor utilization, average queue length and average waiting time. We validate the proposed modeling and evaluation approach by comparing the results of evaluation against those that are obtained by SystemC simulation of the same communication architectures under consideration. The HCFG approach is not only time efficient but also provides much detailed evaluation of stochastic properties of performance parameters as compared to SystemC simulation. To illustrate the efficacy of the approach, we compare the results with the results available in the literature for some more examples.

@inproceedings{
 title = {Multi-objective genetic approach for analog circuit sizing using SVM macro-model},
 type = {inproceedings},
 year = {2009},
 keywords = {Analog circuits,Circuit simulation,Circuit synthesis,Computational modeling,Genetics,HSPICE,MATLAB,Operational amplifiers,Parameter estimation,SPICE,SVM macromodel,Support vector machine classification,Support vector machines,analog circuit sizing,analogue circuits,automated synthesis,combinatorial mathematics,combinatorial optimization algorithms,least square SVM toolbox,least squares approximations,mathematics computing,multiobjective genetic approach,optimisation,support vector machine,support vector machines},
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 abstract = {Analog circuit sizing is the task to determine the sizes of all components in the circuit during automated synthesis. Randomized combinatorial optimization algorithms are desired for quicker determination of a set of optimal sizes of the components. These algorithms require set of multiple performance parameters, for a very large number of sized circuits. Therefore the reduction in time required to estimate these performance parameters is also highly desired. For the purpose of estimation of performance parameters, we employ Support Vector Machine (SVM) based macro-models of analog circuits, instead of using SPICE simulation. These SVM macro-models are not only faster to evaluate, but use of efficient kernel functions has also made them almost as accurate as SPICE. In this paper, we report multi-objective genetic algorithm for simultaneous optimization of multiple performance parameters. We compute the Pareto optimal points for various performance parameters of a two-stage op-amp circuit in 180 nm technology. We perform SVM classification and regression using Least Square SVM toolbox with MATLAB. HSPICE was used to generate data-set from simulation of two-stage op-amp, which was used to train the SVM macro-model. The results pertaining to total time consumed in sizing task are very encouraging. We observed 'time taken' in one evaluation by SVM macromodel as compared to HSPICE is upto two order smaller, resulting in speed-up of approximately 20.},
 bibtype = {inproceedings},
 author = {Boolchandani, D. and Kumar, Anupam and Sahula, Vineet},
 doi = {10.1109/TENCON.2009.5395927},
 booktitle = {IEEE Region 10 Annual International Conference, Proceedings/TENCON}
}

Analog circuit sizing is the task to determine the sizes of all components in the circuit during automated synthesis. Randomized combinatorial optimization algorithms are desired for quicker determination of a set of optimal sizes of the components. These algorithms require set of multiple performance parameters, for a very large number of sized circuits. Therefore the reduction in time required to estimate these performance parameters is also highly desired. For the purpose of estimation of performance parameters, we employ Support Vector Machine (SVM) based macro-models of analog circuits, instead of using SPICE simulation. These SVM macro-models are not only faster to evaluate, but use of efficient kernel functions has also made them almost as accurate as SPICE. In this paper, we report multi-objective genetic algorithm for simultaneous optimization of multiple performance parameters. We compute the Pareto optimal points for various performance parameters of a two-stage op-amp circuit in 180 nm technology. We perform SVM classification and regression using Least Square SVM toolbox with MATLAB. HSPICE was used to generate data-set from simulation of two-stage op-amp, which was used to train the SVM macro-model. The results pertaining to total time consumed in sizing task are very encouraging. We observed 'time taken' in one evaluation by SVM macromodel as compared to HSPICE is upto two order smaller, resulting in speed-up of approximately 20.

@inproceedings{
 title = {Improved support vector machine regression for analog circuits macromodeling using efficient kernel functions},
 type = {inproceedings},
 year = {2008},
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 author = {Boolchandani, D and Ahmed, A and Sahula, V},
 booktitle = {Proceedings of IEEE international workshop on symbolic and numerical methods, modeling and applications to circuit design}
}

@inproceedings{
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 booktitle = {IE National Seminar on Advanced Electronic Systems- Modeling & Simulation (Verification)}
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@inproceedings{
 title = {HCFG Approach for performance evaluation of SoC communication architecture},
 type = {inproceedings},
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 booktitle = {12th IEEE VLSI Design and Test Symposium}
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@inproceedings{
 title = {System Level Design & Verification: A Case Study of MPEG-2 Video Decoder},
 type = {inproceedings},
 year = {2008},
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@inproceedings{
 title = {Technologies for Microsystems beyond System-on-Chip},
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@inproceedings{
 title = {Interactive generalized semi Markov process model for evaluating arbitration schemes of SoC bus architectures},
 type = {inproceedings},
 year = {2008},
 keywords = {Computer architecture,Hardware,High performance computing,Interacting generalized semi Markov process model,Markov processes,Mathematical model,Network-on-a-chip,Performance analysis,Performance estimation,Round robin,SoC bus architectures,Stateflow components,System level modeling,System-on-Chip communication,System-on-a-chip,Telecommunication computing,arbitration schemes,bus-based communication architecture,formal technique,interactive generalized semiMarkov process model,system level performance analysis,system-on-chip},
 pages = {578-583},
 websites = {http://ieeexplore.ieee.org/lpdocs/epic03/wrapper.htm?arnumber=4625337},
 month = {9},
 publisher = {Ieee},
 id = {b98770b7-50c4-317a-bd6d-78d5299c232d},
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 abstract = {Ever increasing component counts of a system-on-chip makes communication among components complex and diverse. Thus communication architecture becomes a major performance determining candidate. This paper proposes a formal technique for system level performance analysis that can help the designer to select the appropriate arbitration scheme for a chosen bus-based communication architecture. For a bus with arbitration, we formulate a model based on interacting generalized semi Markov process. We mainly focus on building model for single shared bus architecture and explore arbitration along with different priority schemes viz. (i) fixed, (ii) lottery based and (iii) round robin. We describe the model of bus architecture using these arbitration schemes in the stateflow component of MATLAB. Our modeling approach provides an evaluation and comparison of performance parameters viz. memory bandwidth, processing element utilization, average queue length at the memory and average waiting time seen by a processing element, for a chosen arbitration scheme.},
 bibtype = {inproceedings},
 author = {Deshmukh, Ulhas and Sahula, Vineet},
 doi = {10.1109/EMS.2008.77},
 booktitle = {Proceedings - EMS 2008, European Modelling Symposium, 2nd UKSim European Symposium on Computer Modelling and Simulation}
}

Ever increasing component counts of a system-on-chip makes communication among components complex and diverse. Thus communication architecture becomes a major performance determining candidate. This paper proposes a formal technique for system level performance analysis that can help the designer to select the appropriate arbitration scheme for a chosen bus-based communication architecture. For a bus with arbitration, we formulate a model based on interacting generalized semi Markov process. We mainly focus on building model for single shared bus architecture and explore arbitration along with different priority schemes viz. (i) fixed, (ii) lottery based and (iii) round robin. We describe the model of bus architecture using these arbitration schemes in the stateflow component of MATLAB. Our modeling approach provides an evaluation and comparison of performance parameters viz. memory bandwidth, processing element utilization, average queue length at the memory and average waiting time seen by a processing element, for a chosen arbitration scheme.

@inproceedings{
 title = {Analytical performance estimation from GSMP model for hierarchical bus-bridge based SoC communication architecture},
 type = {inproceedings},
 year = {2008},
 keywords = {Bandwidth,Bridges,Computer architecture,GSMP model,Manufacturing,Markov processes,Microelectronics,Monte Carlo methods,Monte Carlo simulation,Network-on-a-chip,Parameter estimation,Performance analysis,SoC communication architecture,System-on-a-chip,computer architecture,concurrent communication techniques,generalized semi Markov process model,hierarchical bus bridge communication architecture,hierarchical bus-bridge,integrated circuit design,memory bandwidth,performance estimation,performance parameters,processing element,queue length,queueing theory,system-on-chip,system-on-chip communication},
 pages = {155-158},
 websites = {http://ieeexplore.ieee.org/lpdocs/epic03/wrapper.htm?arnumber=5393540},
 month = {12},
 publisher = {IEEE},
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 abstract = {The modern-day system-on-chip communication posses complex characteristics- (a) the communication times of individual transactions are difficult to predict, (b) concurrent communication techniques are employed to meet the performance of emerging applications, and (c) communication is hierarchical. Thus, performance of communication architecture plays major role in determining the performance of the system. An early and efficient performance estimation of communication architecture is essential in order to select appropriate communication architecture from the possible choices, within design time deadlines. In this paper, we propose an analytical technique for performance estimation of hierarchical bus bridge communication architecture, based on generalized semi Markov process (GSMP) model. Our modeling approach provides an early estimation of performance parameters viz. memory bandwidth, average queue length at memory and average waiting time seen by a processing element. The input parameters to the model are number of processing elements, the mean computation time of processing elements, and the first and second moments of communication time of processing elements. We validate efficacy of modeling approach by comparing the results against those obtained by Monte Carlo simulation for the underlying model.},
 bibtype = {inproceedings},
 author = {Deshmukh, Ulhas and Sahula, Vineet},
 doi = {10.1109/ICM.2008.5393540},
 booktitle = {Proceedings of the International Conference on Microelectronics, ICM}
}

The modern-day system-on-chip communication posses complex characteristics- (a) the communication times of individual transactions are difficult to predict, (b) concurrent communication techniques are employed to meet the performance of emerging applications, and (c) communication is hierarchical. Thus, performance of communication architecture plays major role in determining the performance of the system. An early and efficient performance estimation of communication architecture is essential in order to select appropriate communication architecture from the possible choices, within design time deadlines. In this paper, we propose an analytical technique for performance estimation of hierarchical bus bridge communication architecture, based on generalized semi Markov process (GSMP) model. Our modeling approach provides an early estimation of performance parameters viz. memory bandwidth, average queue length at memory and average waiting time seen by a processing element. The input parameters to the model are number of processing elements, the mean computation time of processing elements, and the first and second moments of communication time of processing elements. We validate efficacy of modeling approach by comparing the results against those obtained by Monte Carlo simulation for the underlying model.

@inproceedings{
 title = {Stochastic Automata Network for Performance Evaluation of Heterogeneous SoC Communication},
 type = {inproceedings},
 year = {2008},
 keywords = {Automata,Computer architecture,Costs,GSMP model,Markov processes,Parameter estimation,Stochastic processes,Storage area networks,System performance,System-on-a-chip,Time to market,bus based communication architecture,generalized semi Markov process,heterogeneous SoC communication,memory bandwidth,modular SAN,parameter estimation,performance evaluation,processing element,queue length,queueing theory,stochastic automata,stochastic automata network,system buses,system-on-chip},
 pages = {208-211},
 websites = {http://ieeexplore.ieee.org/lpdocs/epic03/wrapper.htm?arnumber=4738313},
 month = {11},
 publisher = {IEEE},
 id = {5b330306-e38d-375f-9cf1-ab047b3229dc},
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 citation_key = {Deshmukh2008c},
 short_title = {NORCHIP, 2008.},
 private_publication = {false},
 abstract = {To meet ever increasing demand for performance of emerging System-on-Chip (SoC) applications, designer employ techniques for concurrent communication between components. Hence communication architecture becomes complex and major performance bottleneck. An early performance evaluation of communication architecture is the key to reduce design time, time-to-market and consequently cost of the system. Moreover, it helps to optimize system performance by selecting appropriate communication architecture. However, performance model of concurrent communication is complex to describe and hard to solve. In this paper, we propose methodology for performance evaluation of bus based communication architectures, modeling for which is based on modular Stochastic Automata Network (SAN). We employ Generalized Semi Markov Process (GSMP) model for each module of the SAN that emulates dynamic behavior of a Processing Element (PE) of an SoC architecture. The proposed modeling approach provides an early estimation of performance parameters viz. memory bandwidth, average queue length at memory and average waiting time seen by a processing element; while we provide parameters viz. number of processing elements, the mean computation time of processing elements and the first and second moments of connection time between processing elements and memories, as input to the model.},
 bibtype = {inproceedings},
 author = {Deshmukh, Ulhas and Sahula, Vineet},
 doi = {10.1109/NORCHP.2008.4738313},
 booktitle = {Norchip - 26th Norchip Conference, Formal Proceedings}
}

To meet ever increasing demand for performance of emerging System-on-Chip (SoC) applications, designer employ techniques for concurrent communication between components. Hence communication architecture becomes complex and major performance bottleneck. An early performance evaluation of communication architecture is the key to reduce design time, time-to-market and consequently cost of the system. Moreover, it helps to optimize system performance by selecting appropriate communication architecture. However, performance model of concurrent communication is complex to describe and hard to solve. In this paper, we propose methodology for performance evaluation of bus based communication architectures, modeling for which is based on modular Stochastic Automata Network (SAN). We employ Generalized Semi Markov Process (GSMP) model for each module of the SAN that emulates dynamic behavior of a Processing Element (PE) of an SoC architecture. The proposed modeling approach provides an early estimation of performance parameters viz. memory bandwidth, average queue length at memory and average waiting time seen by a processing element; while we provide parameters viz. number of processing elements, the mean computation time of processing elements and the first and second moments of connection time between processing elements and memories, as input to the model.

@inproceedings{
 title = {Stochastic Modeling approach for SoC Communication},
 type = {inproceedings},
 year = {2007},
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@inproceedings{
 title = {Improvement of ASIC design processes},
 type = {inproceedings},
 year = {2002},
 keywords = {AND concurrency,ASIC design processes,Application specific integrated circuits,Asia,Concurrent computing,Educational institutions,Flow graphs,Instruments,Meeting planning,OR concurrency,Power system modeling,Process design,Project management,application specific integrated circuits,circuit CAD,circuit layout CAD,design flow,flow graphs,hierarchical concurrent flow graph model,high level synthesis,incremental changes,integrated circuit design,project execution time,textual description},
 pages = {105-110},
 websites = {http://ieeexplore.ieee.org/lpdocs/epic03/wrapper.htm?arnumber=994893},
 publisher = {IEEE Comput. Soc},
 id = {2396f592-b65b-3d06-a688-63110100c1f8},
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 abstract = {With device counts on modem-day ASICs crossing the 10 million mark, careful planning of an ASIC design project is necessary to meet time deadlines. Two problems arise in this context. The first is the estimation of man-months for a project, with the knowledge of the ASIC design flow that will be followed for project execution. The second problem is that of making incremental changes to the design flow in order to reduce the time to complete a project. We consider these two problems in a theoretical framework. Starting from a textual description of the design flow, a model known as the hierarchical concurrent flow graph (HCFG) model is constructed to capture the concurrency in the execution of an ASIC design flow and the inherent hierarchy in such a flow. The HCFG model allows us to (a) quickly estimate the project execution time and (b) analyze the effect of introducing AND and OR concurrency in the flow to improve the execution time. We illustrate the use of the powerful estimation technique through two examples. The first example shows the use of AND concurrency in a back-end flow and the second example shows the use of OR concurrency in a software design flow},
 bibtype = {inproceedings},
 author = {Sahula, V. and Ravikumar, C. P. and Nagchoudhuri, D.},
 doi = {10.1109/ASPDAC.2002.994893},
 booktitle = {Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design}
}

With device counts on modem-day ASICs crossing the 10 million mark, careful planning of an ASIC design project is necessary to meet time deadlines. Two problems arise in this context. The first is the estimation of man-months for a project, with the knowledge of the ASIC design flow that will be followed for project execution. The second problem is that of making incremental changes to the design flow in order to reduce the time to complete a project. We consider these two problems in a theoretical framework. Starting from a textual description of the design flow, a model known as the hierarchical concurrent flow graph (HCFG) model is constructed to capture the concurrency in the execution of an ASIC design flow and the inherent hierarchy in such a flow. The HCFG model allows us to (a) quickly estimate the project execution time and (b) analyze the effect of introducing AND and OR concurrency in the flow to improve the execution time. We illustrate the use of the powerful estimation technique through two examples. The first example shows the use of AND concurrency in a back-end flow and the second example shows the use of OR concurrency in a software design flow

@inproceedings{
 title = {Design methodologies for Design of Wireless Mobile Transceivers: A tutorial},
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@inproceedings{
 title = {The hierarchical concurrent flow graph approach for modeling and analysis of design processes},
 type = {inproceedings},
 year = {2001},
 keywords = {Chip scale packaging,Concurrent computing,Design engineering,Educational institutions,Flow graphs,Process design,Project management,Stochastic processes,Time to market,VLSI,Very large scale integration,chip design process,concurrent engineering,design flow management strategy,design processes,execution times,flow graphs,graph transmittance,hierarchical concurrent flow graph approach,integrated circuit design,project management,stochastic variation,task execution times,time-to-market,vlsi,what-if analysis},
 pages = {91-96},
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 notes = {<b>From Duplicate 2 (<i>The hierarchical concurrent flow graph approach for modeling and analysis of design processes</i> - Sahula, V.; Ravikumar, C.P. P)<br/></b><br/><b>From Duplicate 2 ( </b><br/><br/><br/><br/><br/><br/><br/><b><br/><br/><br/><br/><br/><br/><br/></b><br/><br/><br/><b><br/><br/><br/></b><br/><b><br/><i>The hierarchical concurrent flow graph approach for modeling and analysis of design processes</i><br/></b><br/><b><br/><br/><br/></b><br/><br/><br/><b><br/><br/><br/><br/><br/><br/><br/></b><br/><br/><br/><br/><br/><br/><br/><b>- Sahula, V.; Ravikumar, C.P. P )<br/><br/><br/><br/><br/><br/><br/><br/></b><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/><b>From Duplicate 1 ( </b><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/><b><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/></b><br/><br/><br/><br/><br/><br/><br/><b><br/><br/><br/><br/><br/><br/><br/></b><br/><br/><br/><b><br/><br/><br/></b><br/><b><br/><i>The hierarchical concurrent flow graph approach for modeling andanalysis of design processes</i><br/></b><br/><b><br/><br/><br/></b><br/><br/><br/><b><br/><br/><br/><br/><br/><br/><br/></b><br/><br/><br/><br/><br/><br/><br/><b><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/></b><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/><b>- Sahula, V.; Ravikumar, C.P. )<br/>And Duplicate 3 ( </b><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/><b><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/></b><br/><br/><br/><br/><br/><br/><br/><b><br/><br/><br/><br/><br/><br/><br/></b><br/><br/><br/><b><br/><br/><br/></b><br/><b><br/><i>The hierarchical concurrent flow graph approach for modeling andanalysis of design processes</i><br/></b><br/><b><br/><br/><br/></b><br/><br/><br/><b><br/><br/><br/><br/><br/><br/><br/></b><br/><br/><br/><br/><br/><br/><br/><b><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/></b><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/><b>- Sahula, V.; Ravikumar, C.P. )<br/><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/></b>},
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 abstract = {In this paper, we expose a new technique for the analysis of\ndesign flows. The modern-day chip design process is a complex one, with\nthe following characteristics: (a) the execution times of individual\ntasks are difficult to predict, since a tool may occasionally produce\nunsatisfactory results, requiring the designer to repeat the task, (b)\nthe increasing pressure on the project management to cut down the\ntime-to-market forces the management to employ concurrent design\ntechniques, and (c) the VLSI design flow is hierarchical, and a\ncompletely flat representation of the design flow is too complex to\nanalyze. Existing techniques for design flow analysis cannot deal with\nthe problems mentioned above. The hierarchical concurrent flow graph\n(HCFG) presented in this paper is an analysis technique which borrows\nthe idea of graph transmittance from circuit theory and extends the\nconcept to include hierarchy, concurrency and stochastic variation in\ntask execution times. We apply the HCFG technique to analyze two\nrealistic design flows. We show that a project manager can carry out a\npre-execution &amp;ldquo;what-if&amp;rdquo; analysis to determine the best\ndesign flow management strategy, that is most likely to lead to the\nlowest execution time},
 bibtype = {inproceedings},
 author = {Sahula, V. and Ravikumar, C.P.},
 doi = {10.1109/ICVD.2001.902645},
 booktitle = {Fourteenth IEEE International Conference on VLSI Design}
}

In this paper, we expose a new technique for the analysis of\ndesign flows. The modern-day chip design process is a complex one, with\nthe following characteristics: (a) the execution times of individual\ntasks are difficult to predict, since a tool may occasionally produce\nunsatisfactory results, requiring the designer to repeat the task, (b)\nthe increasing pressure on the project management to cut down the\ntime-to-market forces the management to employ concurrent design\ntechniques, and (c) the VLSI design flow is hierarchical, and a\ncompletely flat representation of the design flow is too complex to\nanalyze. Existing techniques for design flow analysis cannot deal with\nthe problems mentioned above. The hierarchical concurrent flow graph\n(HCFG) presented in this paper is an analysis technique which borrows\nthe idea of graph transmittance from circuit theory and extends the\nconcept to include hierarchy, concurrency and stochastic variation in\ntask execution times. We apply the HCFG technique to analyze two\nrealistic design flows. We show that a project manager can carry out a\npre-execution &ldquo;what-if&rdquo; analysis to determine the best\ndesign flow management strategy, that is most likely to lead to the\nlowest execution time

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@inproceedings{
 title = {Design planning for single chip implementation of digital wireless mobile transceiver},
 type = {inproceedings},
 year = {2000},
 keywords = {CDMA spread spectrum technique,Consumer electronics,Costs,Design engineering,Design optimization,Educational institutions,Flow graphs,Multiaccess communication,Process design,Time to market,Transceivers,concurrent constructs,concurrent engineering,design completion time,design cost,design planning paradigm,digital radio,digital wireless mobile transceiver,flow graphs,hardware-software codesign,hardware-software design flow,hierarchical concurrent flow graph,integrated circuit design,mobile radio,pre-execution what-if analysis,single chip implementation,total system cost,transceivers},
 pages = {19-23},
 websites = {http://ieeexplore.ieee.org/lpdocs/epic03/wrapper.htm?arnumber=905765},
 publisher = {IEEE},
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 abstract = {In this paper, we present a design planning paradigm for the design of a wireless mobile transceiver. We consider the digital part in a single chip implementation of a transceiver based on the CDMA spread spectrum technique. The complexity of such a chip implementation makes the design process complex and very expensive. The desired characteristics of a mobile transceiver are low cost, small size, and low power. Design cost forms a major portion of total system cost. In order to reduce design cost, design completion time should be reduced. We assume hardware-software design flow for design of the transceiver. We analyze the design flow using the hierarchical concurrent flow graph (HCFG) approach. We illustrate, using AND and OR concurrent constructs of the HCFG approach, how the design process completion time can be reduced by employing concurrent design efforts. We also present an approach for completion time improvement which considers the sensitivity of completion time with respect to task completion time and probabilities. HCFG analysis facilitates a pre-execution “what-if” analysis to determine the suitable design flow which provides lowest process completion time},
 bibtype = {inproceedings},
 author = {Sahula, V. and Ravikumar, C.P.},
 doi = {10.1109/ICPWC.2000.905765},
 booktitle = {2000 IEEE International Conference on Personal Wireless Communications. Conference Proceedings (Cat. No.00TH8488)}
}

In this paper, we present a design planning paradigm for the design of a wireless mobile transceiver. We consider the digital part in a single chip implementation of a transceiver based on the CDMA spread spectrum technique. The complexity of such a chip implementation makes the design process complex and very expensive. The desired characteristics of a mobile transceiver are low cost, small size, and low power. Design cost forms a major portion of total system cost. In order to reduce design cost, design completion time should be reduced. We assume hardware-software design flow for design of the transceiver. We analyze the design flow using the hierarchical concurrent flow graph (HCFG) approach. We illustrate, using AND and OR concurrent constructs of the HCFG approach, how the design process completion time can be reduced by employing concurrent design efforts. We also present an approach for completion time improvement which considers the sensitivity of completion time with respect to task completion time and probabilities. HCFG analysis facilitates a pre-execution &ldquo;what-if&rdquo; analysis to determine the suitable design flow which provides lowest process completion time

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@inproceedings{
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@article{
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