\n \n \n
\n
\n\n \n \n \n \n \n A Hierarchical and Distributed Fault Tolerant Proposal for NoC-Based MPSoCs.\n \n \n \n\n\n \n W. Wachter, E.; Fochi, V.; Barreto, F.; Amory, A. M.; and Moraes, F. G.\n\n\n \n\n\n\n
IEEE Transactions on Emerging Topics in Computing, 6(4): 524-537. Oct 2018.\n
\n\n
\n\n
\n\n
\n\n \n\n \n \n doi\n \n \n\n \n link\n \n \n\n bibtex\n \n\n \n \n \n abstract \n \n\n \n\n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n\n\n\n
\n
@ARTICLE{7517358, \nauthor={E. {W. Wachter} and V. {Fochi} and F. {Barreto} and Alexandre M. Amory and F. G. {Moraes}}, \njournal={IEEE Transactions on Emerging Topics in Computing}, \ntitle={A Hierarchical and Distributed Fault Tolerant Proposal for NoC-Based MPSoCs}, \nyear={2018}, \nvolume={6}, \nnumber={4}, \npages={524-537}, \nabstract={Aggressive scaling of CMOS process technology allows the fabrication of highly integrated chips such as NoC-based MPSoCs. However, fault probability increases when devices’ size reduces. Hence, fault tolerant design has an important role in current nanometric technologies, leading to research on fault mitigation techniques for NoC-based MPSoCs. Most of the state-of-the-art papers present partial solutions to design a fault tolerant MPSoC, i.e., they present fault tolerant mechanisms for either NoCs or processing elements (PEs). Thegoalof this paper is to propose a comprehensive integration of previously defined recovery mechanisms. The mainnoveltyis the system-level integration itself, which is organized in a hierarchical and distributed manner, ensuring the correct execution of applications in the presence of multiple transient or permanent faults in both the NoC and/or the PEs. The combination of both NoC and PE recovery methods enable the proposed system to tolerate a very severe number of faults. Depending on the severity of the fault in the NoC, it may operate in degraded mode or require the search of fault-free paths. In both cases, the communication is reestablished in less than 50 microseconds. Faults detected into the PEs fire a lightweight and fast task relocation protocol, which executes in less than one millisecond.}, \nkeywords = {mpsoc, fault tolerance},\ndoi={10.1109/TETC.2016.2593640}, \nISSN={2168-6750}, \nmonth={Oct},}\n\n\n\n
\n
\n\n\n
\n Aggressive scaling of CMOS process technology allows the fabrication of highly integrated chips such as NoC-based MPSoCs. However, fault probability increases when devices’ size reduces. Hence, fault tolerant design has an important role in current nanometric technologies, leading to research on fault mitigation techniques for NoC-based MPSoCs. Most of the state-of-the-art papers present partial solutions to design a fault tolerant MPSoC, i.e., they present fault tolerant mechanisms for either NoCs or processing elements (PEs). Thegoalof this paper is to propose a comprehensive integration of previously defined recovery mechanisms. The mainnoveltyis the system-level integration itself, which is organized in a hierarchical and distributed manner, ensuring the correct execution of applications in the presence of multiple transient or permanent faults in both the NoC and/or the PEs. The combination of both NoC and PE recovery methods enable the proposed system to tolerate a very severe number of faults. Depending on the severity of the fault in the NoC, it may operate in degraded mode or require the search of fault-free paths. In both cases, the communication is reestablished in less than 50 microseconds. Faults detected into the PEs fire a lightweight and fast task relocation protocol, which executes in less than one millisecond.\n
\n\n\n
\n\n\n
\n\n\n
\n
\n\n \n \n \n \n \n Broker Fault Recovery for a Multiprocessor System-an-Chip Middleware.\n \n \n \n\n\n \n Domingues, A. R. P.; Hamerski, J. C.; and Amory, A.\n\n\n \n\n\n\n In
2018 31st Symposium on Integrated Circuits and Systems Design (SBCCI), pages 1-6, Aug 2018. \n
\n\n
\n\n
\n\n
\n\n \n\n \n \n doi\n \n \n\n \n link\n \n \n\n bibtex\n \n\n \n \n \n abstract \n \n\n \n\n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n\n\n\n
\n
@INPROCEEDINGS{8533254,\nauthor={A. R. P. {Domingues} and J. C. {Hamerski} and A. {Amory}},\nbooktitle={2018 31st Symposium on Integrated Circuits and Systems Design (SBCCI)},\ntitle={Broker Fault Recovery for a Multiprocessor System-an-Chip Middleware},\nyear={2018},\nvolume={},\nnumber={},\npages={1-6},\nabstract={The publish-subscribe programming model has been used successfully in many distributed embedded application domains and has been recently ported to the MPSoC domain. However, the publish-subscribe model requires the element of the broker, which is a single process that manages the communication between nodes; a unique point of failure in the system. This paper presents a lightweight extension of the publish-subscribe model with a fault recovery method for the broker. The results show that the proposed method inserts small memory footprint to the system while providing minimal system downtime during recovery.},\nkeywords={mpsoc, software},\ndoi={10.1109/SBCCI.2018.8533254},\nISSN={},\nmonth={Aug},}\n\n\n\n
\n
\n\n\n
\n The publish-subscribe programming model has been used successfully in many distributed embedded application domains and has been recently ported to the MPSoC domain. However, the publish-subscribe model requires the element of the broker, which is a single process that manages the communication between nodes; a unique point of failure in the system. This paper presents a lightweight extension of the publish-subscribe model with a fault recovery method for the broker. The results show that the proposed method inserts small memory footprint to the system while providing minimal system downtime during recovery.\n
\n\n\n
\n\n\n
\n
\n\n \n \n \n \n \n Testable Error Detection Logic Design Applied to an Asynchronous Timing Resilient Template.\n \n \n \n\n\n \n Kuentzer, F. A.; Juracy, L. R.; Moreira, M. T.; and Amory, A. M.\n\n\n \n\n\n\n In
2018 31st Symposium on Integrated Circuits and Systems Design (SBCCI), pages 1-6, Aug 2018. \n
\n\n
\n\n
\n\n
\n\n \n\n \n \n doi\n \n \n\n \n link\n \n \n\n bibtex\n \n\n \n \n \n abstract \n \n\n \n\n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n\n\n\n
\n
@INPROCEEDINGS{8533263,\nauthor={F. A. {Kuentzer} and L. R. {Juracy} and M. T. {Moreira} and Alexandre M. {Amory}},\nbooktitle={2018 31st Symposium on Integrated Circuits and Systems Design (SBCCI)},\ntitle={Testable Error Detection Logic Design Applied to an Asynchronous Timing Resilient Template},\nyear={2018},\nvolume={},\nnumber={},\npages={1-6},\nabstract={Resilient circuits are becoming a popular alternative to cope with process, voltage, and temperature variability under ultra-deep-submicron technology. Timing resilient architectures rely on error detection logic (EDL) to detect and recover from timing violations. Different EDLs have been proposed to either reduce the area overheads associated with the additional circuitry or to reduce recovery time, but most of them do not account for testability. This paper proposes a testable EDL (TEDL) architecture for manufacturing and field testing. Fault coverage and area overhead are illustrated on a resilient implementation of Plasma, a 3-stage OpenCore MIPS CPU, which contains the proposed testable EDL circuitry. The results show that 100\\% of the stuck-at faults of the TEDL are detectable with 4.61\\% area overhead when compared to the Plasma with the original EDL design.},\nkeywords = {async, testing},\ndoi={10.1109/SBCCI.2018.8533263},\nISSN={},\nmonth={Aug},}\n\n\n
\n
\n\n\n
\n Resilient circuits are becoming a popular alternative to cope with process, voltage, and temperature variability under ultra-deep-submicron technology. Timing resilient architectures rely on error detection logic (EDL) to detect and recover from timing violations. Different EDLs have been proposed to either reduce the area overheads associated with the additional circuitry or to reduce recovery time, but most of them do not account for testability. This paper proposes a testable EDL (TEDL) architecture for manufacturing and field testing. Fault coverage and area overhead are illustrated on a resilient implementation of Plasma, a 3-stage OpenCore MIPS CPU, which contains the proposed testable EDL circuitry. The results show that 100% of the stuck-at faults of the TEDL are detectable with 4.61% area overhead when compared to the Plasma with the original EDL design.\n
\n\n\n
\n\n\n
\n\n\n
\n
\n\n \n \n \n \n \n A DfT Insertion Methodology to Scannable Q-Flop Elements.\n \n \n \n\n\n \n Juracy, L. R.; Moreira, M. T.; Kuentzer, F. A.; and Amory, A. M.\n\n\n \n\n\n\n
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 26(8): 1609-1612. Aug 2018.\n
\n\n
\n\n
\n\n
\n\n \n\n \n \n doi\n \n \n\n \n link\n \n \n\n bibtex\n \n\n \n \n \n abstract \n \n\n \n\n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n\n\n\n
\n
@ARTICLE{Juracy-tvlsi2018, \nauthor={L. R. Juracy and M. T. Moreira and F. A. Kuentzer and Alexandre M. Amory}, \n journal={IEEE Transactions on Very Large Scale Integration (VLSI) Systems}, \n title={A DfT Insertion Methodology to Scannable Q-Flop Elements}, \n year={2018}, \n volume={26},\n number={8},\n pages={1609-1612}, \n abstract={The Q-Flop is an alternative memory element for designs that are prone to metastability. It has been substantially explored by past research work, specially in synchronization schemes. However, there is very limited support to test insertion on these critical components. This brief presents a testable Q-flop cell and a methodology to integrate it to standard synthesis and DfT flows, allowing automated scan insertion using conventional sequential cells and commercial design automation solutions. Experimental results explore the tradeoffs of the proposed cell in terms of silicon area, energy, and power when compared to the original Q-flop.}, \n keywords = {async, testing},\n doi={10.1109/TVLSI.2018.2821134}, \n ISSN={1063-8210}, \n month={Aug}\n}\n\n
\n
\n\n\n
\n The Q-Flop is an alternative memory element for designs that are prone to metastability. It has been substantially explored by past research work, specially in synchronization schemes. However, there is very limited support to test insertion on these critical components. This brief presents a testable Q-flop cell and a methodology to integrate it to standard synthesis and DfT flows, allowing automated scan insertion using conventional sequential cells and commercial design automation solutions. Experimental results explore the tradeoffs of the proposed cell in terms of silicon area, energy, and power when compared to the original Q-flop.\n
\n\n\n
\n\n\n
\n
\n\n \n \n \n \n \n Software-Defined Networking Architecture for NoC-Based Many-Cores.\n \n \n \n\n\n \n Ruaro, M.; Medina, H. M.; Amory, A. M.; and Moraes, F. G.\n\n\n \n\n\n\n In
IEEE International Symposium on Circuits and Systems (ISCAS), pages 1–4, 2018. \n
\n\n
\n\n
\n\n
\n\n \n\n \n \n doi\n \n \n\n \n link\n \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n\n\n\n
\n
@inproceedings{Ruaro18,\n author = {Marcelo Ruaro and Henrique Martins Medina and Alexandre M. Amory and Fernado G. Moraes},\n title = {Software-Defined Networking Architecture for NoC-Based Many-Cores},\n booktitle = {IEEE International Symposium on Circuits and Systems (ISCAS)},\n pages = {1--4},\n doi={10.1109/ISCAS.2018.8351830}, \n year = {2018},\nkeywords={mpsoc, software}\n}\n\n
\n
\n\n\n\n
\n\n\n
\n
\n\n \n \n \n \n \n An LSSD Compliant Scan Cell for Flip-Flops.\n \n \n \n\n\n \n Juracy, L. R.; Moreira, M. T.; Kuentzer, F. A.; Moraes, F. G.; and Amory, A. M.\n\n\n \n\n\n\n In
IEEE International Symposium on Circuits and Systems (ISCAS), pages 1–4, 2018. \n
\n\n
\n\n
\n\n
\n\n \n\n \n \n doi\n \n \n\n \n link\n \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n\n\n\n
\n
@inproceedings{Juracy18,\n author = {Leonardo Rezende Juracy and Matheus Trevisan Moreira and Felipe A. Kuentzer and F. G. Moraes and Alexandre M. Amory },\n title = {An LSSD Compliant Scan Cell for Flip-Flops},\n booktitle = {IEEE International Symposium on Circuits and Systems (ISCAS)},\n pages = {1--4},\n doi={10.1109/ISCAS.2018.8351515}, \n year = {2018},\n keywords = {async, testing}\n}\n\n
\n
\n\n\n\n
\n\n\n
\n
\n\n \n \n \n \n \n On the Reuse of Timing Resilient Architecture for Testing Path Delay Faults in Critical Paths.\n \n \n \n\n\n \n Kuentzer, F. A.; Juracy, L. R.; and Amory, A. M.\n\n\n \n\n\n\n In
IEEE Design, Automation and Test in Europe (DATE), pages 379–384, 2018. \n
\n\n
\n\n
\n\n
\n\n \n\n \n \n doi\n \n \n\n \n link\n \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n\n\n\n
\n
@inproceedings{Kuentzer18,\n author = {Felipe A. Kuentzer and Leonardo Rezende Juracy and\n Alexandre M. Amory },\n title = {On the Reuse of Timing Resilient Architecture for Testing Path Delay Faults in Critical Paths},\n booktitle = {IEEE Design, Automation and Test in Europe (DATE)},\n pages = {379--384},\n doi={10.23919/DATE.2018.8342039}, \n year = {2018},\n keywords = {async, testing}\n}\n\n
\n
\n\n\n\n
\n\n\n
\n
\n\n \n \n \n \n \n Toward an Accurate Hydrologic Urban Flooding Simulations for Disaster Robotics.\n \n \n \n\n\n \n Paravisi, M.; A. M. Jorge, V.; and Amory, A.\n\n\n \n\n\n\n In
Proceedings of the 15th International Conference on Informatics in Control, Automation and Robotics - Volume 2: ICINCO,, pages 425-431, 2018. \n
\n\n
\n\n
\n\n
\n\n \n\n \n \n doi\n \n \n\n \n link\n \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n \n \n \n \n \n\n\n\n
\n
@inproceedings{paravisi18icinco,\nauthor={Marcelo Paravisi and Vitor {A. M. Jorge} and Alexandre Amory},\ntitle={Toward an Accurate Hydrologic Urban Flooding Simulations for Disaster Robotics},\nbooktitle={Proceedings of the 15th International Conference on Informatics in Control, Automation and Robotics - Volume 2: ICINCO,},\nyear={2018},\npages={425-431},\ndoi={10.5220/0006904704350441},\nisbn={978-989-758-321-6},\nkeywords = {robotics}\n}\n\n
\n
\n\n\n\n
\n\n\n
\n
\n\n \n \n \n \n \n Overseer: A Multi Robot Monitoring Infrastructure.\n \n \n \n\n\n \n Roman, F.; Amory, A.; and Maidana, R.\n\n\n \n\n\n\n In
Proceedings of the 15th International Conference on Informatics in Control, Automation and Robotics - Volume 1: ICINCO,, pages 141-148, 2018. \n
\n\n
\n\n
\n\n
\n\n \n\n \n \n doi\n \n \n\n \n link\n \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n \n \n \n \n \n\n\n\n
\n
@inproceedings{roman18icinco,\nauthor={Felipe Roman and Alexandre Amory and Renan Maidana},\ntitle={Overseer: A Multi Robot Monitoring Infrastructure},\nbooktitle={Proceedings of the 15th International Conference on Informatics in Control, Automation and Robotics - Volume 1: ICINCO,},\nyear={2018},\npages={141-148},\ndoi={10.5220/0006851801510158},\nisbn={978-989-758-321-6},\nkeywords = {robotics}\n}\n\n\n\n
\n
\n\n\n\n
\n\n\n\n\n\n