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\n  \n 2020\n \n \n (6)\n \n \n
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\n \n\n \n \n \n \n \n Test oriented design and layout generation of an asynchronous controller for the blade template.\n \n \n \n\n\n \n Kuentzer, F. A; Juracy, L. R; Moreira, M. T; and Amory, A. M\n\n\n \n\n\n\n In 2020 26th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), pages 86–93, 2020. IEEE\n \n\n\n\n
\n\n\n\n \n\n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{kuentzer2020test,\n  title={Test oriented design and layout generation of an asynchronous controller for the blade template},\n  author={Kuentzer, Felipe A and Juracy, Leonardo R and Moreira, Matheus T and Amory, Alexandre M},\n  booktitle={2020 26th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC)},\n  pages={86--93},\n  year={2020},\n  organization={IEEE}\n}\n\n
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\n \n\n \n \n \n \n \n A Survey of Aging Monitors and Reconfiguration Techniques.\n \n \n \n\n\n \n Juracy, L. R.; Moreira, M. T.; Amory, A. d. M.; and Moraes, F. G.\n\n\n \n\n\n\n arXiv preprint arXiv:2007.07829. 2020.\n \n\n\n\n
\n\n\n\n \n\n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@article{juracy2020survey,\n  title={A Survey of Aging Monitors and Reconfiguration Techniques},\n  author={Juracy, Leonardo Rezende and Moreira, Matheus Trevisan and Amory, Alexandre de Morais and Moraes, Fernando Gehm},\n  journal={arXiv preprint arXiv:2007.07829},\n  year={2020}\n}\n\n
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\n \n\n \n \n \n \n \n Braille character detection using deep neural networks for an educational robot for visually impaired people.\n \n \n \n\n\n \n Gonçalves, D.; Santos, G.; Campos, M.; Amory, A.; and Manssour, I.\n\n\n \n\n\n\n In Anais do XVI Workshop de Visão Computacional, pages 123–128, 2020. SBC\n \n\n\n\n
\n\n\n\n \n\n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{gonccalves2020braille,\n  title={Braille character detection using deep neural networks for an educational robot for visually impaired people},\n  author={Gon{\\c{c}}alves, Diego and Santos, Gabriel and Campos, M{\\'a}rcia and Amory, Alexandre and Manssour, Isabel},\n  booktitle={Anais do XVI Workshop de Vis{\\~a}o Computacional},\n  pages={123--128},\n  year={2020},\n  organization={SBC}\n}\n\n\n
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\n \n\n \n \n \n \n \n Testing the blade resilient asynchronous template.\n \n \n \n\n\n \n Kuentzer, F. A; Juracy, L. R; Moreira, M. T; and Amory, A. M\n\n\n \n\n\n\n Analog Integrated Circuits and Signal Processing,1–16. 2020.\n \n\n\n\n
\n\n\n\n \n\n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@article{kuentzer2020testing,\n  title={Testing the blade resilient asynchronous template},\n  author={Kuentzer, Felipe A and Juracy, Leonardo R and Moreira, Matheus T and Amory, Alexandre M},\n  journal={Analog Integrated Circuits and Signal Processing},\n  pages={1--16},\n  year={2020},\n  publisher={Springer}\n}\n\n\n
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\n \n\n \n \n \n \n \n A fault recovery protocol for brokers in centralized publish-subscribe systems targeting multiprocessor systems-on-chips.\n \n \n \n\n\n \n Domingues, A. R.; Hamerski, J. C.; and de Morais Amory, A.\n\n\n \n\n\n\n Analog Integrated Circuits and Signal Processing,1–16. 2020.\n \n\n\n\n
\n\n\n\n \n\n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@article{domingues2020fault,\n  title={A fault recovery protocol for brokers in centralized publish-subscribe systems targeting multiprocessor systems-on-chips},\n  author={Domingues, Anderson RP and Hamerski, Jean Carlo and de Morais Amory, Alexandre},\n  journal={Analog Integrated Circuits and Signal Processing},\n  pages={1--16},\n  year={2020},\n  publisher={Springer}\n}\n\n\n
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\n \n\n \n \n \n \n \n Energy-Aware Path Planning for Autonomous Mobile Robot Navigation.\n \n \n \n\n\n \n Maidana, R.; Granada, R.; Jurak, D.; Magnaguagno, M.; Meneguzzi, F.; and Amory, A.\n\n\n \n\n\n\n In The Thirty-Third International Flairs Conference, 2020. \n \n\n\n\n
\n\n\n\n \n\n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{maidana2020energy,\n  title={Energy-Aware Path Planning for Autonomous Mobile Robot Navigation},\n  author={Maidana, Renan and Granada, Roger and Jurak, Darlan and Magnaguagno, Maur{\\'\\i}cio and Meneguzzi, Felipe and Amory, Alexandre},\n  booktitle={The Thirty-Third International Flairs Conference},\n  year={2020}\n}\n\n
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\n  \n 2019\n \n \n (3)\n \n \n
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\n \n\n \n \n \n \n \n \n Unmanned Surface Vehicle Simulator with Realistic Environmental Disturbances.\n \n \n \n \n\n\n \n Paravisi, M.; H. Santos, D.; Jorge, V.; Heck, G.; Gonçalves, L. M.; and Amory, A. M.\n\n\n \n\n\n\n Sensors, 19(5). 2019.\n \n\n\n\n
\n\n\n\n \n \n \"UnmannedPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n  \n \n abstract \n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n \n \n\n\n\n
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@Article{s19051068,\nAUTHOR = {Paravisi, Marcelo and H. Santos, Davi and Jorge, Vitor and Heck, Guilherme and Gonçalves, Luiz Marcos and Alexandre M. Amory},\nTITLE = {Unmanned Surface Vehicle Simulator with Realistic Environmental Disturbances},\nJOURNAL = {Sensors},\nVOLUME = {19},\nYEAR = {2019},\nNUMBER = {5},\nARTICLE-NUMBER = {1068},\nURL = {http://www.mdpi.com/1424-8220/19/5/1068},\nISSN = {1424-8220},\nABSTRACT = {The use of robotics in disaster scenarios has become a reality. However, an Unmanned Surface Vehicle (USV) needs a robust navigation strategy to face unpredictable environmental forces such as waves, wind, and water current. A starting step toward this goal is to have a programming environment with realistic USV models where designers can assess their control strategies under different degrees of environmental disturbances. This paper presents a simulation environment integrated with robotic middleware which models the forces that act on a USV in a disaster scenario. Results show that these environmental forces affect the USV&rsquo;s trajectories negatively, indicating the need for more research on USV control strategies considering harsh environmental conditions. Evaluation scenarios were presented to highlight specific features of the simulator, including a bridge inspection scenario with fast water current and winds.},\nkeywords={robotics},\nDOI = {10.3390/s19051068}\n}\n\n\n\n
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\n\n\n
\n The use of robotics in disaster scenarios has become a reality. However, an Unmanned Surface Vehicle (USV) needs a robust navigation strategy to face unpredictable environmental forces such as waves, wind, and water current. A starting step toward this goal is to have a programming environment with realistic USV models where designers can assess their control strategies under different degrees of environmental disturbances. This paper presents a simulation environment integrated with robotic middleware which models the forces that act on a USV in a disaster scenario. Results show that these environmental forces affect the USV’s trajectories negatively, indicating the need for more research on USV control strategies considering harsh environmental conditions. Evaluation scenarios were presented to highlight specific features of the simulator, including a bridge inspection scenario with fast water current and winds.\n
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\n \n\n \n \n \n \n \n \n A Survey on Unmanned Surface Vehicles for Disaster Robotics: Main Challenges and Directions.\n \n \n \n \n\n\n \n Jorge, V. A. M.; Granada, R.; Maidana, R. G.; Jurak, D. A.; Heck, G.; Negreiros, A. P. F.; dos Santos, D. H.; Gonçalves, L. M. G.; and Amory, A. M.\n\n\n \n\n\n\n Sensors, 19(3). 2019.\n \n\n\n\n
\n\n\n\n \n \n \"APaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n  \n \n abstract \n \n\n \n  \n \n 2 downloads\n \n \n\n \n \n \n \n \n \n \n\n  \n \n \n \n \n\n\n\n
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@Article{s19030702,\nAUTHOR = {Jorge, Vitor A. M. and Granada, Roger and Maidana, Renan G. and Jurak, Darlan A. and Heck, Guilherme and Negreiros, Alvaro P. F. and dos Santos, Davi H. and Gonçalves, Luiz M. G. and Alexandre M. Amory},\nTITLE = {A Survey on Unmanned Surface Vehicles for Disaster Robotics: Main Challenges and Directions},\nJOURNAL = {Sensors},\nVOLUME = {19},\nYEAR = {2019},\nNUMBER = {3},\nARTICLE-NUMBER = {702},\nURL = {http://www.mdpi.com/1424-8220/19/3/702},\nISSN = {1424-8220},\nABSTRACT = {Disaster robotics has become a research area in its own right, with several reported cases of successful robot deployment in actual disaster scenarios. Most of these disaster deployments use aerial, ground, or underwater robotic platforms. However, the research involving autonomous boats or Unmanned Surface Vehicles (USVs) for Disaster Management (DM) is currently spread across several publications, with varying degrees of depth, and focusing on more than one unmanned vehicle&mdash;usually under the umbrella of Unmanned Marine Vessels (UMV). Therefore, the current importance of USVs for the DM process in its different phases is not clear. This paper presents the first comprehensive survey about the applications and roles of USVs for DM, as far as we know. This work demonstrates that there are few current deployments in disaster scenarios, with most of the research in the area focusing on the technological aspects of USV hardware and software, such as Guidance Navigation and Control, and not focusing on their actual importance for DM. Finally, to guide future research, this paper also summarizes our own contributions, the lessons learned, guidelines, and research gaps.},\nkeywords={robotics},\nDOI = {10.3390/s19030702}\n}\n\n\n
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\n\n\n
\n Disaster robotics has become a research area in its own right, with several reported cases of successful robot deployment in actual disaster scenarios. Most of these disaster deployments use aerial, ground, or underwater robotic platforms. However, the research involving autonomous boats or Unmanned Surface Vehicles (USVs) for Disaster Management (DM) is currently spread across several publications, with varying degrees of depth, and focusing on more than one unmanned vehicle—usually under the umbrella of Unmanned Marine Vessels (UMV). Therefore, the current importance of USVs for the DM process in its different phases is not clear. This paper presents the first comprehensive survey about the applications and roles of USVs for DM, as far as we know. This work demonstrates that there are few current deployments in disaster scenarios, with most of the research in the area focusing on the technological aspects of USV hardware and software, such as Guidance Navigation and Control, and not focusing on their actual importance for DM. Finally, to guide future research, this paper also summarizes our own contributions, the lessons learned, guidelines, and research gaps.\n
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\n \n\n \n \n \n \n \n Outdoor Localization System with Augmented State Extended Kalman Filter and Radio-Frequency Received Signal Strength.\n \n \n \n\n\n \n Maidana, R.; Amory, A.; and Salton, A.\n\n\n \n\n\n\n In 2019 19th International Conference on Advanced Robotics (ICAR), pages 604–609, 2019. IEEE\n \n\n\n\n
\n\n\n\n \n\n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
\n
@inproceedings{maidana2019outdoor,\n  title={Outdoor Localization System with Augmented State Extended Kalman Filter and Radio-Frequency Received Signal Strength},\n  author={Maidana, Renan and Amory, Alexandre and Salton, Aur{\\'e}lio},\n  booktitle={2019 19th International Conference on Advanced Robotics (ICAR)},\n  pages={604--609},\n  year={2019},\n  organization={IEEE}\n}\n\n\n\n
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\n  \n 2018\n \n \n (11)\n \n \n
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\n \n\n \n \n \n \n \n A Hierarchical and Distributed Fault Tolerant Proposal for NoC-Based MPSoCs.\n \n \n \n\n\n \n W. Wachter, E.; Fochi, V.; Barreto, F.; Amory, A. M.; and Moraes, F. G.\n\n\n \n\n\n\n IEEE Transactions on Emerging Topics in Computing, 6(4): 524-537. Oct 2018.\n \n\n\n\n
\n\n\n\n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n  \n \n abstract \n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n \n \n \n \n\n\n\n
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@ARTICLE{7517358, \nauthor={E. {W. Wachter} and V. {Fochi} and F. {Barreto} and Alexandre M. Amory and F. G. {Moraes}}, \njournal={IEEE Transactions on Emerging Topics in Computing}, \ntitle={A Hierarchical and Distributed Fault Tolerant Proposal for NoC-Based MPSoCs}, \nyear={2018}, \nvolume={6}, \nnumber={4}, \npages={524-537}, \nabstract={Aggressive scaling of CMOS process technology allows the fabrication of highly integrated chips such as NoC-based MPSoCs. However, fault probability increases when devices’ size reduces. Hence, fault tolerant design has an important role in current nanometric technologies, leading to research on fault mitigation techniques for NoC-based MPSoCs. Most of the state-of-the-art papers present partial solutions to design a fault tolerant MPSoC, i.e., they present fault tolerant mechanisms for either NoCs or processing elements (PEs). Thegoalof this paper is to propose a comprehensive integration of previously defined recovery mechanisms. The mainnoveltyis the system-level integration itself, which is organized in a hierarchical and distributed manner, ensuring the correct execution of applications in the presence of multiple transient or permanent faults in both the NoC and/or the PEs. The combination of both NoC and PE recovery methods enable the proposed system to tolerate a very severe number of faults. Depending on the severity of the fault in the NoC, it may operate in degraded mode or require the search of fault-free paths. In both cases, the communication is reestablished in less than 50 microseconds. Faults detected into the PEs fire a lightweight and fast task relocation protocol, which executes in less than one millisecond.}, \nkeywords  = {mpsoc, fault tolerance},\ndoi={10.1109/TETC.2016.2593640}, \nISSN={2168-6750}, \nmonth={Oct},}\n\n\n\n
\n
\n\n\n
\n Aggressive scaling of CMOS process technology allows the fabrication of highly integrated chips such as NoC-based MPSoCs. However, fault probability increases when devices’ size reduces. Hence, fault tolerant design has an important role in current nanometric technologies, leading to research on fault mitigation techniques for NoC-based MPSoCs. Most of the state-of-the-art papers present partial solutions to design a fault tolerant MPSoC, i.e., they present fault tolerant mechanisms for either NoCs or processing elements (PEs). Thegoalof this paper is to propose a comprehensive integration of previously defined recovery mechanisms. The mainnoveltyis the system-level integration itself, which is organized in a hierarchical and distributed manner, ensuring the correct execution of applications in the presence of multiple transient or permanent faults in both the NoC and/or the PEs. The combination of both NoC and PE recovery methods enable the proposed system to tolerate a very severe number of faults. Depending on the severity of the fault in the NoC, it may operate in degraded mode or require the search of fault-free paths. In both cases, the communication is reestablished in less than 50 microseconds. Faults detected into the PEs fire a lightweight and fast task relocation protocol, which executes in less than one millisecond.\n
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\n \n\n \n \n \n \n \n A Design Patterns-Based Middleware for Multiprocessor Systems-on-Chip.\n \n \n \n\n\n \n Hamerski, J. C.; Abich, G.; Reis, R.; Ost, L.; and Amory, A.\n\n\n \n\n\n\n In 2018 31st Symposium on Integrated Circuits and Systems Design (SBCCI), pages 1-6, Aug 2018. \n \n\n\n\n
\n\n\n\n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n  \n \n abstract \n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n \n \n \n \n\n\n\n
\n
@INPROCEEDINGS{8533250,\nauthor={J. C. {Hamerski} and G. {Abich} and R. {Reis} and L. {Ost} and A. {Amory}},\nbooktitle={2018 31st Symposium on Integrated Circuits and Systems Design (SBCCI)},\ntitle={A Design Patterns-Based Middleware for Multiprocessor Systems-on-Chip},\nyear={2018},\nvolume={},\nnumber={},\npages={1-6},\nabstract={Current multiprocessor systems might comprise dozens of processors, requiring a runtime management to provide performance while complying with system's constraints such as energy consumption, thermal balance, and fault tolerance. Self-adaptive multiprocessor systems have been proposed to cover some key aspects such as hardware abstraction, programming models and modular software architecture. This paper provides a modular middleware to assist the development of self-adaptive services and applications on MPSoC environments. Based on key design patterns, the proposed middleware uses highly efficient features of object-oriented programming for embedded systems and specific compiler optimization options. The results show a case study of a self-adaptive application on top of the proposed middleware. Additional experiments demonstrate a reduction in the execution time from 3\\% up to 19\\%, presenting a memory footprint overhead of 8.7\\% when compared to previous middleware without the features to ease modular software design.},\nkeywords={mpsoc, software},\ndoi={10.1109/SBCCI.2018.8533250},\nISSN={},\nmonth={Aug},}\n\n\n
\n
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\n Current multiprocessor systems might comprise dozens of processors, requiring a runtime management to provide performance while complying with system's constraints such as energy consumption, thermal balance, and fault tolerance. Self-adaptive multiprocessor systems have been proposed to cover some key aspects such as hardware abstraction, programming models and modular software architecture. This paper provides a modular middleware to assist the development of self-adaptive services and applications on MPSoC environments. Based on key design patterns, the proposed middleware uses highly efficient features of object-oriented programming for embedded systems and specific compiler optimization options. The results show a case study of a self-adaptive application on top of the proposed middleware. Additional experiments demonstrate a reduction in the execution time from 3% up to 19%, presenting a memory footprint overhead of 8.7% when compared to previous middleware without the features to ease modular software design.\n
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\n \n\n \n \n \n \n \n Broker Fault Recovery for a Multiprocessor System-an-Chip Middleware.\n \n \n \n\n\n \n Domingues, A. R. P.; Hamerski, J. C.; and Amory, A.\n\n\n \n\n\n\n In 2018 31st Symposium on Integrated Circuits and Systems Design (SBCCI), pages 1-6, Aug 2018. \n \n\n\n\n
\n\n\n\n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n  \n \n abstract \n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n \n \n \n \n\n\n\n
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@INPROCEEDINGS{8533254,\nauthor={A. R. P. {Domingues} and J. C. {Hamerski} and A. {Amory}},\nbooktitle={2018 31st Symposium on Integrated Circuits and Systems Design (SBCCI)},\ntitle={Broker Fault Recovery for a Multiprocessor System-an-Chip Middleware},\nyear={2018},\nvolume={},\nnumber={},\npages={1-6},\nabstract={The publish-subscribe programming model has been used successfully in many distributed embedded application domains and has been recently ported to the MPSoC domain. However, the publish-subscribe model requires the element of the broker, which is a single process that manages the communication between nodes; a unique point of failure in the system. This paper presents a lightweight extension of the publish-subscribe model with a fault recovery method for the broker. The results show that the proposed method inserts small memory footprint to the system while providing minimal system downtime during recovery.},\nkeywords={mpsoc, software},\ndoi={10.1109/SBCCI.2018.8533254},\nISSN={},\nmonth={Aug},}\n\n\n\n
\n
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\n The publish-subscribe programming model has been used successfully in many distributed embedded application domains and has been recently ported to the MPSoC domain. However, the publish-subscribe model requires the element of the broker, which is a single process that manages the communication between nodes; a unique point of failure in the system. This paper presents a lightweight extension of the publish-subscribe model with a fault recovery method for the broker. The results show that the proposed method inserts small memory footprint to the system while providing minimal system downtime during recovery.\n
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\n \n\n \n \n \n \n \n Testable Error Detection Logic Design Applied to an Asynchronous Timing Resilient Template.\n \n \n \n\n\n \n Kuentzer, F. A.; Juracy, L. R.; Moreira, M. T.; and Amory, A. M.\n\n\n \n\n\n\n In 2018 31st Symposium on Integrated Circuits and Systems Design (SBCCI), pages 1-6, Aug 2018. \n \n\n\n\n
\n\n\n\n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n  \n \n abstract \n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n \n \n \n \n\n\n\n
\n
@INPROCEEDINGS{8533263,\nauthor={F. A. {Kuentzer} and L. R. {Juracy} and M. T. {Moreira} and Alexandre M. {Amory}},\nbooktitle={2018 31st Symposium on Integrated Circuits and Systems Design (SBCCI)},\ntitle={Testable Error Detection Logic Design Applied to an Asynchronous Timing Resilient Template},\nyear={2018},\nvolume={},\nnumber={},\npages={1-6},\nabstract={Resilient circuits are becoming a popular alternative to cope with process, voltage, and temperature variability under ultra-deep-submicron technology. Timing resilient architectures rely on error detection logic (EDL) to detect and recover from timing violations. Different EDLs have been proposed to either reduce the area overheads associated with the additional circuitry or to reduce recovery time, but most of them do not account for testability. This paper proposes a testable EDL (TEDL) architecture for manufacturing and field testing. Fault coverage and area overhead are illustrated on a resilient implementation of Plasma, a 3-stage OpenCore MIPS CPU, which contains the proposed testable EDL circuitry. The results show that 100\\% of the stuck-at faults of the TEDL are detectable with 4.61\\% area overhead when compared to the Plasma with the original EDL design.},\nkeywords  = {async, testing},\ndoi={10.1109/SBCCI.2018.8533263},\nISSN={},\nmonth={Aug},}\n\n\n
\n
\n\n\n
\n Resilient circuits are becoming a popular alternative to cope with process, voltage, and temperature variability under ultra-deep-submicron technology. Timing resilient architectures rely on error detection logic (EDL) to detect and recover from timing violations. Different EDLs have been proposed to either reduce the area overheads associated with the additional circuitry or to reduce recovery time, but most of them do not account for testability. This paper proposes a testable EDL (TEDL) architecture for manufacturing and field testing. Fault coverage and area overhead are illustrated on a resilient implementation of Plasma, a 3-stage OpenCore MIPS CPU, which contains the proposed testable EDL circuitry. The results show that 100% of the stuck-at faults of the TEDL are detectable with 4.61% area overhead when compared to the Plasma with the original EDL design.\n
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\n \n\n \n \n \n \n \n Evaluating Serialization for a Publish-Subscribe Based Middleware for MPSoCs.\n \n \n \n\n\n \n Hamerski, J. C.; Domingues, A. R. P.; Moraes, F. G.; and Amory, A.\n\n\n \n\n\n\n In 2018 25th IEEE International Conference on Electronics, Circuits and Systems (ICECS), pages 773-776, Dec 2018. \n \n\n\n\n
\n\n\n\n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n  \n \n abstract \n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n \n \n \n \n\n\n\n
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@INPROCEEDINGS{8618003,\nauthor={J. C. {Hamerski} and A. R. P. {Domingues} and F. G. {Moraes} and A. {Amory}},\nbooktitle={2018 25th IEEE International Conference on Electronics, Circuits and Systems (ICECS)},\ntitle={Evaluating Serialization for a Publish-Subscribe Based Middleware for MPSoCs},\nyear={2018},\nvolume={},\nnumber={},\npages={773-776},\nabstract={Efficient serialization is a must-have feature in distributed embedded protocol stacks because of the restrained resources available for use in such systems. Although there are many serialization libraries out there, only some of them focus on resource usage, which is of most importance for the embedded domain. Thus, a comparison of serialization libraries considering resource usage is of high relevance for the embedded systems domain. This paper presents an experiment-based comparison of serialization libraries while concentrating on resource usage for a multiprocessor system-on-chip (MPSoC) platform. Results show that MsgPuck library surpasses other libraries for both serialization speed and memory consumption criteria.},\ndoi={10.1109/ICECS.2018.8618003},\nkeywords={mpsoc, software},\nISSN={},\nmonth={Dec},}\n\n
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\n Efficient serialization is a must-have feature in distributed embedded protocol stacks because of the restrained resources available for use in such systems. Although there are many serialization libraries out there, only some of them focus on resource usage, which is of most importance for the embedded domain. Thus, a comparison of serialization libraries considering resource usage is of high relevance for the embedded systems domain. This paper presents an experiment-based comparison of serialization libraries while concentrating on resource usage for a multiprocessor system-on-chip (MPSoC) platform. Results show that MsgPuck library surpasses other libraries for both serialization speed and memory consumption criteria.\n
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\n \n\n \n \n \n \n \n A DfT Insertion Methodology to Scannable Q-Flop Elements.\n \n \n \n\n\n \n Juracy, L. R.; Moreira, M. T.; Kuentzer, F. A.; and Amory, A. M.\n\n\n \n\n\n\n IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 26(8): 1609-1612. Aug 2018.\n \n\n\n\n
\n\n\n\n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n  \n \n abstract \n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n \n \n \n \n\n\n\n
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@ARTICLE{Juracy-tvlsi2018, \nauthor={L. R. Juracy and M. T. Moreira and F. A. Kuentzer and Alexandre M. Amory}, \n  journal={IEEE Transactions on Very Large Scale Integration (VLSI) Systems}, \n  title={A DfT Insertion Methodology to Scannable Q-Flop Elements}, \n  year={2018}, \n  volume={26},\n  number={8},\n  pages={1609-1612}, \n  abstract={The Q-Flop is an alternative memory element for designs that are prone to metastability. It has been substantially explored by past research work, specially in synchronization schemes. However, there is very limited support to test insertion on these critical components. This brief presents a testable Q-flop cell and a methodology to integrate it to standard synthesis and DfT flows, allowing automated scan insertion using conventional sequential cells and commercial design automation solutions. Experimental results explore the tradeoffs of the proposed cell in terms of silicon area, energy, and power when compared to the original Q-flop.}, \n  keywords  = {async, testing},\n  doi={10.1109/TVLSI.2018.2821134}, \n  ISSN={1063-8210}, \n  month={Aug}\n}\n\n
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\n The Q-Flop is an alternative memory element for designs that are prone to metastability. It has been substantially explored by past research work, specially in synchronization schemes. However, there is very limited support to test insertion on these critical components. This brief presents a testable Q-flop cell and a methodology to integrate it to standard synthesis and DfT flows, allowing automated scan insertion using conventional sequential cells and commercial design automation solutions. Experimental results explore the tradeoffs of the proposed cell in terms of silicon area, energy, and power when compared to the original Q-flop.\n
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\n \n\n \n \n \n \n \n Software-Defined Networking Architecture for NoC-Based Many-Cores.\n \n \n \n\n\n \n Ruaro, M.; Medina, H. M.; Amory, A. M.; and Moraes, F. G.\n\n\n \n\n\n\n In IEEE International Symposium on Circuits and Systems (ISCAS), pages 1–4, 2018. \n \n\n\n\n
\n\n\n\n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n \n \n \n \n\n\n\n
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@inproceedings{Ruaro18,\n  author    = {Marcelo Ruaro and Henrique Martins Medina and  Alexandre M. Amory and Fernado G. Moraes},\n  title     = {Software-Defined Networking Architecture for NoC-Based Many-Cores},\n  booktitle = {IEEE International Symposium on Circuits and Systems (ISCAS)},\n  pages     = {1--4},\n  doi={10.1109/ISCAS.2018.8351830}, \n  year      = {2018},\nkeywords={mpsoc, software}\n}\n\n
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\n \n\n \n \n \n \n \n An LSSD Compliant Scan Cell for Flip-Flops.\n \n \n \n\n\n \n Juracy, L. R.; Moreira, M. T.; Kuentzer, F. A.; Moraes, F. G.; and Amory, A. M.\n\n\n \n\n\n\n In IEEE International Symposium on Circuits and Systems (ISCAS), pages 1–4, 2018. \n \n\n\n\n
\n\n\n\n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n \n \n \n \n\n\n\n
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@inproceedings{Juracy18,\n  author    = {Leonardo Rezende Juracy and Matheus Trevisan Moreira and Felipe A. Kuentzer and F. G. Moraes and Alexandre M. Amory },\n  title     = {An LSSD Compliant Scan Cell for Flip-Flops},\n  booktitle = {IEEE International Symposium on Circuits and Systems (ISCAS)},\n  pages     = {1--4},\n  doi={10.1109/ISCAS.2018.8351515}, \n  year      = {2018},\n  keywords  = {async, testing}\n}\n\n
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\n \n\n \n \n \n \n \n On the Reuse of Timing Resilient Architecture for Testing Path Delay Faults in Critical Paths.\n \n \n \n\n\n \n Kuentzer, F. A.; Juracy, L. R.; and Amory, A. M.\n\n\n \n\n\n\n In IEEE Design, Automation and Test in Europe (DATE), pages 379–384, 2018. \n \n\n\n\n
\n\n\n\n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n \n \n \n \n\n\n\n
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@inproceedings{Kuentzer18,\n  author    = {Felipe A. Kuentzer and Leonardo Rezende Juracy and\n               Alexandre M. Amory },\n  title     = {On the Reuse of Timing Resilient Architecture for Testing Path Delay Faults in Critical Paths},\n  booktitle = {IEEE Design, Automation and Test in Europe (DATE)},\n  pages     = {379--384},\n  doi={10.23919/DATE.2018.8342039}, \n  year      = {2018},\n  keywords  = {async, testing}\n}\n\n
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\n \n\n \n \n \n \n \n Toward an Accurate Hydrologic Urban Flooding Simulations for Disaster Robotics.\n \n \n \n\n\n \n Paravisi, M.; A. M. Jorge, V.; and Amory, A.\n\n\n \n\n\n\n In Proceedings of the 15th International Conference on Informatics in Control, Automation and Robotics - Volume 2: ICINCO,, pages 425-431, 2018. \n \n\n\n\n
\n\n\n\n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n \n \n\n\n\n
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@inproceedings{paravisi18icinco,\nauthor={Marcelo Paravisi and Vitor {A. M. Jorge} and Alexandre Amory},\ntitle={Toward an Accurate Hydrologic Urban Flooding Simulations for Disaster Robotics},\nbooktitle={Proceedings of the 15th International Conference on Informatics in Control, Automation and Robotics - Volume 2: ICINCO,},\nyear={2018},\npages={425-431},\ndoi={10.5220/0006904704350441},\nisbn={978-989-758-321-6},\nkeywords  = {robotics}\n}\n\n
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\n \n\n \n \n \n \n \n Overseer: A Multi Robot Monitoring Infrastructure.\n \n \n \n\n\n \n Roman, F.; Amory, A.; and Maidana, R.\n\n\n \n\n\n\n In Proceedings of the 15th International Conference on Informatics in Control, Automation and Robotics - Volume 1: ICINCO,, pages 141-148, 2018. \n \n\n\n\n
\n\n\n\n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n \n \n\n\n\n
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@inproceedings{roman18icinco,\nauthor={Felipe Roman and Alexandre Amory and Renan Maidana},\ntitle={Overseer: A Multi Robot Monitoring Infrastructure},\nbooktitle={Proceedings of the 15th International Conference on Informatics in Control, Automation and Robotics - Volume 1: ICINCO,},\nyear={2018},\npages={141-148},\ndoi={10.5220/0006851801510158},\nisbn={978-989-758-321-6},\nkeywords  = {robotics}\n}\n\n\n\n
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\n  \n 2017\n \n \n (7)\n \n \n
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\n \n\n \n \n \n \n \n Optimized Design of an LSSD Scan Cell.\n \n \n \n\n\n \n Juracy, L. R.; Moreira, M. T.; Kuentzer, F. A.; and Amory, A. M.\n\n\n \n\n\n\n IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 25(2): 765-768. Feb 2017.\n \n\n\n\n
\n\n\n\n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n  \n \n abstract \n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n \n \n \n \n\n\n\n
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@ARTICLE{7522078, \nauthor={L. R. Juracy and M. T. Moreira and F. A. Kuentzer and Alexandre M. Amory}, \njournal={IEEE Transactions on Very Large Scale Integration (VLSI) Systems}, \ntitle={Optimized Design of an LSSD Scan Cell}, \nyear={2017}, \nvolume={25}, \nnumber={2}, \npages={765-768}, \nabstract={Type D flip-flop cell and its scannable version called Muxed-D are the most used sequential components in cell-based synchronous designs because it simplifies timing analysis and it is less susceptible to race problems. However, as technology nodes shrink, it becomes more difficult, especially for high-performance designs, to cope with a hard global timing boundary. The use of latches emerges as a possible solution to the contemporary design challenges such as clock skew/jitter, PVT variation, and low-power and high-performance designs. Moreover, latches are also gaining popularity among asynchronous and timing resilient circuits. One of the available scannable cells for latches is called level sensitivity scan-based design (LSSD). The goal of this brief is to present an open design of an optimized single-latch LSSD cell, which has better tradeoffs between propagation delay, power, energy, and silicon area than the original LSSD design, thus reducing the cost for testing latch-based designs.}, \ndoi={10.1109/TVLSI.2016.2589548}, \nkeywords={async,testing},\nISSN={1063-8210}, \nmonth={Feb},}\n\n\n
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\n Type D flip-flop cell and its scannable version called Muxed-D are the most used sequential components in cell-based synchronous designs because it simplifies timing analysis and it is less susceptible to race problems. However, as technology nodes shrink, it becomes more difficult, especially for high-performance designs, to cope with a hard global timing boundary. The use of latches emerges as a possible solution to the contemporary design challenges such as clock skew/jitter, PVT variation, and low-power and high-performance designs. Moreover, latches are also gaining popularity among asynchronous and timing resilient circuits. One of the available scannable cells for latches is called level sensitivity scan-based design (LSSD). The goal of this brief is to present an open design of an optimized single-latch LSSD cell, which has better tradeoffs between propagation delay, power, energy, and silicon area than the original LSSD design, thus reducing the cost for testing latch-based designs.\n
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\n \n\n \n \n \n \n \n Publish-subscribe programming for a NoC-based multiprocessor system-on-chip.\n \n \n \n\n\n \n Hamerski, J. C.; Abich, G.; Reis, R.; Ost, L.; and Amory, A.\n\n\n \n\n\n\n In 2017 IEEE International Symposium on Circuits and Systems (ISCAS), pages 1-4, May 2017. \n \n\n\n\n
\n\n\n\n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n  \n \n abstract \n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n \n \n \n \n\n\n\n
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@INPROCEEDINGS{8050967,\nauthor={J. C. {Hamerski} and G. {Abich} and R. {Reis} and L. {Ost} and A. {Amory}},\nbooktitle={2017 IEEE International Symposium on Circuits and Systems (ISCAS)},\ntitle={Publish-subscribe programming for a NoC-based multiprocessor system-on-chip},\nyear={2017},\nvolume={},\nnumber={},\npages={1-4},\nabstract={Shared memory and message passing are traditional parallel programming models used on multiprocessor system-on-chip environments. Underlying models are traditionally meant for static scenarios where all communicating entities and their intercommunication patterns are known a priori by the software engineer. The systems design following such programming models became complex due to dynamic behavior of applications at runtime. The goal of this work is to incorporate a publish-subscribe programming model to an MPSoC framework to decouple, in the time and space, the application development. The modified MPSoC framework is composed of a FreeRTOS kernel running on homogeneous processing elements distributed into a network-on-chip. The results present reduction around of 2\\% to 30\\% in DTW application execution time, and low overhead in memory footprint when comparing the original MPI primitives with the publish-subscribe programming model.},\nkeywords={mpsoc, software},\ndoi={10.1109/ISCAS.2017.8050967},\nISSN={2379-447X},\nmonth={May},}\n\n\n
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\n Shared memory and message passing are traditional parallel programming models used on multiprocessor system-on-chip environments. Underlying models are traditionally meant for static scenarios where all communicating entities and their intercommunication patterns are known a priori by the software engineer. The systems design following such programming models became complex due to dynamic behavior of applications at runtime. The goal of this work is to incorporate a publish-subscribe programming model to an MPSoC framework to decouple, in the time and space, the application development. The modified MPSoC framework is composed of a FreeRTOS kernel running on homogeneous processing elements distributed into a network-on-chip. The results present reduction around of 2% to 30% in DTW application execution time, and low overhead in memory footprint when comparing the original MPI primitives with the publish-subscribe programming model.\n
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\n \n\n \n \n \n \n \n The 2017 Humanitarian Robotics and Automation Technology Challenge [Humanitarian Technology].\n \n \n \n\n\n \n Madhavan, R.; Amory, A.; Prestes, E.; Guedes, R.; Bergamin, A.; Neuland, R.; Mantelli, M.; Kindin, D.; and Rodrigues, F.\n\n\n \n\n\n\n IEEE Robotics & Automation Magazine, 24(4): 127–129. 2017.\n \n\n\n\n
\n\n\n\n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n \n \n\n\n\n
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@article{Madhavan2017,\n  title={The 2017 Humanitarian Robotics and Automation Technology Challenge [Humanitarian Technology]},\n  author={Raj Madhavan and Alexandre Amory and Edson Prestes and Renan Guedes and Augusto Bergamin and Renata Neuland and Mathias Mantelli and Diego Kindin and Fernanda Rodrigues},\n  journal={IEEE Robotics \\& Automation Magazine},\n  volume={24},\n  number={4},\n  pages={127--129},\n  year={2017},\n  doi={https://doi.org/10.1109/MRA.2017.2757722},\n  publisher={IEEE},\n  keywords  = {robotics}\n}\n\n
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\n \n\n \n \n \n \n \n Deep Neural Networks for Handwritten Chinese Character Recognition.\n \n \n \n\n\n \n Maidana, R. G.; Monteiro, J.; Granada, R.; Amory, A. M.; and Barros, R. C.\n\n\n \n\n\n\n In Brazilian Conference on Intelligent Systems (BRACIS), 2017. \n \n\n\n\n
\n\n\n\n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{renan2017deep,\n  title={Deep Neural Networks for Handwritten Chinese Character Recognition},\n  author={Renan G. Maidana and Juarez Monteiro and Roger Granada and Alexandre M. Amory and Rodrigo C. Barros},\n  booktitle={Brazilian Conference on Intelligent Systems (BRACIS)},\n  doi={https://doi.org/10.1109/BRACIS.2017.24},\n  year={2017}\n}\n\n
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\n \n\n \n \n \n \n \n Donnie Robot: Towards an Accessible And Educational Robot for Visually Impaired People.\n \n \n \n\n\n \n Marques, G. H. M.; Einloft, D. C.; Bergamin, A. C. P.; Marek, J. A.; Maidana, R. G.; Campos, M. B.; Manssour, I. H.; and Amory, A. M.\n\n\n \n\n\n\n In Latin American Robotics Symposium (LARS), 2017. \n \n\n\n\n
\n\n\n\n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n \n \n\n\n\n
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@inproceedings{guilherme2017donnie,\n  title={Donnie Robot: Towards an Accessible And Educational Robot for Visually Impaired People},\n  author={Guilherme H. M. Marques and Daniel C. Einloft and Augusto C. P. Bergamin and Joice A. Marek and Renan G. Maidana and Marcia B. Campos and Isabel H. Manssour and Alexandre M. Amory},\n  booktitle={Latin American Robotics Symposium (LARS)},\n  doi={https://doi.org/10.1109/SBR-LARS-R.2017.8215273},\n  year={2017}, \n  keywords  = {robotics}  \n}\n\n
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\n \n\n \n \n \n \n \n Odometria Visual Monocular para Localização de Robô Terrestre.\n \n \n \n\n\n \n Maidana, R. G.; Salton, A. T.; and Amory, A. M.\n\n\n \n\n\n\n In SBAI, 2017. \n \n\n\n\n
\n\n\n\n \n\n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n \n \n\n\n\n
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@inproceedings{maidana2017odometria,\n  title={Odometria Visual Monocular para Localiza{\\c{c}}{\\~a}o de Rob{\\^o} Terrestre},\n  author={Renan Guedes Maidana and Aurelio Tergolina Salton and Alexandre M. Amory},\n  booktitle={SBAI},\n  year={2017},\n  keywords  = {robotics}  \n}\n\n\n
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\n \n\n \n \n \n \n \n \n .\n \n \n \n \n\n\n \n Oliveira, J. D.; Campos, M. B.; Amory, A. M.; and Manssour, I. H.\n\n\n \n\n\n\n Teaching Robot Programming Activities for Visually Impaired Students: A Systematic Review, pages 155–167. Antona, M.; and Stephanidis, C., editor(s). Springer International Publishing, 2017.\n \n\n\n\n
\n\n\n\n \n \n \"TeachingPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n  \n \n abstract \n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n \n \n\n\n\n
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@Inbook{DamasioOliveira2017,\nauthor={Juliana Damasio Oliveira \nand M{\\'a}rcia Borba Campos\nand Alexandre M. Amory\nand Isabel Harb Manssour},\neditor="Antona, Margherita\nand Stephanidis, Constantine",\ntitle="Teaching Robot Programming Activities for Visually Impaired Students: A Systematic Review",\nbookTitle="Universal Access in Human--Computer Interaction. Human and Technological Environments: 11th International Conference, UAHCI 2017, Held as Part of HCI International 2017, Vancouver, BC, Canada, July 9--14, 2017, Proceedings, Part III",\nyear="2017",\npublisher="Springer International Publishing",\npages="155--167",\nabstract="This paper presents a systematic review of studies concerning the use of robotics for the programming education of individuals with visual impairment. This study presents a thorough discussion and classification of the surveyed papers, including: different programming teaching methodologies based on robotics for people who are blind; the use of several robotics kits and programming environments; the evaluation procedure for each environment; and the challenges found during the teaching process. Based on these papers we created a guideline to prepare, conduct and evaluate a robot programming workshop for people who are visually impaired. These instructions include, for example, how to train instructors to work in workshops for people with visual disabilities, how to prepare concrete and digital support materials, suggestions of work dynamics for programming teaching, how to conduct collaborative activities, forms of feedback for the student to better understand the syntax and semantics of the language, recommendations for the development of a robotic environment concerning the hardware (robot) and software (programming language to operate the robot). These recommendations were validated with two users with visual impairment.",\nkeywords={robotics},\nisbn="978-3-319-58700-4",\ndoi="10.1007/978-3-319-58700-4_14",\nurl="https://doi.org/10.1007/978-3-319-58700-4_14"\n}\n\n\n\n
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\n This paper presents a systematic review of studies concerning the use of robotics for the programming education of individuals with visual impairment. This study presents a thorough discussion and classification of the surveyed papers, including: different programming teaching methodologies based on robotics for people who are blind; the use of several robotics kits and programming environments; the evaluation procedure for each environment; and the challenges found during the teaching process. Based on these papers we created a guideline to prepare, conduct and evaluate a robot programming workshop for people who are visually impaired. These instructions include, for example, how to train instructors to work in workshops for people with visual disabilities, how to prepare concrete and digital support materials, suggestions of work dynamics for programming teaching, how to conduct collaborative activities, forms of feedback for the student to better understand the syntax and semantics of the language, recommendations for the development of a robotic environment concerning the hardware (robot) and software (programming language to operate the robot). These recommendations were validated with two users with visual impairment.\n
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\n  \n 2016\n \n \n (3)\n \n \n
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\n \n\n \n \n \n \n \n A data extraction and debugging framework for large-scale MPSoCs.\n \n \n \n\n\n \n Ruaro, M.; Chamorra, H.; Rubin, F.; Amory, A.; and Moraes, F. G.\n\n\n \n\n\n\n In 2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS), pages 616-619, Dec 2016. \n \n\n\n\n
\n\n\n\n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n \n \n\n\n\n
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@INPROCEEDINGS{7841277, \nauthor={M. Ruaro and H. Chamorra and F. Rubin and A. Amory and F. G. Moraes}, \nbooktitle={2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS)}, \ntitle={A data extraction and debugging framework for large-scale MPSoCs}, \nyear={2016}, \npages={616-619},  \ndoi={10.1109/ICECS.2016.7841277}, \nkeywords={mpsoc},\nmonth={Dec},}\n\n
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\n \n\n \n \n \n \n \n Fault Classification of the Error Detection Logic in the Blade Resilient Templates.\n \n \n \n\n\n \n Kuentzer, F. A.; and Amory, A. M.\n\n\n \n\n\n\n In IEEE International Symposium on Asynchronous Circuits and Systems, pages 1–6, 2016. \n \n\n\n\n
\n\n\n\n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n \n \n \n \n\n\n\n
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@inproceedings{DBLP:conf/async/Kuentzer16,\n  author    = {Felipe A. Kuentzer and\n               Alexandre M. Amory },\n  title     = {Fault Classification of the Error Detection Logic in the Blade Resilient Templates},\n  booktitle = {IEEE International Symposium on Asynchronous Circuits and Systems},\n  pages     = {1--6},\n  year      = {2016},\n  doi       = {https://doi.org/10.1109/ASYNC.2016.9},\n  keywords  = {async, testing}\n}\n\n
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\n \n\n \n \n \n \n \n \n A layered approach for fault tolerant NoC-based MPSoCs - Special session: Dependable MPSoCs.\n \n \n \n \n\n\n \n Wächter, E.; Barreto, F. F. S.; Fochi, V.; Amory, A. M.; and Moraes, F. G.\n\n\n \n\n\n\n In 17th Latin-American Test Symposium, LATS 2016, Foz do Iguacu, Brazil, April 6-8, 2016, pages 189–194, 2016. \n \n\n\n\n
\n\n\n\n \n \n \"APaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n \n \n \n \n\n\n\n
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@inproceedings{DBLP:conf/latw/WachterBFAM16,\n  author    = {Eduardo W{\\"{a}}chter and\n               Francisco F. S. Barreto and\n               Vinicius Fochi and\n               Alexandre M. Amory and\n               Fernando Gehm Moraes},\n  title     = {A layered approach for fault tolerant NoC-based MPSoCs - Special session:\n               Dependable MPSoCs},\n  booktitle = {17th Latin-American Test Symposium, {LATS} 2016, Foz do Iguacu, Brazil,\n               April 6-8, 2016},\n  pages     = {189--194},\n  year      = {2016},\n  crossref  = {DBLP:conf/latw/2016},\n  url       = {http://dx.doi.org/10.1109/LATW.2016.7483367},\n  doi       = {10.1109/LATW.2016.7483367},\n  timestamp = {Fri, 03 Jun 2016 16:39:38 +0200},\n  biburl    = {http://dblp.uni-trier.de/rec/bib/conf/latw/WachterBFAM16},\n  bibsource = {dblp computer science bibliography, http://dblp.org},\n  keywords  = {mpsoc, fault tolerance}\n}\n\n
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\n  \n 2015\n \n \n (3)\n \n \n
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\n \n\n \n \n \n \n \n \n Distributed fault diagnosis for multiple mobile robots using an agent programming language.\n \n \n \n \n\n\n \n Morais, M. G.; Meneguzzi, F. R.; Bordini, R. H.; and Amory, A. M.\n\n\n \n\n\n\n In International Conference on Advanced Robotics, ICAR 2015, Istanbul, Turkey, July 27-31, 2015, pages 395–400, 2015. \n \n\n\n\n
\n\n\n\n \n \n \"DistributedPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n \n \n \n \n\n\n\n
\n
@inproceedings{DBLP:conf/icar/MoraisMBA15,\n  author    = {Marcio G. Morais and\n               Felipe Rech Meneguzzi and\n               Rafael H. Bordini and\n               Alexandre M. Amory},\n  title     = {Distributed fault diagnosis for multiple mobile robots using an agent\n               programming language},\n  booktitle = {International Conference on Advanced Robotics, {ICAR} 2015, Istanbul,\n               Turkey, July 27-31, 2015},\n  pages     = {395--400},\n  year      = {2015},\n  crossref  = {DBLP:conf/icar/2015},\n  url       = {http://dx.doi.org/10.1109/ICAR.2015.7251486},\n  doi       = {10.1109/ICAR.2015.7251486},\n  timestamp = {Tue, 22 Sep 2015 20:37:46 +0200},\n  biburl    = {http://dblp.uni-trier.de/rec/bib/conf/icar/MoraisMBA15},\n  bibsource = {dblp computer science bibliography, http://dblp.org},\n  keywords  = {robotics, fault tolerance}  \n}\n\n
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\n \n\n \n \n \n \n \n \n Fault recovery protocol for distributed memory MPSoCs.\n \n \n \n \n\n\n \n Barreto, F. F. S.; Amory, A. M.; and Moraes, F. G.\n\n\n \n\n\n\n In 2015 IEEE International Symposium on Circuits and Systems, ISCAS 2015, Lisbon, Portugal, May 24-27, 2015, pages 421–424, 2015. \n \n\n\n\n
\n\n\n\n \n \n \"FaultPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n \n \n \n \n\n\n\n
\n
@inproceedings{DBLP:conf/iscas/BarretoAM15,\n  author    = {Francisco F. S. Barreto and\n               Alexandre M. Amory and\n               Fernando Gehm Moraes},\n  title     = {Fault recovery protocol for distributed memory MPSoCs},\n  booktitle = {2015 {IEEE} International Symposium on Circuits and Systems, {ISCAS}\n               2015, Lisbon, Portugal, May 24-27, 2015},\n  pages     = {421--424},\n  year      = {2015},\n  crossref  = {DBLP:conf/iscas/2015},\n  url       = {http://dx.doi.org/10.1109/ISCAS.2015.7168660},\n  doi       = {10.1109/ISCAS.2015.7168660},\n  timestamp = {Wed, 05 Aug 2015 09:08:53 +0200},\n  biburl    = {http://dblp.uni-trier.de/rec/bib/conf/iscas/BarretoAM15},\n  bibsource = {dblp computer science bibliography, http://dblp.org},\n  keywords  = {mpsoc, fault tolerance}  \n}\n\n
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\n \n\n \n \n \n \n \n \n An integrated method for implementing online fault detection in NoC-based MPSoCs.\n \n \n \n \n\n\n \n Fochi, V.; Wächter, E.; Erichsen, A.; Amory, A. M.; and Moraes, F. G.\n\n\n \n\n\n\n In 2015 IEEE International Symposium on Circuits and Systems, ISCAS 2015, Lisbon, Portugal, May 24-27, 2015, pages 1562–1565, 2015. \n \n\n\n\n
\n\n\n\n \n \n \"AnPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n \n \n \n \n\n\n\n
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@inproceedings{DBLP:conf/iscas/FochiWEAM15,\n  author    = {Vinicius Fochi and\n               Eduardo W{\\"{a}}chter and\n               Augusto Erichsen and\n               Alexandre M. Amory and\n               Fernando Gehm Moraes},\n  title     = {An integrated method for implementing online fault detection in NoC-based\n               MPSoCs},\n  booktitle = {2015 {IEEE} International Symposium on Circuits and Systems, {ISCAS}\n               2015, Lisbon, Portugal, May 24-27, 2015},\n  pages     = {1562--1565},\n  year      = {2015},\n  crossref  = {DBLP:conf/iscas/2015},\n  url       = {http://dx.doi.org/10.1109/ISCAS.2015.7168945},\n  doi       = {10.1109/ISCAS.2015.7168945},\n  timestamp = {Wed, 05 Aug 2015 09:08:53 +0200},\n  biburl    = {http://dblp.uni-trier.de/rec/bib/conf/iscas/FochiWEAM15},\n  bibsource = {dblp computer science bibliography, http://dblp.org},\n  keywords  = {mpsoc, fault tolerance}\n}\n\n
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\n  \n 2014\n \n \n (3)\n \n \n
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\n \n\n \n \n \n \n \n \n Optimization and Analysis of Seriation Algorithm for Ordering Protein Networks.\n \n \n \n \n\n\n \n Kuentzer, F. A.; Pereira, A. S.; Amory, A. M.; Perrone, G.; Silva, S. R. M.; Dinis, J. M.; and Almeida, R. M. C.\n\n\n \n\n\n\n In 2014 IEEE International Conference on Bioinformatics and Bioengineering, Boca Raton, FL, USA, November 10-12, 2014, pages 231–237, 2014. \n \n\n\n\n
\n\n\n\n \n \n \"OptimizationPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n \n \n \n \n \n \n\n\n\n
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@inproceedings{DBLP:conf/bibe/KuentzerPAPSDA14,\n  author    = {Felipe A. Kuentzer and\n               Alexandre S. Pereira and\n               Alexandre M. Amory and\n               Gabriel Perrone and\n               Samoel R. M. Silva and\n               Joao M. Dinis and\n               Rita M. C. Almeida},\n  title     = {Optimization and Analysis of Seriation Algorithm for Ordering Protein\n               Networks},\n  booktitle = {2014 {IEEE} International Conference on Bioinformatics and Bioengineering,\n               Boca Raton, FL, USA, November 10-12, 2014},\n  pages     = {231--237},\n  year      = {2014},\n  crossref  = {DBLP:conf/bibe/2014},\n  url       = {http://dx.doi.org/10.1109/BIBE.2014.43},\n  doi       = {10.1109/BIBE.2014.43},\n  timestamp = {Fri, 08 Jan 2016 00:00:00 +0100},\n  biburl    = {http://dblp.uni-trier.de/rec/bib/conf/bibe/KuentzerPAPSDA14},\n  bibsource = {dblp computer science bibliography, http://dblp.org},\n  keywords  = {bioinformatics, seriation, software optimization}  \n}\n\n
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\n \n\n \n \n \n \n \n \n Runtime fault recovery protocol for NoC-based MPSoCs.\n \n \n \n \n\n\n \n Wächter, E.; Erichsen, A.; Juracy, L. R.; Amory, A. M.; and Moraes, F. G.\n\n\n \n\n\n\n In Fifteenth International Symposium on Quality Electronic Design, ISQED 2014, Santa Clara, CA, USA, March 3-5, 2014, pages 132–139, 2014. \n \n\n\n\n
\n\n\n\n \n \n \"RuntimePaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n \n \n \n \n\n\n\n
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@inproceedings{DBLP:conf/isqed/WachterEJAM14,\n  author    = {Eduardo W{\\"{a}}chter and\n               Augusto Erichsen and\n               Leonardo R. Juracy and\n               Alexandre M. Amory and\n               Fernando Gehm Moraes},\n  title     = {Runtime fault recovery protocol for NoC-based MPSoCs},\n  booktitle = {Fifteenth International Symposium on Quality Electronic Design, {ISQED}\n               2014, Santa Clara, CA, USA, March 3-5, 2014},\n  pages     = {132--139},\n  year      = {2014},\n  crossref  = {DBLP:conf/isqed/2014},\n  url       = {http://dx.doi.org/10.1109/ISQED.2014.6783316},\n  doi       = {10.1109/ISQED.2014.6783316},\n  timestamp = {Fri, 26 Sep 2014 14:08:22 +0200},\n  biburl    = {http://dblp.uni-trier.de/rec/bib/conf/isqed/WachterEJAM14},\n  bibsource = {dblp computer science bibliography, http://dblp.org},\n  keywords  = {mpsoc, fault tolerance}\n  \n}\n\n
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\n \n\n \n \n \n \n \n \n A Fast Runtime Fault Recovery Approach for NoC-Based MPSoCS for Performance Constrained Applications.\n \n \n \n \n\n\n \n Wächter, E.; Erichsen, A.; Juracy, L. R.; Amory, A. M.; and Moraes, F. G.\n\n\n \n\n\n\n In Proceedings of the 27th Symposium on Integrated Circuits and Systems Design, Aracaju, Brazil, September 1-5, 2014, pages 18:1–18:7, 2014. \n \n\n\n\n
\n\n\n\n \n \n \"APaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n \n \n \n \n\n\n\n
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@inproceedings{DBLP:conf/sbcci/WachterEJAM14,\n  author    = {Eduardo W{\\"{a}}chter and\n               Augusto Erichsen and\n               Leonardo R. Juracy and\n               Alexandre M. Amory and\n               Fernando Gehm Moraes},\n  title     = {A Fast Runtime Fault Recovery Approach for NoC-Based MPSoCS for Performance\n               Constrained Applications},\n  booktitle = {Proceedings of the 27th Symposium on Integrated Circuits and Systems\n               Design, Aracaju, Brazil, September 1-5, 2014},\n  pages     = {18:1--18:7},\n  year      = {2014},\n  crossref  = {DBLP:conf/sbcci/2014},\n  url       = {http://doi.acm.org/10.1145/2660540.2660986},\n  doi       = {10.1145/2660540.2660986},\n  timestamp = {Thu, 23 Apr 2015 01:00:00 +0200},\n  biburl    = {http://dblp.uni-trier.de/rec/bib/conf/sbcci/WachterEJAM14},\n  bibsource = {dblp computer science bibliography, http://dblp.org},\n  keywords  = {mpsoc, fault tolerance}\n\n}\n\n
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\n  \n 2013\n \n \n (6)\n \n \n
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\n \n\n \n \n \n \n \n \n Topology-agnostic fault-tolerant NoC routing method.\n \n \n \n \n\n\n \n Wächter, E.; Erichsen, A.; Amory, A. M.; and Moraes, F. G.\n\n\n \n\n\n\n In Design, Automation and Test in Europe, DATE 13, Grenoble, France, March 18-22, 2013, pages 1595–1600, 2013. \n \n\n\n\n
\n\n\n\n \n \n \"Topology-agnosticPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n \n \n \n \n\n\n\n
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@inproceedings{DBLP:conf/date/WachterEAM13,\n  author    = {Eduardo W{\\"{a}}chter and\n               Augusto Erichsen and\n               Alexandre M. Amory and\n               Fernando Gehm Moraes},\n  title     = {Topology-agnostic fault-tolerant NoC routing method},\n  booktitle = {Design, Automation and Test in Europe, {DATE} 13, Grenoble, France,\n               March 18-22, 2013},\n  pages     = {1595--1600},\n  year      = {2013},\n  crossref  = {DBLP:conf/date/2013},\n  url       = {http://dx.doi.org/10.7873/DATE.2013.324},\n  doi       = {10.7873/DATE.2013.324},\n  timestamp = {Wed, 11 Nov 2015 00:00:00 +0100},\n  biburl    = {http://dblp.uni-trier.de/rec/bib/conf/date/WachterEAM13},\n  bibsource = {dblp computer science bibliography, http://dblp.org},\n  keywords  = {noc, fault tolerance}\n}\n\n
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\n \n\n \n \n \n \n \n \n Phoenix NoC: A distributed fault tolerant architecture.\n \n \n \n \n\n\n \n Marcon, C. A. M.; Amory, A. M.; Webber, T.; Volpato, T.; and Poehls, L. B.\n\n\n \n\n\n\n In 2013 IEEE 31st International Conference on Computer Design, ICCD 2013, Asheville, NC, USA, October 6-9, 2013, pages 7–12, 2013. \n \n\n\n\n
\n\n\n\n \n \n \"PhoenixPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n \n \n \n \n\n\n\n
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@inproceedings{DBLP:conf/iccd/MarconAWVP13,\n  author    = {C{\\'{e}}sar A. M. Marcon and\n               Alexandre M. Amory and\n               Thais Webber and\n               Thomas Volpato and\n               Leticia B. Poehls},\n  title     = {Phoenix NoC: {A} distributed fault tolerant architecture},\n  booktitle = {2013 {IEEE} 31st International Conference on Computer Design, {ICCD}\n               2013, Asheville, NC, USA, October 6-9, 2013},\n  pages     = {7--12},\n  year      = {2013},\n  crossref  = {DBLP:conf/iccd/2013},\n  url       = {http://dx.doi.org/10.1109/ICCD.2013.6657018},\n  doi       = {10.1109/ICCD.2013.6657018},\n  timestamp = {Mon, 22 Sep 2014 16:50:10 +0200},\n  biburl    = {http://dblp.uni-trier.de/rec/bib/conf/iccd/MarconAWVP13},\n  bibsource = {dblp computer science bibliography, http://dblp.org},\n  keywords  = {noc, fault tolerance}\n}\n\n
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\n \n\n \n \n \n \n \n \n Evaluating the scalability of test buses.\n \n \n \n \n\n\n \n Amory, A. M.; Moreira, M. T.; Calazans, N. L. V.; Moraes, F. G.; Lazzari, C.; and Lubaszewski, M.\n\n\n \n\n\n\n In 2013 International Symposium on System on Chip, ISSoC 2013, Tampere, Finland, October 23-24, 2013, pages 1–6, 2013. \n \n\n\n\n
\n\n\n\n \n \n \"EvaluatingPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n \n \n \n \n\n\n\n
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@inproceedings{DBLP:conf/issoc/AmoryMCMLL13,\n  author    = {Alexandre M. Amory and\n               Matheus T. Moreira and\n               Ney Laert Vilar Calazans and\n               Fernando Gehm Moraes and\n               Cristiano Lazzari and\n               Marcelo Lubaszewski},\n  title     = {Evaluating the scalability of test buses},\n  booktitle = {2013 International Symposium on System on Chip, ISSoC 2013, Tampere,\n               Finland, October 23-24, 2013},\n  pages     = {1--6},\n  year      = {2013},\n  crossref  = {DBLP:conf/issoc/2013},\n  url       = {http://dx.doi.org/10.1109/ISSoC.2013.6675278},\n  doi       = {10.1109/ISSoC.2013.6675278},\n  timestamp = {Thu, 18 Dec 2014 16:57:42 +0100},\n  biburl    = {http://dblp.uni-trier.de/rec/bib/conf/issoc/AmoryMCMLL13},\n  bibsource = {dblp computer science bibliography, http://dblp.org},\n  keywords  = {noc,testing}\n}\n\n
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\n \n\n \n \n \n \n \n \n Determining the test sources/sinks for NoC TAMs.\n \n \n \n \n\n\n \n Amory, A. M.; Moreno, E. I.; Moraes, F. G.; and Lubaszewski, M.\n\n\n \n\n\n\n In IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2013, Natal, Brazil, August 5-7, 2013, pages 8–13, 2013. \n \n\n\n\n
\n\n\n\n \n \n \"DeterminingPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n \n \n \n \n\n\n\n
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@inproceedings{DBLP:conf/isvlsi/AmoryMML13,\n  author    = {Alexandre M. Amory and\n               Edson I. Moreno and\n               Fernando Gehm Moraes and\n               Marcelo Lubaszewski},\n  title     = {Determining the test sources/sinks for NoC TAMs},\n  booktitle = {{IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2013, Natal,\n               Brazil, August 5-7, 2013},\n  pages     = {8--13},\n  year      = {2013},\n  crossref  = {DBLP:conf/isvlsi/2013},\n  url       = {http://dx.doi.org/10.1109/ISVLSI.2013.6654615},\n  doi       = {10.1109/ISVLSI.2013.6654615},\n  timestamp = {Tue, 26 May 2015 18:41:04 +0200},\n  biburl    = {http://dblp.uni-trier.de/rec/bib/conf/isvlsi/AmoryMML13},\n  bibsource = {dblp computer science bibliography, http://dblp.org},\n  keywords  = {noc,testing}\n}\n\n
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\n \n\n \n \n \n \n \n \n Fault recovery communication protocol for NoC-based MPSoCs.\n \n \n \n \n\n\n \n Wächter, E.; Amory, A. M.; and Moraes, F. G.\n\n\n \n\n\n\n In IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2013, Natal, Brazil, August 5-7, 2013, pages 219–220, 2013. \n \n\n\n\n
\n\n\n\n \n \n \"FaultPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n \n \n \n \n\n\n\n
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@inproceedings{DBLP:conf/isvlsi/WachterAM13,\n  author    = {Eduardo W{\\"{a}}chter and\n               Alexandre M. Amory and\n               Fernando Gehm Moraes},\n  title     = {Fault recovery communication protocol for NoC-based MPSoCs},\n  booktitle = {{IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2013, Natal,\n               Brazil, August 5-7, 2013},\n  pages     = {219--220},\n  year      = {2013},\n  crossref  = {DBLP:conf/isvlsi/2013},\n  url       = {http://dx.doi.org/10.1109/ISVLSI.2013.6654648},\n  doi       = {10.1109/ISVLSI.2013.6654648},\n  timestamp = {Tue, 26 May 2015 18:41:04 +0200},\n  biburl    = {http://dblp.uni-trier.de/rec/bib/conf/isvlsi/WachterAM13},\n  bibsource = {dblp computer science bibliography, http://dblp.org},\n  keywords  = {mpsoc, fault tolerance}\n}\n\n
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\n \n\n \n \n \n \n \n \n An implementation of a distributed fault-tolerant mechanism for 2D mesh NoCs.\n \n \n \n \n\n\n \n Marcon, C. A. M.; Amory, A. M.; Bortolon, F. T.; Webber, T.; Volpato, T.; and Munareto, J.\n\n\n \n\n\n\n In Proceedings of the 24th IEEE International Symposium on Rapid System Prototyping, RSP 2013, Montreal, QC, Canada, October 3-4, 2013, pages 24–29, 2013. \n \n\n\n\n
\n\n\n\n \n \n \"AnPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n \n \n \n \n\n\n\n
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@inproceedings{DBLP:conf/rsp/MarconABWVM13,\n  author    = {C{\\'{e}}sar A. M. Marcon and\n               Alexandre M. Amory and\n               Felipe T. Bortolon and\n               Thais Webber and\n               Thomas Volpato and\n               Jader Munareto},\n  title     = {An implementation of a distributed fault-tolerant mechanism for 2D\n               mesh NoCs},\n  booktitle = {Proceedings of the 24th {IEEE} International Symposium on Rapid System\n               Prototyping, {RSP} 2013, Montreal, QC, Canada, October 3-4, 2013},\n  pages     = {24--29},\n  year      = {2013},\n  crossref  = {DBLP:conf/rsp/2013},\n  url       = {http://dx.doi.org/10.1109/RSP.2013.6683954},\n  doi       = {10.1109/RSP.2013.6683954},\n  timestamp = {Mon, 20 Jan 2014 14:07:54 +0100},\n  biburl    = {http://dblp.uni-trier.de/rec/bib/conf/rsp/MarconABWVM13},\n  bibsource = {dblp computer science bibliography, http://dblp.org},\n  keywords  = {mpsoc, fault tolerance}\n}\n\n
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\n  \n 2012\n \n \n (1)\n \n \n
\n
\n \n \n
\n \n\n \n \n \n \n \n Reliability, Availability and Serviceability of Networks-on-Chip.\n \n \n \n\n\n \n Cota, É. F.; Amory, A. M.; and Lubaszewski, M.\n\n\n \n\n\n\n Springer, 2012.\n \n\n\n\n
\n\n\n\n \n\n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n \n \n \n \n\n\n\n
\n
@book{ras-noc-book,\n  author    = {Érika F. Cota and A. M. Amory and Marcelo Lubaszewski}, \n  title     = {Reliability, Availability and Serviceability of Networks-on-Chip},\n  publisher = {Springer},\n  year      = 2012,\n  keywords={testing, noc},\n  isbn      = {9781461407904}\n}\n\n
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\n\n
\n
\n  \n 2011\n \n \n (6)\n \n \n
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\n \n \n
\n \n\n \n \n \n \n \n \n A new test scheduling algorithm based on Networks-on-Chip as Test Access Mechanisms.\n \n \n \n \n\n\n \n Amory, A. M.; Lazzari, C.; Lubaszewski, M.; and Moraes, F. G.\n\n\n \n\n\n\n J. Parallel Distrib. Comput., 71(5): 675–686. 2011.\n \n\n\n\n
\n\n\n\n \n \n \"APaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n \n \n \n \n\n\n\n
\n
@article{DBLP:journals/jpdc/AmoryLLM11,\n  author    = {Alexandre M. Amory and\n               Cristiano Lazzari and\n               Marcelo Lubaszewski and\n               Fernando Gehm Moraes},\n  title     = {A new test scheduling algorithm based on Networks-on-Chip as Test\n               Access Mechanisms},\n  journal   = {J. Parallel Distrib. Comput.},\n  volume    = {71},\n  number    = {5},\n  pages     = {675--686},\n  year      = {2011},\n  url       = {http://dx.doi.org/10.1016/j.jpdc.2010.09.008},\n  doi       = {10.1016/j.jpdc.2010.09.008},\n  timestamp = {Tue, 26 Apr 2011 01:00:00 +0200},\n  biburl    = {http://dblp.uni-trier.de/rec/bib/journals/jpdc/AmoryLLM11},\n  bibsource = {dblp computer science bibliography, http://dblp.org},\n  keywords  = {noc,testing}\n}\n\n
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\n\n\n
\n \n\n \n \n \n \n \n \n Evaluating energy consumption of homogeneous MPSoCs using spare tiles.\n \n \n \n \n\n\n \n Amory, A. M.; Ost, L.; Marcon, C. A. M.; Moraes, F. G.; and Lubaszewski, M.\n\n\n \n\n\n\n In Design, Automation and Test in Europe, DATE 2011, Grenoble, France, March 14-18, 2011, pages 1164–1167, 2011. \n \n\n\n\n
\n\n\n\n \n \n \"EvaluatingPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n \n \n\n\n\n
\n
@inproceedings{DBLP:conf/date/AmoryOMML11,\n  author    = {Alexandre M. Amory and\n               Luciano Ost and\n               C{\\'{e}}sar A. M. Marcon and\n               Fernando Gehm Moraes and\n               Marcelo Lubaszewski},\n  title     = {Evaluating energy consumption of homogeneous MPSoCs using spare tiles},\n  booktitle = {Design, Automation and Test in Europe, {DATE} 2011, Grenoble, France,\n               March 14-18, 2011},\n  pages     = {1164--1167},\n  year      = {2011},\n  crossref  = {DBLP:conf/date/2011},\n  url       = {http://dx.doi.org/10.1109/DATE.2011.5763304},\n  doi       = {10.1109/DATE.2011.5763304},\n  timestamp = {Wed, 11 Nov 2015 10:09:32 +0100},\n  biburl    = {http://dblp.uni-trier.de/rec/bib/conf/date/AmoryOMML11},\n  bibsource = {dblp computer science bibliography, http://dblp.org},\n  keywords  = {mpsoc}\n}\n\n
\n
\n\n\n\n
\n\n\n
\n \n\n \n \n \n \n \n \n Task mapping on NoC-based MPSoCs with faulty tiles: Evaluating the energy consumption and the application execution time.\n \n \n \n \n\n\n \n Amory, A. M.; Marcon, C. A. M.; Moraes, F. G.; and Lubaszewski, M.\n\n\n \n\n\n\n In Proceedings of the 22nd IEEE International Symposium on Rapid System Prototyping, RSP 2011, Karlsruhe, Germany, 24-27 May, 2011, pages 164–170, 2011. \n \n\n\n\n
\n\n\n\n \n \n \"TaskPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n \n \n\n\n\n
\n
@inproceedings{DBLP:conf/rsp/AmoryMML11,\n  author    = {Alexandre M. Amory and\n               C{\\'{e}}sar A. M. Marcon and\n               Fernando Gehm Moraes and\n               Marcelo Lubaszewski},\n  title     = {Task mapping on NoC-based MPSoCs with faulty tiles: Evaluating the\n               energy consumption and the application execution time},\n  booktitle = {Proceedings of the 22nd {IEEE} International Symposium on Rapid System\n               Prototyping, {RSP} 2011, Karlsruhe, Germany, 24-27 May, 2011},\n  pages     = {164--170},\n  year      = {2011},\n  crossref  = {DBLP:conf/rsp/2011},\n  url       = {http://dx.doi.org/10.1109/RSP.2011.5929991},\n  doi       = {10.1109/RSP.2011.5929991},\n  timestamp = {Mon, 14 Nov 2011 10:29:34 +0100},\n  biburl    = {http://dblp.uni-trier.de/rec/bib/conf/rsp/AmoryMML11},\n  bibsource = {dblp computer science bibliography, http://dblp.org},\n  keywords  = {mpsoc}\n}\n\n
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\n \n\n \n \n \n \n \n \n Early estimation of wire length for dedicated test access mechanisms in networks-on-chip based SoCs.\n \n \n \n \n\n\n \n Amory, A. M.; Lazzari, C.; Lubaszewski, M.; and Moraes, F. G.\n\n\n \n\n\n\n In 24th Symposium on Integrated Circuits and Systems Design, SBCCI '11, João Pessoa, Brazil, August 30 - September 02, 2011, pages 73–78, 2011. \n \n\nBest Paper Award\n\n
\n\n\n\n \n \n \"EarlyPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n \n \n \n \n\n\n\n
\n
@inproceedings{DBLP:conf/sbcci/AmoryLLM11,\n  author    = {Alexandre M. Amory and\n               Cristiano Lazzari and\n               Marcelo Lubaszewski and\n               Fernando Gehm Moraes},\n  title     = {Early estimation of wire length for dedicated test access mechanisms\n               in networks-on-chip based SoCs},\n  booktitle = {24th Symposium on Integrated Circuits and Systems Design, {SBCCI}\n               '11, Jo{\\~{a}}o Pessoa, Brazil, August 30 - September 02, 2011},\n  pages     = {73--78},\n  year      = {2011},\n  crossref  = {DBLP:conf/sbcci/2011},\n  url       = {http://doi.acm.org/10.1145/2020876.2020894},\n  doi       = {10.1145/2020876.2020894},\n  timestamp = {Fri, 16 Nov 2012 13:42:43 +0100},\n  biburl    = {http://dblp.uni-trier.de/rec/bib/conf/sbcci/AmoryLLM11},\n  bibsource = {dblp computer science bibliography, http://dblp.org},\n  bibbase_note = {<span style="color: #9CC984"><strong>Best Paper Award</strong></span>},\n  keywords  = {noc,testing}\n}\n\n
\n
\n\n\n\n
\n\n\n
\n \n\n \n \n \n \n \n \n Multi-task dynamic mapping onto NoC-based MPSoCs.\n \n \n \n \n\n\n \n Mandelli, M.; Amory, A. M.; Ost, L.; and Moraes, F. G.\n\n\n \n\n\n\n In 24th Symposium on Integrated Circuits and Systems Design, SBCCI '11, João Pessoa, Brazil, August 30 - September 02, 2011, pages 191–196, 2011. \n \n\n\n\n
\n\n\n\n \n \n \"Multi-taskPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n \n \n\n\n\n
\n
@inproceedings{DBLP:conf/sbcci/MandelliAOM11,\n  author    = {Marcelo Mandelli and\n               Alexandre M. Amory and\n               Luciano Ost and\n               Fernando Gehm Moraes},\n  title     = {Multi-task dynamic mapping onto NoC-based MPSoCs},\n  booktitle = {24th Symposium on Integrated Circuits and Systems Design, {SBCCI}\n               '11, Jo{\\~{a}}o Pessoa, Brazil, August 30 - September 02, 2011},\n  pages     = {191--196},\n  year      = {2011},\n  crossref  = {DBLP:conf/sbcci/2011},\n  url       = {http://doi.acm.org/10.1145/2020876.2020920},\n  doi       = {10.1145/2020876.2020920},\n  timestamp = {Fri, 16 Nov 2012 13:42:43 +0100},\n  biburl    = {http://dblp.uni-trier.de/rec/bib/conf/sbcci/MandelliAOM11},\n  bibsource = {dblp computer science bibliography, http://dblp.org},\n  keywords  = {mpsoc}\n}\n\n\n
\n
\n\n\n\n
\n\n\n
\n \n\n \n \n \n \n \n \n Crosstalk Fault Tolerant NoC: Design and Evaluation.\n \n \n \n \n\n\n \n Lucas, A. H.; Amory, A. M.; and Moraes, F. G.\n\n\n \n\n\n\n In Becker, J.; Johann, M.; and Reis, R., editor(s), VLSI-SoC: Technologies for Systems Integration, pages 81–93, Berlin, Heidelberg, 2011. Springer Berlin Heidelberg\n \n\n\n\n
\n\n\n\n \n \n \"CrosstalkPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n  \n \n abstract \n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n \n \n \n \n\n\n\n
\n
@InProceedings{10.1007/978-3-642-23120-9_5,\nauthor="Lucas, Alzemiro H.\nand Amory, Alexandre M.\nand Moraes, Fernando G.",\neditor="Becker, J{\\"u}rgen\nand Johann, Marcelo\nand Reis, Ricardo",\ntitle="Crosstalk Fault Tolerant NoC: Design and Evaluation",\nbooktitle="VLSI-SoC: Technologies for Systems Integration",\nyear="2011",\npublisher="Springer Berlin Heidelberg",\naddress="Berlin, Heidelberg",\npages="81--93",\nabstract="The innovations on integrated circuit fabrics are continuously reducing components size, which increases the logic density of systems-on-chip (SoC), but also affect the reliability of these components. Chip-level global buses are especially subject to crosstalk faults, which can lead to increased delay and glitches. This paper evaluates different crosstalk fault tolerant approaches for Networks-on-chip (NoCs) links such that the network can maintain the original network performance even in the presence of errors. Three different approaches are presented and evaluated in terms of area overhead, packet latency, power consumption, and residual fault coverage. Results demonstrate that the use of CRC coding at each link is preferred when minimal area and power overhead are the main goals. However, each one of the methods presented here has its own advantages and can be applied depending on the application.",\nkeywords  = {noc,testing},\ndoi="10.1007/978-3-642-23120-9_5",\nurl="http://dx.doi.org/10.1007/978-3-642-23120-9_5",\nisbn="978-3-642-23120-9"\n}\n\n\n\n\n\n
\n
\n\n\n
\n The innovations on integrated circuit fabrics are continuously reducing components size, which increases the logic density of systems-on-chip (SoC), but also affect the reliability of these components. Chip-level global buses are especially subject to crosstalk faults, which can lead to increased delay and glitches. This paper evaluates different crosstalk fault tolerant approaches for Networks-on-chip (NoCs) links such that the network can maintain the original network performance even in the presence of errors. Three different approaches are presented and evaluated in terms of area overhead, packet latency, power consumption, and residual fault coverage. Results demonstrate that the use of CRC coding at each link is preferred when minimal area and power overhead are the main goals. However, each one of the methods presented here has its own advantages and can be applied depending on the application.\n
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\n  \n 2009\n \n \n (1)\n \n \n
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\n \n\n \n \n \n \n \n Testing Chips with Mesh-Based Network-on-Chip.\n \n \n \n\n\n \n Amory, A. M.; Lubaszewski, M.; and Moraes, F. G.\n\n\n \n\n\n\n LAP Lambert Academic Publishing, 2009.\n \n\n\n\n
\n\n\n\n \n\n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n \n \n \n \n\n\n\n
\n
@book{noc-book,\n  author    = {A. M. Amory and Marcelo Lubaszewski and Fernando Gehm Moraes}, \n  title     = {Testing Chips with Mesh-Based Network-on-Chip},\n  publisher = {LAP Lambert Academic Publishing},\n  year      = 2009,\n  keywords={testing, noc},\n  isbn      = {3838321618}\n}\n\n\n
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\n  \n 2008\n \n \n (1)\n \n \n
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\n \n\n \n \n \n \n \n \n A High-Fault-Coverage Approach for the Test of Data, Control and Handshake Interconnects in Mesh Networks-on-Chip.\n \n \n \n \n\n\n \n Cota, É. F.; de Lima Kastensmidt, F. G.; Cassel, M.; Herve, M.; Almeida, P.; Meirelles, P.; Amory, A. M.; and Lubaszewski, M.\n\n\n \n\n\n\n IEEE Trans. Computers, 57(9): 1202–1215. 2008.\n \n\n\n\n
\n\n\n\n \n \n \"APaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n \n \n \n \n\n\n\n
\n
@article{DBLP:journals/tc/CotaKCHAMAL08,\n  author    = {{\\'{E}}rika F. Cota and\n               Fernanda Gusm{\\~{a}}o de Lima Kastensmidt and\n               Maico Cassel and\n               Marcos Herve and\n               Pedro Almeida and\n               Paulo Meirelles and\n               Alexandre M. Amory and\n               Marcelo Lubaszewski},\n  title     = {A High-Fault-Coverage Approach for the Test of Data, Control and Handshake\n               Interconnects in Mesh Networks-on-Chip},\n  journal   = {{IEEE} Trans. Computers},\n  volume    = {57},\n  number    = {9},\n  pages     = {1202--1215},\n  year      = {2008},\n  url       = {http://dx.doi.org/10.1109/TC.2008.62},\n  doi       = {10.1109/TC.2008.62},\n  timestamp = {Tue, 22 Dec 2015 00:00:00 +0100},\n  biburl    = {http://dblp.uni-trier.de/rec/bib/journals/tc/CotaKCHAMAL08},\n  bibsource = {dblp computer science bibliography, http://dblp.org},\n  keywords  = {noc,testing}\n}\n\n
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\n  \n 2007\n \n \n (3)\n \n \n
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\n \n \n
\n \n\n \n \n \n \n \n \n Wrapper design for the reuse of a bus, network-on-chip, or other functional interconnect as test access mechanism.\n \n \n \n \n\n\n \n Amory, A. M.; Goossens, K.; Marinissen, E. J.; Lubaszewski, M.; and Moraes, F. G.\n\n\n \n\n\n\n IET Computers & Digital Techniques, 1(3): 197–206. 2007.\n \n\n\n\n
\n\n\n\n \n \n \"WrapperPaper\n  \n \n\n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n \n \n \n \n\n\n\n
\n
@article{DBLP:journals/iet-cdt/AmoryGMLM07,\n  author    = {Alexandre M. Amory and\n               Kees Goossens and\n               Erik Jan Marinissen and\n               Marcelo Lubaszewski and\n               Fernando  Gehm Moraes},\n  title     = {Wrapper design for the reuse of a bus, network-on-chip, or other functional\n               interconnect as test access mechanism},\n  journal   = {{IET} Computers {\\&} Digital Techniques},\n  volume    = {1},\n  number    = {3},\n  pages     = {197--206},\n  year      = {2007},\n  url       = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=4205035},\n  timestamp = {Wed, 22 Jun 2011 01:00:00 +0200},\n  biburl    = {http://dblp.uni-trier.de/rec/bib/journals/iet-cdt/AmoryGMLM07},\n  bibsource = {dblp computer science bibliography, http://dblp.org},\n  keywords  = {noc,testing}\n}\n\n
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\n \n\n \n \n \n \n \n \n Redefining and testing interconnect faults in Mesh NoCs.\n \n \n \n \n\n\n \n Cota, É. F.; de Lima Kastensmidt, F. G.; Cassel, M.; Meirelles, P.; Amory, A. M.; and Lubaszewski, M.\n\n\n \n\n\n\n In 2007 IEEE International Test Conference, ITC 2007, Santa Clara, California, USA, October 21-26, 2007, pages 1–10, 2007. \n \n\n\n\n
\n\n\n\n \n \n \"RedefiningPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n \n \n \n \n\n\n\n
\n
@inproceedings{DBLP:conf/itc/CotaKCMAL07,\n  author    = {{\\'{E}}rika F. Cota and\n               Fernanda Gusm{\\~{a}}o de Lima Kastensmidt and\n               Maico Cassel and\n               Paulo Meirelles and\n               Alexandre M. Amory and\n               Marcelo Lubaszewski},\n  title     = {Redefining and testing interconnect faults in Mesh NoCs},\n  booktitle = {2007 {IEEE} International Test Conference, {ITC} 2007, Santa Clara,\n               California, USA, October 21-26, 2007},\n  pages     = {1--10},\n  year      = {2007},\n  crossref  = {DBLP:conf/itc/2007},\n  url       = {http://dx.doi.org/10.1109/TEST.2007.4437574},\n  doi       = {10.1109/TEST.2007.4437574},\n  timestamp = {Tue, 07 Feb 2012 18:07:12 +0100},\n  biburl    = {http://dblp.uni-trier.de/rec/bib/conf/itc/CotaKCMAL07},\n  bibsource = {dblp computer science bibliography, http://dblp.org},\n  keywords  = {noc,testing}\n}\n\n
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\n \n\n \n \n \n \n \n \n DfT for the Reuse of Networks-on-Chip as Test Access Mechanism.\n \n \n \n \n\n\n \n Amory, A. M.; Ferlini, F.; Lubaszewski, M.; and Moraes, F. G.\n\n\n \n\n\n\n In 25th IEEE VLSI Test Symposium (VTS 2007), 6-10 May 2007, Berkeley, California, USA, pages 435–440, 2007. \n \n\n\n\n
\n\n\n\n \n \n \"DfTPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n \n \n \n \n\n\n\n
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@inproceedings{DBLP:conf/vts/AmoryFLM07,\n  author    = {Alexandre M. Amory and\n               Frederico Ferlini and\n               Marcelo Lubaszewski and\n               Fernando  Gehm Moraes},\n  title     = {DfT for the Reuse of Networks-on-Chip as Test Access Mechanism},\n  booktitle = {25th {IEEE} {VLSI} Test Symposium {(VTS} 2007), 6-10 May 2007, Berkeley,\n               California, {USA}},\n  pages     = {435--440},\n  year      = {2007},\n  crossref  = {DBLP:conf/vts/2007},\n  url       = {http://dx.doi.org/10.1109/VTS.2007.26},\n  doi       = {10.1109/VTS.2007.26},\n  timestamp = {Wed, 05 Nov 2014 16:44:47 +0100},\n  biburl    = {http://dblp.uni-trier.de/rec/bib/conf/vts/AmoryFLM07},\n  bibsource = {dblp computer science bibliography, http://dblp.org},\n  keywords  = {noc,testing}\n}\n\n
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\n  \n 2006\n \n \n (2)\n \n \n
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\n \n\n \n \n \n \n \n \n Wrapper Design for the Reuse of Networks-on-Chip as Test Access Mechanism.\n \n \n \n \n\n\n \n Amory, A. M.; Goossens, K.; Marinissen, E. J.; Lubaszewski, M.; and Moraes, F. G.\n\n\n \n\n\n\n In 11th European Test Symposium, ETS 2006, Southhampton, UK, May 21-24, 2006, pages 213–218, 2006. \n \n\n\n\n
\n\n\n\n \n \n \"WrapperPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n \n \n \n \n\n\n\n
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@inproceedings{DBLP:conf/ets/AmoryGMLM06,\n  author    = {Alexandre M. Amory and\n               Kees Goossens and\n               Erik Jan Marinissen and\n               Marcelo Lubaszewski and\n               Fernando Gehm Moraes},\n  title     = {Wrapper Design for the Reuse of Networks-on-Chip as Test Access Mechanism},\n  booktitle = {11th European Test Symposium, {ETS} 2006, Southhampton, UK, May 21-24,\n               2006},\n  pages     = {213--218},\n  year      = {2006},\n  crossref  = {DBLP:conf/ets/2006},\n  url       = {http://dx.doi.org/10.1109/ETS.2006.48},\n  doi       = {10.1109/ETS.2006.48},\n  timestamp = {Tue, 18 Aug 2015 20:06:20 +0200},\n  biburl    = {http://dblp.uni-trier.de/rec/bib/conf/ets/AmoryGMLM06},\n  bibsource = {dblp computer science bibliography, http://dblp.org},\n  keywords  = {noc,testing}\n}\n\n
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\n \n\n \n \n \n \n \n \n .\n \n \n \n \n\n\n \n Amory, A. M.; Oliveira, L. A.; and Moraes, F. G.\n\n\n \n\n\n\n Software-Based Test for Nonprogrammable Cores in Bus-Based System-On-Chip Architectures, pages 165–179. Glesner, M.; Reis, R.; Indrusiak, L.; Mooney, V.; and Eveking, H., editor(s). Springer US, Boston, MA, 2006.\n \n\n\n\n
\n\n\n\n \n \n \"Software-BasedPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n \n \n \n \n\n\n\n
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@Inbook{Amory2006,\nauthor="Amory, Alexandre M.\nand Oliveira, Leandro A.\nand Moraes, Fernando G.",\neditor="Glesner, Manfred\nand Reis, Ricardo\nand Indrusiak, Leandro\nand Mooney, Vincent\nand Eveking, Hans",\ntitle="Software-Based Test for Nonprogrammable Cores in Bus-Based System-On-Chip Architectures",\nbookTitle="VLSI-SOC: From Systems to Chips: IFIP TC 10/ WG 10.5 Twelfth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC 2003), December 1--3, 2003, Darmstadt, Germany",\nyear="2006",\npublisher="Springer US",\naddress="Boston, MA",\npages="165--179",\nisbn="978-0-387-33403-5",\ndoi="10.1007/0-387-33403-3_11",\nurl="http://dx.doi.org/10.1007/0-387-33403-3_11",\nkeywords  = {soc, testing}\n}\n\n\n
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\n  \n 2005\n \n \n (2)\n \n \n
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\n \n\n \n \n \n \n \n \n Test Time Reduction Reusing Multiple Processors in a Network-on-Chip Based Architecture.\n \n \n \n \n\n\n \n Amory, A. M.; Lubaszewski, M.; Moraes, F. G.; and Moreno, E. I.\n\n\n \n\n\n\n In 2005 Design, Automation and Test in Europe Conference and Exposition (DATE 2005), 7-11 March 2005, Munich, Germany, pages 62–63, 2005. \n \n\n\n\n
\n\n\n\n \n \n \"TestPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n \n \n \n \n\n\n\n
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@inproceedings{DBLP:conf/date/AmoryLMM05,\n  author    = {Alexandre M. Amory and\n               Marcelo Lubaszewski and\n               Fernando Gehm Moraes and\n               Edson I. Moreno},\n  title     = {Test Time Reduction Reusing Multiple Processors in a Network-on-Chip\n               Based Architecture},\n  booktitle = {2005 Design, Automation and Test in Europe Conference and Exposition\n               {(DATE} 2005), 7-11 March 2005, Munich, Germany},\n  pages     = {62--63},\n  year      = {2005},\n  crossref  = {DBLP:conf/date/2005},\n  url       = {http://dx.doi.org/10.1109/DATE.2005.304},\n  doi       = {10.1109/DATE.2005.304},\n  timestamp = {Thu, 23 Jun 2016 15:53:29 +0200},\n  biburl    = {http://dblp.uni-trier.de/rec/bib/conf/date/AmoryLMM05},\n  bibsource = {dblp computer science bibliography, http://dblp.org},\n  keywords  = {noc,testing}\n}\n\n
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\n \n\n \n \n \n \n \n \n A scalable test strategy for network-on-chip routers.\n \n \n \n \n\n\n \n Amory, A. M.; Brião, E. W.; Cota, É. F.; Lubaszewski, M.; and Moraes, F. G.\n\n\n \n\n\n\n In Proceedings 2005 IEEE International Test Conference, ITC 2005, Austin, TX, USA, November 8-10, 2005, pages 9, 2005. \n \n\n\n\n
\n\n\n\n \n \n \"APaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n \n \n \n \n\n\n\n
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@inproceedings{DBLP:conf/itc/AmoryBCLM05,\n  author    = {Alexandre M. Amory and\n               Eduardo Wenzel Bri{\\~{a}}o and\n               {\\'{E}}rika F. Cota and\n               Marcelo Lubaszewski and\n               Fernando Gehm Moraes},\n  title     = {A scalable test strategy for network-on-chip routers},\n  booktitle = {Proceedings 2005 {IEEE} International Test Conference, {ITC} 2005,\n               Austin, TX, USA, November 8-10, 2005},\n  pages     = {9},\n  year      = {2005},\n  crossref  = {DBLP:conf/itc/2005},\n  url       = {http://dx.doi.org/10.1109/TEST.2005.1584020},\n  doi       = {10.1109/TEST.2005.1584020},\n  timestamp = {Wed, 26 Aug 2015 09:28:47 +0200},\n  biburl    = {http://dblp.uni-trier.de/rec/bib/conf/itc/AmoryBCLM05},\n  bibsource = {dblp computer science bibliography, http://dblp.org},\n  keywords  = {noc,testing}\n}\n\n
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\n  \n 2004\n \n \n (1)\n \n \n
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\n \n\n \n \n \n \n \n \n Reducing test time with processor reuse in network-on-chip based systems.\n \n \n \n \n\n\n \n Amory, A. M.; Cota, É. F.; Lubaszewski, M.; and Moraes, F. G.\n\n\n \n\n\n\n In Proceedings of the 17th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2004, Pernambuco, Brazil, September 7-11, 2004, pages 111–116, 2004. \n \n\n\n\n
\n\n\n\n \n \n \"ReducingPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n \n \n \n \n\n\n\n
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@inproceedings{DBLP:conf/sbcci/AmoryCLM04,\n  author    = {Alexandre M. Amory and\n               {\\'{E}}rika F. Cota and\n               Marcelo Lubaszewski and\n               Fernando Gehm Moraes},\n  title     = {Reducing test time with processor reuse in network-on-chip based systems},\n  booktitle = {Proceedings of the 17th Annual Symposium on Integrated Circuits and\n               Systems Design, {SBCCI} 2004, Pernambuco, Brazil, September 7-11,\n               2004},\n  pages     = {111--116},\n  year      = {2004},\n  crossref  = {DBLP:conf/sbcci/2004},\n  url       = {http://doi.acm.org/10.1145/1016568.1016602},\n  doi       = {10.1145/1016568.1016602},\n  timestamp = {Mon, 04 Jun 2007 15:14:14 +0200},\n  biburl    = {http://dblp.uni-trier.de/rec/bib/conf/sbcci/AmoryCLM04},\n  bibsource = {dblp computer science bibliography, http://dblp.org},\n  keywords  = {noc,testing}\n}\n\n
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\n  \n 2003\n \n \n (1)\n \n \n
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\n \n\n \n \n \n \n \n Software-Based Test for Non-Programmable Cores in Bus-Based System-on-Chip Architectures.\n \n \n \n\n\n \n Amory, A. M.; Oliveira, L. A.; and Moraes, F. G.\n\n\n \n\n\n\n In IFIP VLSI-SoC 2003, IFIP WG 10.5 International Conference on Very Large Scale Integration of System-on-Chip, Darmstadt, Germany, 1-3 December 2003, pages 174–179, 2003. \n \n\n\n\n
\n\n\n\n \n\n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n \n \n \n \n\n\n\n
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@inproceedings{DBLP:conf/vlsi/AmoryOM03,\n  author    = {Alexandre M. Amory and\n               Leandro A. Oliveira and\n               Fernando Gehm Moraes},\n  title     = {Software-Based Test for Non-Programmable Cores in Bus-Based System-on-Chip\n               Architectures},\n  booktitle = {{IFIP} VLSI-SoC 2003, {IFIP} {WG} 10.5 International Conference on\n               Very Large Scale Integration of System-on-Chip, Darmstadt, Germany,\n               1-3 December 2003},\n  pages     = {174--179},\n  year      = {2003},\n  crossref  = {DBLP:conf/vlsi/2003soc},\n  timestamp = {Thu, 07 Oct 2004 09:29:26 +0200},\n  biburl    = {http://dblp.uni-trier.de/rec/bib/conf/vlsi/AmoryOM03},\n  bibsource = {dblp computer science bibliography, http://dblp.org},\n  keywords  = {soc, testing}\n}\n\n
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\n  \n 2002\n \n \n (1)\n \n \n
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\n \n\n \n \n \n \n \n \n Prototyping of embedded digital systems from SDL language: a case study.\n \n \n \n \n\n\n \n Marcon, C. A. M.; Hessel, F.; Amory, A. M.; Ries, L. H. L.; Moraes, F. G.; and Calazans, N. L. V.\n\n\n \n\n\n\n In Seventh IEEE International High-Level Design Validation and Test Workshop 2002, Cannes, France, October 27-29, 2002, pages 133–138, 2002. \n \n\n\n\n
\n\n\n\n \n \n \"PrototypingPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/hldvt/MarconHARMC02,\n  author    = {C{\\'{e}}sar A. M. Marcon and\n               Fabiano Hessel and\n               Alexandre M. Amory and\n               Luis H. L. Ries and\n               Fernando Gehm Moraes and\n               Ney Laert Vilar Calazans},\n  title     = {Prototyping of embedded digital systems from {SDL} language: a case\n               study},\n  booktitle = {Seventh {IEEE} International High-Level Design Validation and Test\n               Workshop 2002, Cannes, France, October 27-29, 2002},\n  pages     = {133--138},\n  year      = {2002},\n  crossref  = {DBLP:conf/hldvt/2002},\n  url       = {http://dx.doi.org/10.1109/HLDVT.2002.1224442},\n  doi       = {10.1109/HLDVT.2002.1224442},\n  timestamp = {Tue, 12 May 2015 17:11:46 +0200},\n  biburl    = {http://dblp.uni-trier.de/rec/bib/conf/hldvt/MarconHARMC02},\n  bibsource = {dblp computer science bibliography, http://dblp.org}\n}\n\n
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\n  \n 2000\n \n \n (2)\n \n \n
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\n \n\n \n \n \n \n \n \n Transient-fault tolerant VHDL descriptions: a case-study for area overhead analysis.\n \n \n \n \n\n\n \n Vargas, F.; and Amory, A. M.\n\n\n \n\n\n\n In 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, pages 417–422, 2000. \n \n\n\n\n
\n\n\n\n \n \n \"Transient-faultPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n \n \n\n\n\n
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@inproceedings{DBLP:conf/ats/VargasA00,\n  author    = {Fabian Vargas and\n               Alexandre M. Amory},\n  title     = {Transient-fault tolerant {VHDL} descriptions: a case-study for area\n               overhead analysis},\n  booktitle = {9th Asian Test Symposium {(ATS} 2000), 4-6 December 2000, Taipei,\n               Taiwan},\n  pages     = {417--422},\n  year      = {2000},\n  crossref  = {DBLP:conf/ats/2000},\n  url       = {http://dx.doi.org/10.1109/ATS.2000.893659},\n  doi       = {10.1109/ATS.2000.893659},\n  timestamp = {Thu, 14 Jan 2016 10:13:57 +0100},\n  biburl    = {http://dblp.uni-trier.de/rec/bib/conf/ats/VargasA00},\n  bibsource = {dblp computer science bibliography, http://dblp.org},\n  keywords  = {fault tolerance}\n}\n\n
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\n \n\n \n \n \n \n \n \n Estimating Circuit Fault-Tolerance by Means of Transient-Fault Injection in VHDL.\n \n \n \n \n\n\n \n Vargas, F.; Amory, A. M.; and Velazco, R.\n\n\n \n\n\n\n In 6th IEEE International On-Line Testing Workshop (IOLTW 2000), 3-5 July 2000, Palma de Mallorca, Spain, pages 67–72, 2000. \n \n\n\n\n
\n\n\n\n \n \n \"EstimatingPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n \n \n\n\n\n
\n
@inproceedings{DBLP:conf/iolts/VargasAV00,\n  author    = {Fabian Vargas and\n               Alexandre M. Amory and\n               Raoul Velazco},\n  title     = {Estimating Circuit Fault-Tolerance by Means of Transient-Fault Injection\n               in {VHDL}},\n  booktitle = {6th {IEEE} International On-Line Testing Workshop {(IOLTW} 2000),\n               3-5 July 2000, Palma de Mallorca, Spain},\n  pages     = {67--72},\n  year      = {2000},\n  crossref  = {DBLP:conf/iolts/2000},\n  url       = {http://dx.doi.org/10.1109/OLT.2000.856614},\n  doi       = {10.1109/OLT.2000.856614},\n  timestamp = {Thu, 19 May 2016 09:23:39 +0200},\n  biburl    = {http://dblp.uni-trier.de/rec/bib/conf/iolts/VargasAV00},\n  bibsource = {dblp computer science bibliography, http://dblp.org},\n  keywords  = {fault tolerance}\n}\n
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