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\n \n 2020\n \n \n (3)\n \n \n

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\n \n\n \n \n \n \n \n \n Um simulador robótico para inundações considerando distúrbios ambientais.\n \n \n \n \n\n\n \n Paravisi, M.\n\n\n \n\n\n\n Ph.D. Thesis, Escola Politécnica, Pontifícia Universidade Católica do Rio Grande do Sul (PUCRS), Porto Alegre, Brasil, 2020.\n \n\n\n\n
\n\n\n\n \n \n $\"Um$ link\n \n \n\n \n\n \n link\n \n \n\n bibtex\n \n\n \n \n \n abstract \n \n\n \n\n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n \n \n \n\n\n\n

\n

@phdthesis{paravisi2020,\n    title    = {{Um simulador robótico para inundações considerando distúrbios ambientais}},\n    school   = {Escola Politécnica, {Pontifícia Universidade Católica do Rio Grande do Sul (PUCRS)}},\n    author   = {Marcelo Paravisi},\n    year     = {2020},\n    address  = {Porto Alegre, Brasil},\n    keywords = {LSA, robotics, USV, advised},\n    xxxurl_link = {http://tede2.pucrs.br/tede2/handle/tede/9390},\n    url_link = {http://tede2.pucrs.br/tede2/bitstream/tede/9390/2/MARCELO_PARAVISI_TES.pdf},\n    abstract   = {Extreme weather events cause most disasters around the world, and in Brazil, the main kind of such event are landslides and rains. Rescue Robots have become important allies of rescue teams to assist in carrying out tasks with a high degree of danger. However, the development of new robotic platforms capable of handling such unpredictable environments demands that the roboticist evaluate the robot platform under similar conditions of the real world. Considering that there are few test sites for disasters, robotic simulators for natural disasters present themselves as an essential tool to reduce research and development costs, avoiding equipment losses, and identifying defects and limitations in prototypes. In this sense, the present document proposes a robotic simulation environment for natural disasters that reproduces the environmental disturbances present in flooding scenarios. Thus, this thesis presents a protocol to reproduce real scenarios and their disturbances in the virtual environment, it also describes a protocol and experiments to validate the movement of virtual USVs. Finally, case studies demonstrate the impact of disturbances on the activities performed by the USVs. }\n}\n\n\n

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\n \n\n \n \n \n \n \n \n A COLREGS-compliant collision avoidance system for unmanned surface vehicles.\n \n \n \n \n\n\n \n Jurak, D. A.\n\n\n \n\n\n\n Master's thesis, Escola Politécnica, Pontifícia Universidade Católica do Rio Grande do Sul (PUCRS), Porto Alegre, Brasil, 2020.\n \n\n\n\n
\n\n\n\n \n \n $\"A$ link\n \n \n\n \n\n \n link\n \n \n\n bibtex\n \n\n \n \n \n abstract \n \n\n \n\n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n \n \n \n\n\n\n

\n

@mastersthesis{darlan2020,\n  author       = {Jurak, Darlan Alves}, \n  title        = {{A COLREGS-compliant collision avoidance system for unmanned surface vehicles}},\n  school       = {Escola Politécnica, {Pontifícia Universidade Católica do Rio Grande do Sul (PUCRS)}},\n  year         = 2020,\n  address      = {Porto Alegre, Brasil},\n  url_link     = {http://tede2.pucrs.br/tede2/handle/tede/9471},\n  xxxurl_link  = {http://tede2.pucrs.br/tede2/bitstream/tede/9471/2/DARLAN%20ALVES%20JURAK_DIS.pdf},\n  keywords     = {LSA, robotics, USV, advised},\n  abstract     = {Unmanned surface vehicles (USVs) are a category of aquatic robots that act unmanned on the water surface, performing autonomous behavior or being remotely controlled. In recent decades, several studies have been carried out to make USVs autonomous. The main challenges are related to collision avoidance, accurate navigation on the high seas, and compliance with international maritime rules, such as the Convention on the International Regulations for Preventing Collisions at Sea (COLREGS). Current applications of USVs include monitoring the environment, exploiting ocean resources such as oil and gas, port and coastal surveillance for military purposes, transport, and scientific research. COLREGS determines rules that must be followed by sailors to avoid collisions in possible collision scenarios, such as crossing, head-on, and overtaking. Currently, direct collisions between vessels represent 60% of accidents at sea, and the violation of COLREGS causes 56% of collisions. Therefore, USVs must comply with COLREGS. In this master’s thesis, we present the system we developed to guide USVs on autonomous missions while following the COLREGS. The main guidance module of our system is a path planner that follows the COLREGS. We adapted the Artificial Terrain Cost method, presented by Agrawal [3] et al., to our solution, blocking locations in the search space that are not compliant with COLREGS, through the creation of virtual obstacles. We integrated our system to a differential boat available in the USV_sim simulator, a simulator for USVs, capable of generating realistic disturbances, such as wind and water current. To evaluate the proposed system, we measure the computational time, the maximum sustained wind, and the minimum distance maintained when encountering another vessel in the scenarios of head-on, crossing from the left, crossing from the right, and overtaking encounters.},\n}\n\n\n

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\n \n\n \n \n \n \n \n \n ORCA : a self-adaptive, multiprocessor system-on-chip platform.\n \n \n \n \n\n\n \n Domingues, A.\n\n\n \n\n\n\n Master's thesis, Escola Politécnica, Pontifícia Universidade Católica do Rio Grande do Sul (PUCRS), Porto Alegre, Brasil, 2020.\n \n\n\n\n
\n\n\n\n \n \n $\"ORCA$ link\n \n \n\n \n\n \n link\n \n \n\n bibtex\n \n\n \n \n \n abstract \n \n\n \n\n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n \n\n\n\n

\n

@mastersthesis{domingues2020,\n  author       = {Domingues, Anderson}, \n  title        = {{ORCA : a self-adaptive, multiprocessor system-on-chip platform}},\n  school       = {Escola Politécnica, {Pontifícia Universidade Católica do Rio Grande do Sul (PUCRS)}},\n  year         = 2020,\n  address      = {Porto Alegre, Brasil},\n  url_link     = {http://tede2.pucrs.br/tede2/handle/tede/9344},\n  xxxurl_link  = {http://tede2.pucrs.br/tede2/bitstream/tede/9344/2/ANDERSON%20ROBERTO%20PINHEIRO%20DOMINGUES_DIS.pdf},\n  keywords     = {GAPH, MPSoC, advised},\n  abstract     = {The complex organization of multiprocessor systems-on-chips (MPSoCs) requires the smart management of systems’ resources during runtime and the capability of systems to optimize their operation under abnormal situations such as temporary hardware unavailability. One of the approaches for resource management in MPSoCs is self-adaptation, which augment these systems with sensors, actuators, and decision logic components. In this thesis, we propose ORCA, a development platform to aid in designing self-adaptive systems. The platform provides abstractions to deal with self-adaptation complexity, based on previous work in the field, including a configurable hardware architecture, operating system, software libraries, and simulation environment. The hardware architecture consists of open-source hardware modules and implements a many-core approach based on a RISCV compatible processor core. That architecture can be emulated and simulated through ORCA-SIM, a simulation tool, also part of this work. The tool uses discrete-event simulation to speed up the simulation process, based on the URSA application programming interface, also part of this work. Software components are also discussed, including a library for hardware monitoring and energy consumption estimation, and a library for designing publish-subscribe systems. We present a compilation of results achieved in previous work and new experiments to cover the validation of the entire platform. For the latter, we focus the discussion on the design of a task reallocation mechanism based on self-adaptive components.},\n}\n\n\n

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\n\n\n\n\n\n

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\n \n 2019\n \n \n (1)\n \n \n

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\n \n \n

\n \n\n \n \n \n \n \n \n Support to Run-Time Adaptation by a Publish-Subscribe Based Middleware for MPSOC Architectures.\n \n \n \n \n\n\n \n Hamerski, J.\n\n\n \n\n\n\n Ph.D. Thesis, Escola Politécnica, Pontifícia Universidade Católica do Rio Grande do Sul (PUCRS), Porto Alegre, Brasil, 2019.\n \n\n\n\n
\n\n\n\n \n \n $\"Support$ link\n \n \n\n \n\n \n link\n \n \n\n bibtex\n \n\n \n \n \n abstract \n \n\n \n\n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n \n\n\n\n

\n

@phdthesis{hamerski2019,\n    title    = {{Support to Run-Time Adaptation by a Publish-Subscribe Based Middleware for MPSOC Architectures}},\n    school   = {Escola Politécnica, {Pontifícia Universidade Católica do Rio Grande do Sul (PUCRS)}},\n    author   = {Hamerski, Jean},\n    year     = {2019},\n    address  = {Porto Alegre, Brasil},\n    keywords = {GAPH, mpsoc, software},\n    xxxurl_link = {http://hdl.handle.net/10923/15862},\n    url_link = {http://repositorio.pucrs.br/dspace/bitstream/10923/15862/1/000495763-Texto%2bCompleto-0.pdf},\n    abstract   = {Embedded applications have been migrating from single processor-based systems to intensive data communication requiring multi-processing systems. The performance demanded by applications motivate the use of Multi-Processor System-on-Chip (MPSoC) architectures. software over a complex, distributed and possibly heterogeneous hardware platform.  Run-time changes in the quality of service provided by the MPSoC platform to the applications motivate the implementation of self-adaptive MPSoC platforms. Self-adaptive MPSoC platforms employ systems composed of sensor-actuator-rich architectures that observe the changes in the execution environment and adapt the system dynamically balancing the multiple objectives across multiple architecture levels. These self-adaptive systems require communication/programming models well suited to the distributed characteristic of the environment in order to coordinate communication between the elements that compose it. This Thesis investigates current programming/communication models on MPSoC and other correlated domains regarding the coupling between the communicating elements and the adjacent hardware and software infrastructure. The hypothesis raised is that it is necessary to use a model that, besides abstracting the communication complexity, also provides a more flexible coupling between the communicating elements of the self-adaptive system. Additionally, we argue that the current approaches used to incorporate self-adaptive systems in MPSoC platforms follow a non-systematic development methodology, which impacts the quality of software related to code reuse and maintainability. Therefore, this Thesis proposes to apply the publish-subscribe model in a middleware-based development approach to perform the communication employed between the elements of a self-adaptive MPSoC platform and to improve software quality of self-adaptive systems while minimizing undesired impacts of the proposed approach on the system. The Thesis is supported through a case study where we implement a self-adaptive system following the proposed approach and compare the results with a baseline self-adaptive system according to performance, energy and software quality metrics. The results show that the proposed model employed on a middleware based development approach has improved the software quality of the self-adaptive system  by 33\\% to 47.8\\%, depending on the metrics evaluated, with a reduced overhead regarding metrics of performance (4.5\\%) and energy spent (5.9\\%). We also show that the requirements for middleware software are suitable for MPSoC platforms with memory usage constraints. }\n}\n\n

\n

\n\n\n

\n Embedded applications have been migrating from single processor-based systems to intensive data communication requiring multi-processing systems. The performance demanded by applications motivate the use of Multi-Processor System-on-Chip (MPSoC) architectures. software over a complex, distributed and possibly heterogeneous hardware platform. Run-time changes in the quality of service provided by the MPSoC platform to the applications motivate the implementation of self-adaptive MPSoC platforms. Self-adaptive MPSoC platforms employ systems composed of sensor-actuator-rich architectures that observe the changes in the execution environment and adapt the system dynamically balancing the multiple objectives across multiple architecture levels. These self-adaptive systems require communication/programming models well suited to the distributed characteristic of the environment in order to coordinate communication between the elements that compose it. This Thesis investigates current programming/communication models on MPSoC and other correlated domains regarding the coupling between the communicating elements and the adjacent hardware and software infrastructure. The hypothesis raised is that it is necessary to use a model that, besides abstracting the communication complexity, also provides a more flexible coupling between the communicating elements of the self-adaptive system. Additionally, we argue that the current approaches used to incorporate self-adaptive systems in MPSoC platforms follow a non-systematic development methodology, which impacts the quality of software related to code reuse and maintainability. Therefore, this Thesis proposes to apply the publish-subscribe model in a middleware-based development approach to perform the communication employed between the elements of a self-adaptive MPSoC platform and to improve software quality of self-adaptive systems while minimizing undesired impacts of the proposed approach on the system. The Thesis is supported through a case study where we implement a self-adaptive system following the proposed approach and compare the results with a baseline self-adaptive system according to performance, energy and software quality metrics. The results show that the proposed model employed on a middleware based development approach has improved the software quality of the self-adaptive system by 33% to 47.8%, depending on the metrics evaluated, with a reduced overhead regarding metrics of performance (4.5%) and energy spent (5.9%). We also show that the requirements for middleware software are suitable for MPSoC platforms with memory usage constraints. \n

\n\n\n

\n\n\n\n\n\n

\n

\n \n 2018\n \n \n (3)\n \n \n

\n

\n \n \n

\n \n\n \n \n \n \n \n \n More than a timing resilient template: a case study on reliability-oriented improvements on Blade.\n \n \n \n \n\n\n \n Kuentzer, F.\n\n\n \n\n\n\n Ph.D. Thesis, Escola Politécnica, Pontifícia Universidade Católica do Rio Grande do Sul (PUCRS), Porto Alegre, Brasil, 2018.\n \n\n\n\n
\n\n\n\n \n \n $\"More$ link\n \n \n\n \n\n \n link\n \n \n\n bibtex\n \n\n \n \n \n abstract \n \n\n \n\n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n \n \n \n \n \n\n\n\n

\n

@phdthesis{kuentzer2018,\n    title    = {{More than a timing resilient template: a case study on reliability-oriented improvements on Blade}},\n    school   = {Escola Politécnica, {Pontifícia Universidade Católica do Rio Grande do Sul (PUCRS)}},\n    author   = {Kuentzer, Felipe},\n    year     = {2018},\n    address  = {Porto Alegre, Brasil},\n    keywords = {GAPH, design for testability, asynchronous, blade, advised},\n    xxxurl_link = {http://tede2.pucrs.br/tede2/handle/tede/8093},\n    url_link = {http://tede2.pucrs.br/tede2/bitstream/tede/8093/2/FELIPE_AUGUSTO_KUENTZER_TES.pdf},\n    abstract   = {As the VLSI design moves to ultra-deep-submicron technologies timing margins added due variability in the manufacturing process, operation temperature and supply voltage become a significant part of the clock period in traditional synchronous circuits. Timing resilient architectures emerged as a promising solution to alleviate these worst-case timing margins, improving system performance while reducing energy consumption. These architectures embed additional circuits for detecting and recovering from timing violations that may arise when designing the circuit with reduced time margins. On the other hand, asynchronous systems also present potential to improve energy efficiency and performance due to the absence of a global clock. Moreover, asynchronous circuits are known to be robust to process, voltage and temperature variations. Blade is an asynchronous timing resilient template, that leverages the advantages of both asynchronous and timing resilient techniques. However, Blade still presents challenges regarding its testability, which hinders its commercial or large-scale application. Although the design for testability with scan chains is widely applied in the industry, the high silicon costs associated with its use in Blade can be prohibitive. On the other hand, asynchronous circuits can present advantages for functional testing, and the timing resilient characteristic provides constant feedback during the circuit normal operation, which can be applied for concurrent testing. In this Thesis, Blade's testability is evaluated with a different perspective, where the circuit implemented with Blade presents reliability properties that can be explored for stuck-at and delay faults testing. Initially, a fault classification method that relates behavioral patterns with structural faults inside the error detection logic and a new test-driven implementation of this detection module are proposed. The control part is analyzed for internal faults, and a new design is proposed, where the test coverage is improved and the circuit can be further optimized by the design flow. An original method for time measuring delay lines is also addressed. Finally, delay fault testing of critical paths in the data path is explored as a natural consequence of a circuit implemented with Blade, where the constant monitoring for detecting timing violations provide the necessary feedback for online detecting of these delay faults. The integration of all the contributions provides a satisfactory fault coverage for an area overload that, for the circuits evaluated in this thesis, it can vary from 4.24% to 6.87%, while the scan approach for the same circuits vary from 50.19% to 112.70%, respectively. The contributions of this Thesis demonstrated that with a few improvements in the Blade architecture it is possible to expand its reliability beyond a timing resilient system to delay violations in the data path, but also an advance for fault testing (including online faults) of the entire circuit, yield, and aging.}\n}\n\n

\n

\n\n\n

\n As the VLSI design moves to ultra-deep-submicron technologies timing margins added due variability in the manufacturing process, operation temperature and supply voltage become a significant part of the clock period in traditional synchronous circuits. Timing resilient architectures emerged as a promising solution to alleviate these worst-case timing margins, improving system performance while reducing energy consumption. These architectures embed additional circuits for detecting and recovering from timing violations that may arise when designing the circuit with reduced time margins. On the other hand, asynchronous systems also present potential to improve energy efficiency and performance due to the absence of a global clock. Moreover, asynchronous circuits are known to be robust to process, voltage and temperature variations. Blade is an asynchronous timing resilient template, that leverages the advantages of both asynchronous and timing resilient techniques. However, Blade still presents challenges regarding its testability, which hinders its commercial or large-scale application. Although the design for testability with scan chains is widely applied in the industry, the high silicon costs associated with its use in Blade can be prohibitive. On the other hand, asynchronous circuits can present advantages for functional testing, and the timing resilient characteristic provides constant feedback during the circuit normal operation, which can be applied for concurrent testing. In this Thesis, Blade's testability is evaluated with a different perspective, where the circuit implemented with Blade presents reliability properties that can be explored for stuck-at and delay faults testing. Initially, a fault classification method that relates behavioral patterns with structural faults inside the error detection logic and a new test-driven implementation of this detection module are proposed. The control part is analyzed for internal faults, and a new design is proposed, where the test coverage is improved and the circuit can be further optimized by the design flow. An original method for time measuring delay lines is also addressed. Finally, delay fault testing of critical paths in the data path is explored as a natural consequence of a circuit implemented with Blade, where the constant monitoring for detecting timing violations provide the necessary feedback for online detecting of these delay faults. The integration of all the contributions provides a satisfactory fault coverage for an area overload that, for the circuits evaluated in this thesis, it can vary from 4.24% to 6.87%, while the scan approach for the same circuits vary from 50.19% to 112.70%, respectively. The contributions of this Thesis demonstrated that with a few improvements in the Blade architecture it is possible to expand its reliability beyond a timing resilient system to delay violations in the data path, but also an advance for fault testing (including online faults) of the entire circuit, yield, and aging.\n

\n\n\n

\n \n\n \n \n \n \n \n \n Testing The Blade Resilient Asynchronous Template: A Structural Approach.\n \n \n \n \n\n\n \n Juracy, L. R.\n\n\n \n\n\n\n Master's thesis, Escola Politécnica, Pontifícia Universidade Católica do Rio Grande do Sul (PUCRS), Porto Alegre, Brasil, 2018.\n Advisor: Alexandre de Morais Amory; Co-advisor: Matheus Trevisan Moreira\n\n\n\n
\n\n\n\n \n \n $\"Testing$ link\n \n \n\n \n\n \n link\n \n \n\n bibtex\n \n\n \n \n \n abstract \n \n\n \n \n \n 1 download\n \n \n\n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n \n \n \n \n \n\n\n\n

\n

@mastersthesis{juracy2018,\n  author       = {Juracy, Leonardo Rezende}, \n  title        = {{Testing The Blade Resilient Asynchronous Template: A Structural Approach}},\n  school       = {Escola Politécnica, {Pontifícia Universidade Católica do Rio Grande do Sul (PUCRS)}},\n  year         = 2018,\n  address      = {Porto Alegre, Brasil},\n  url_link     = {http://tede2.pucrs.br/tede2/bitstream/tede/8167/2/LEONARDO%20REZENDE%20JURACY_DIS.pdf},\n  keywords     = {GAPH, design for testability, asynchronous, blade, advised},\n  abstract     = {Nowadays, the synchronous circuits design approach is the most used design method since it is highly automated by commercial computer-aided design (CAD) tools. Synchronous designs incorporate timing margins to ensure the correct behavior under the worst-case scenario of process and environmental variations, limiting its clock period optimization and increasing power consumption. On one hand, asynchronous designs present some potential advantages when compared to synchronous ones, such as less power consumption and more data throughput, but they may also suffer with the process and environmental variations. On the other hand, resilient circuits techniques are an alternative to keep the design working in presence of effects of variability. Thus, Blade template has been proposed, combining  the advantages of both asynchronous and resilient circuits. The Blade template employs latches in its implementation and supports average-case circuit performance. Independently of the design style (synchronous or asynchronous), during the fabrication process of integrated circuits, some imperfections can occur, causing defects that reduce the fabrication yield. These defective ICs can present a faulty behavior, which produces an output different from the expected, and it must be identified before the circuit commercialization. Test methodologies help to find and diagnose this faulty behavior. Design for Testability (DfT) increases circuit testability by adding a degree of controllability and observability through different test techniques. Scan design is a DfT technique that provides for an external test equipment the access to the internal memory elements of a circuit, allowing test pattern insertion and response comparison. The goal of this work is to propose a fully integrated and automated structural DfT approach using commercial EDA tools and to propose a series of design methods to address the challenges related to testing asynchronous and resilient designs, with focus on Blade template. The proposed DfT flow is evaluated with a criptocore module and a microprocessor. The obtained results for the criptocore module show a fault coverage of 98.17% for stuck-at fault model and 89.37% for path-delay fault model, with an area overhead of 112.16%. The obtained results for the microprocessor show a fault coverage of 96.04% for stuck-at fault model and 99.00% for path-delay fault model, with an area overhead of 50.57%.},\n  note   = {Advisor: Alexandre de Morais Amory; Co-advisor: Matheus Trevisan Moreira}\n}\n\n

\n

\n\n\n

\n Nowadays, the synchronous circuits design approach is the most used design method since it is highly automated by commercial computer-aided design (CAD) tools. Synchronous designs incorporate timing margins to ensure the correct behavior under the worst-case scenario of process and environmental variations, limiting its clock period optimization and increasing power consumption. On one hand, asynchronous designs present some potential advantages when compared to synchronous ones, such as less power consumption and more data throughput, but they may also suffer with the process and environmental variations. On the other hand, resilient circuits techniques are an alternative to keep the design working in presence of effects of variability. Thus, Blade template has been proposed, combining the advantages of both asynchronous and resilient circuits. The Blade template employs latches in its implementation and supports average-case circuit performance. Independently of the design style (synchronous or asynchronous), during the fabrication process of integrated circuits, some imperfections can occur, causing defects that reduce the fabrication yield. These defective ICs can present a faulty behavior, which produces an output different from the expected, and it must be identified before the circuit commercialization. Test methodologies help to find and diagnose this faulty behavior. Design for Testability (DfT) increases circuit testability by adding a degree of controllability and observability through different test techniques. Scan design is a DfT technique that provides for an external test equipment the access to the internal memory elements of a circuit, allowing test pattern insertion and response comparison. The goal of this work is to propose a fully integrated and automated structural DfT approach using commercial EDA tools and to propose a series of design methods to address the challenges related to testing asynchronous and resilient designs, with focus on Blade template. The proposed DfT flow is evaluated with a criptocore module and a microprocessor. The obtained results for the criptocore module show a fault coverage of 98.17% for stuck-at fault model and 89.37% for path-delay fault model, with an area overhead of 112.16%. The obtained results for the microprocessor show a fault coverage of 96.04% for stuck-at fault model and 99.00% for path-delay fault model, with an area overhead of 50.57%.\n

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\n \n\n \n \n \n \n \n \n Outdoor Localization System for Mobile Robots Based on Radio-Frequency Signal Strength.\n \n \n \n \n\n\n \n Maidana, R. G.\n\n\n \n\n\n\n Master's thesis, Escola Politécnica, Pontifícia Universidade Católica do Rio Grande do Sul (PUCRS), Porto Alegre, Brasil, 2018.\n Advisor: Alexandre de Morais Amory; Co-advisor: Aurelio Tergolina Salton\n\n\n\n
\n\n\n\n \n \n $\"Outdoor$ link\n \n \n\n \n\n \n link\n \n \n\n bibtex\n \n\n \n \n \n abstract \n \n\n \n\n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n \n \n \n\n\n\n

\n

@mastersthesis{renan2018,\n  author       = {Maidana, Renan Guedes}, \n  title        = {{Outdoor Localization System for Mobile Robots Based on Radio-Frequency Signal Strength}},\n  school       = {Escola Politécnica, {Pontifícia Universidade Católica do Rio Grande do Sul (PUCRS)}},\n  year         = 2018,\n  address      = {Porto Alegre, Brasil},\n  url_link     = {http://tede2.pucrs.br/tede2/bitstream/tede/8140/2/RENAN_GUEDES_MAIDANA_DIS.pdf},\n  keywords     = {LSA, robotics, localization, advised},\n  abstract     = {In the field of Mobile Robotics, the localization problem consists on determining a robot's position and orientation in a three-dimensional space through sensor information. The most common solution to this problem is to employ a Global Positioning System receiver, also known as GPS, which reports absolute position in relation to an Earth-centered fixed coordinate system. However, GPS signals are greatly affected by atmospheric conditions and line-of-sight occlusion, sometimes providing very poor position estimates, if any at all. Inspired by these problems, this project proposes a localization system to be used by a robot in an uncontrolled outdoor environment, where GPS measurements are poor or unavailable. As common sensors provide inaccurate position estimates due to environmental factors (e.g. rough terrain), we propose the use of Radio-Frequency receiver-transmitter pairs, in which the Received Signal Strength Indicator is used for estimating the distances between receiver and transmitter, which in turn are used for positioning. This measurement has the advantage of being independent from lighting conditions or the state of the terrain, factors which affect other localization methods such as visual or wheel odometry. A mean positioning error of 0.41 m was achieved by fusing wheel odometry, angular velocity from a gyroscope and the received signal strength, in an Augmented Extended Kalman Filter algorithm, with an improvement of 82.66\\% relative to the mean error of 2.38 m obtained with a common GPS sensor.},\n  note   = {Advisor: Alexandre de Morais Amory; Co-advisor: Aurelio Tergolina Salton}\n}\n\n

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\n \n 2017\n \n \n (2)\n \n \n

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\n \n\n \n \n \n \n \n \n Ferramenta Computacional Para Predição de Alagamento na Região Hidrográfica da Redenção.\n \n \n \n \n\n\n \n Martins, V. M.\n\n\n \n\n\n\n Technical Report 2017.\n Advisor: Alexandre de Morais Amory, Co-Advisor: Regis Alexandre Lahm\n\n\n\n
\n\n\n\n \n \n $\"Ferramenta$ Paper\n \n \n\n \n\n \n link\n \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n \n\n\n\n

\n

@TECHREPORT{vagner-pep-2017,\n  author       = {Vagner Macedo Martins}, \n  title        = {Ferramenta Computacional Para Predição de Alagamento na Região Hidrográfica da Redenção},\n  school       = {Mestrado em Ciência da Computação - PUCRS},\n  year         = 2017,\n  type         = {Masters Research Proposal},\n  keywords     = {LSA, flooding, advised},\n  note         = {Advisor: Alexandre de Morais Amory, Co-Advisor: Regis Alexandre Lahm}, \n  url          = {https://lsa-pucrs.github.io/documentation/master_thesis/pep-doc-vagner-martins-2017.pdf}\n}\n\n

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\n \n\n \n \n \n \n \n \n GoDonnie : definição e avaliação de uma linguagem de programação para comandar robô por programadores iniciantes com deficiência visual.\n \n \n \n \n\n\n \n Oliveira, J. D.\n\n\n \n\n\n\n Master's thesis, Escola Politécnica, Pontifícia Universidade Católica do Rio Grande do Sul (PUCRS), Porto Alegre, Brasil, 2017.\n Advisor: Márcia de Borba Campos; Co-advisor: Alexandre de Morais Amory\n\n\n\n
\n\n\n\n \n \n $\"GoDonnie$ link\n \n \n\n \n\n \n link\n \n \n\n bibtex\n \n\n \n \n \n abstract \n \n\n \n\n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n \n \n \n\n\n\n

\n

@mastersthesis{juliana2017,\n  author       = {Oliveira, Juliana Damasio}, \n  title        = {{GoDonnie : definição e avaliação de uma linguagem de programação para comandar robô por programadores iniciantes com deficiência visual}},\n  school       = {Escola Politécnica, {Pontifícia Universidade Católica do Rio Grande do Sul (PUCRS)}},\n  year         = 2017,\n  address      = {Porto Alegre, Brasil},\n  url_link     = {http://tede2.pucrs.br/tede2/bitstream/tede/7747/4/Juliana_Damasio_Oliveira_dis.pdf},\n  keywords     = {LSA, robotics, assistive technology, advised},\n  abstract     = {The general objective of this work was to define and evaluate a programming language to stimulate orientation and mobility (O&M) skills by people with visual impairment (VI). It is believed that by using a programming language to guide a robot in a virtual setting, the person with VI can better understand O&M skills. In this sense, it was definedthe programming language, which was called GoDonnie, and was based on the Logo language. A GoDonnie is run in a programming environment called Donnie, which provides soundbacks about running the robot. In addition, it has a 2D graphic simulator with a virtual robot, in which one can visualize the execution of the language commands, that is, the virtual robot sedeslocando in the scenario. This simulator allows the use by people with low vision, as well as serve as a resource to better visualize how the person who is blind is interacting with the robot in the environment. A GoDonnie has been evaluated to verify its usability. Evaluations were carried out which included visually impaired people and teachers of programming, without visual impairment. The results pointed out that GoDonnie has good usability, as well as helps the evelopment of O&M.},\n  note   = {Advisor: Márcia de Borba Campos; Co-advisor: Alexandre de Morais Amory}\n}\n\n

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\n \n 2016\n \n \n (1)\n \n \n

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\n \n\n \n \n \n \n \n \n Projeto de uma Célula Latch Testável.\n \n \n \n \n\n\n \n Juracy, L. R.\n\n\n \n\n\n\n Technical Report Faculdade de Informática, Pontifícia Universidade Católica do Rio Grande do Sul (PUCRS), 2016.\n Advisor: Alexandre de Morais Amory, Co-Advisor: Matheus Trevisan Moreira\n\n\n\n
\n\n\n\n \n \n $\"Projeto$ link\n \n \n\n \n\n \n link\n \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n \n \n \n\n\n\n

\n

@TECHREPORT{jura-tcc-2016,\n     author = {Leonardo Rezende Juracy},\n     title  = {Projeto de uma Célula Latch Testável},\n     institution = {Faculdade de Informática, {Pontifícia Universidade Católica do Rio Grande do Sul (PUCRS)}},\n     year   = 2016,\n     type   = {End of Term Work in Computer Engineering},\n     keywords = {GAPH, design for testability, scan, advised},\n     note   = {Advisor: Alexandre de Morais Amory, Co-Advisor: Matheus Trevisan Moreira},\n     url_link    = {http://www.inf.pucrs.br/alexandre.amory/research/bib/docs/2015_TCC_Leonardo_Juracy.pdf}\n}\n\n\n

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\n \n 2015\n \n \n (4)\n \n \n

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\n \n\n \n \n \n \n \n \n Layered approach for runtime fault recovery in NOC-Based MPSOCS.\n \n \n \n \n\n\n \n Wachter, E. W.\n\n\n \n\n\n\n Ph.D. Thesis, Faculdade de Informática, Pontifícia Universidade Católica do Rio Grande do Sul (PUCRS), Porto Alegre, Brasil, 2015.\n Advisor: Fernando Gehm Moraes, Co-Advisor: Alexandre de Morais Amory\n\n\n\n
\n\n\n\n \n \n $\"Layered$ link\n \n \n\n \n\n \n link\n \n \n\n bibtex\n \n\n \n \n \n abstract \n \n\n \n\n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n \n \n \n\n\n\n

\n

@phdthesis{wachter2015,\n    title    = {{Layered approach for runtime fault recovery in NOC-Based MPSOCS}},\n    school   = {Faculdade de Informática, {Pontifícia Universidade Católica do Rio Grande do Sul (PUCRS)}},\n    author   = {Wachter, Eduardo Weber},\n    year     = {2015},\n    address  = {Porto Alegre, Brasil},\n    keywords = {GAPH,MPSoC, fault tolerance, coadvised},\n    xxxurl_link = {http://hdl.handle.net/10923/7538},\n    url_link = {http://repositorio.pucrs.br/dspace/bitstream/10923/7538/1/000474345-Texto%2bCompleto-0.pdf},\n    xxxurl_code = {https://bitbucket.org/nguyenthanhvuh/dig/},\n    xxxurl_paper = {Pub/mpp.pdf},\n    xxxurl_slides = {Pub/icse14_pres.pdf},\n    abstract   = {Mechanisms for fault-tolerance in MPSoCs are mandatory to cope with defects during fabrication or faults during product lifetime. For instance, permanent faults on the interconnect network can stall or crash applications, even though the MPSoCs’ network has alternative faultfree paths to a given destination. Runtime Fault Tolerance provide self-organization mechanisms to continue delivering their processing services despite defective cores due to the presence of permanent and/or transient faults throughout their lifetime. This Thesis presents a runtime layered approach to a fault-tolerant MPSoC, where each layer is responsible for solving one part of the problem. The approach is built on top of a novel small specialized network used to search fault-free paths. The first layer, named physical layer, is responsible for the fault detection and fault isolation of defective routers. The second layer, named the network layer, is responsible for replacing the original faulty path by an alternative fault-free path. A fault-tolerant routing method executes a path search mechanism and reconfigures the network to use the faulty-free path. The third layer, named transport layer, implements a fault-tolerant communication protocol that triggers the path search in the network layer when a packet does not reach its destination.The last layer, application layer, is responsible for moving tasks from the defective processing element (PE) to a healthy PE, saving the task’s internal state, and restoring it in case of fault while executing a task. Results at the network layer, show a fast path finding method. The entire process of finding alternative paths takes typically less than 2000 clock cycles or 20 microseconds. In the transport layer, different approaches were evaluated being capable of detecting a lost message and start the retransmission. The results show that the overhead to retransmit the message is 2.46X compared to the time to transmit a message without fault, being all other messages transmitted with no overhead. For the DTW, MPEG, and synthetic applications the average-case application execution overhead was 0.17%, 0.09%, and 0.42%, respectively. This represents less than 5% of the application execution overhead worst case. At the application layer, the entire fault recovery protocol executes fast, with a low execution time overhead with no faults (5.67%) and with faults (17.33% - 28.34%).},\n    note   = {Advisor: Fernando Gehm Moraes, Co-Advisor: Alexandre de Morais Amory}\n}\n\n

\n

\n\n\n

\n Mechanisms for fault-tolerance in MPSoCs are mandatory to cope with defects during fabrication or faults during product lifetime. For instance, permanent faults on the interconnect network can stall or crash applications, even though the MPSoCs’ network has alternative faultfree paths to a given destination. Runtime Fault Tolerance provide self-organization mechanisms to continue delivering their processing services despite defective cores due to the presence of permanent and/or transient faults throughout their lifetime. This Thesis presents a runtime layered approach to a fault-tolerant MPSoC, where each layer is responsible for solving one part of the problem. The approach is built on top of a novel small specialized network used to search fault-free paths. The first layer, named physical layer, is responsible for the fault detection and fault isolation of defective routers. The second layer, named the network layer, is responsible for replacing the original faulty path by an alternative fault-free path. A fault-tolerant routing method executes a path search mechanism and reconfigures the network to use the faulty-free path. The third layer, named transport layer, implements a fault-tolerant communication protocol that triggers the path search in the network layer when a packet does not reach its destination.The last layer, application layer, is responsible for moving tasks from the defective processing element (PE) to a healthy PE, saving the task’s internal state, and restoring it in case of fault while executing a task. Results at the network layer, show a fast path finding method. The entire process of finding alternative paths takes typically less than 2000 clock cycles or 20 microseconds. In the transport layer, different approaches were evaluated being capable of detecting a lost message and start the retransmission. The results show that the overhead to retransmit the message is 2.46X compared to the time to transmit a message without fault, being all other messages transmitted with no overhead. For the DTW, MPEG, and synthetic applications the average-case application execution overhead was 0.17%, 0.09%, and 0.42%, respectively. This represents less than 5% of the application execution overhead worst case. At the application layer, the entire fault recovery protocol executes fast, with a low execution time overhead with no faults (5.67%) and with faults (17.33% - 28.34%).\n

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\n \n\n \n \n \n \n \n \n Tolerância a falhas em elementos de processamento de MPSoCs.\n \n \n \n \n\n\n \n Barreto, F. F. d. S.\n\n\n \n\n\n\n Master's thesis, Faculdade de Informática, Pontifícia Universidade Católica do Rio Grande do Sul (PUCRS), Porto Alegre, Brasil, 2015.\n Advisor: Alexandre de Morais Amory\n\n\n\n
\n\n\n\n \n \n $\"Tolerância$ link\n \n \n\n \n\n \n link\n \n \n\n bibtex\n \n\n \n \n \n abstract \n \n\n \n\n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n \n\n\n\n

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@mastersthesis{barreto2015,\n  author       = {Barreto, Francisco Favorino da Silva}, \n  title        = {{Tolerância a falhas em elementos de processamento de MPSoCs}},\n  school       = {Faculdade de Informática, {Pontifícia Universidade Católica do Rio Grande do Sul (PUCRS)}},\n  year         = 2015,\n  address      = {Porto Alegre, Brasil},\n  xxxurl_link     = {http://hdl.handle.net/10923/7743},\n  url_link     = {http://repositorio.pucrs.br/dspace/bitstream/10923/7743/1/000476711-Texto%2bCompleto-0.pdf},\n  keywords     = {GAPH,MPSoC, advised}, \n  abstract     = {The need of more processing capacity for embedded systems nowadays is pushing the research of MPSoCs with tens or hundreds of processors. These characteristics bring design challenges such as scalability and dependability. Such complex systems must have fault tolerant methods to ensure acceptable reliability and availability. This way, the user is not exposed to significant data losses, malfunctioning and even the total system failure. Considering this technology trend, the present work proposes a fault tolerance method with focus in fault recovery. The method uses concepts largely explored in distributed systems to solve the problem of permanent failures in the processing elements of MPSoCs. The implementation is exclusively in software, and recovers the system exposed to a permanent failure on processing elements, reallocating all tasks that were executing in the faulty element to a healthy processing element. The failed application tasks restart their executions since there is no context saving, enabling a lightweight method. The experiments are performed in the HeMPS platform, evaluating the most relevant parameters as recovery time, communication bandwidth impact, scalability and others. In the absence of faults, the proposed protocol has 21 Kbytes of memory area (20% more compared to the original kernel) and no overhead in terms of execution time. In the presence of faults, the results demonstrate total recovery times from 0.2ms to 1ms, depending on the number of reallocated tasks (1 to 7). The biggest impact in the protocol time is related with the reallocation task phase.},\n  note   = {Advisor: Alexandre de Morais Amory}\n}\n\n

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\n \n\n \n \n \n \n \n \n Integration of a multi-agent system into a robotic framework: a case study of a cooperative fault diagnosis application.\n \n \n \n \n\n\n \n Morais, M. G.\n\n\n \n\n\n\n Master's thesis, Faculdade de Informática, Pontifícia Universidade Católica do Rio Grande do Sul (PUCRS), Porto Alegre, Brasil, 2015.\n Advisor: Alexandre de Morais Amory\n\n\n\n
\n\n\n\n \n \n $\"Integration$ link\n \n \n\n \n\n \n link\n \n \n\n bibtex\n \n\n \n \n \n abstract \n \n\n \n \n \n 1 download\n \n \n\n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n \n\n\n\n

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@mastersthesis{morais2015,\n  author     = {Morais, Márcio Godoy},\n  title      = {{Integration of a multi-agent system into a robotic framework: a case study of a cooperative fault diagnosis application}},\n  school     = {Faculdade de Informática, {Pontifícia Universidade Católica do Rio Grande do Sul (PUCRS)}},\n  year       = {2015},\n  address    = {Porto Alegre, Brasil},\n  url_link   = {http://hdl.handle.net/10923/7687},\n  url_link   = {http://repositorio.pucrs.br/dspace/bitstream/10923/7687/3/000476244%20-%20Texto%20Completo.pdf},\n  keywords   = {LSA,robotics, advised},\n  abstract   = {Programming multi-robot autonomous systems can be extremely complex without appropriate software development techniques to abstract hardware faults, as well as can be hard to deal with the complexity of software required the coordinated autonomous behavior. Real environments are dynamic and unexpected events may occur, leading a robot to unforeseen situations or even fault situations. This work presents a method of integration of Jason multi-agent system into ROS robotic framework. Through this integration, can be easier to describe complex missions by using Jason agent language and its resources, as well as abstracting hardware details from the decision-taken process. Moreover, software modules related to the hardware control and modules which have a high CPU cost are separated from the planning and decision-taken process in software layers, allowing plan and software modules reuse in different missions and robots.Through this integration, Jason resources such as plans reconsideration and contingency plans can be used in a way where they can enable the robot to reconsider its actions and strategies in order to reach its goals or to take actions to deal with unforeseen situations due the environment unpredictability or even some robot hardware fault. The presented integration method also allows the cooperation between multiple robots through a standardized language of communication between agents. The proposed method is validated by a case study applied in real robots where a robot can detect a fault in its hardware and diagnose it through the help of another robot, in a highly abstract method of cooperative diagnosis.},\n  note   = {Advisor: Alexandre de Morais Amory}\n}\n\n

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\n\n\n\n\n\n

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\n \n\n \n \n \n \n \n \n Fault supervision for multi robotics systems.\n \n \n \n \n\n\n \n Roman, F. d. F.\n\n\n \n\n\n\n Master's thesis, Faculdade de Informática, Pontifícia Universidade Católica do Rio Grande do Sul (PUCRS), Porto Alegre, Brasil, 2015.\n Advisor: Alexandre de Morais Amory\n\n\n\n
\n\n\n\n \n \n $\"Fault$ link\n \n \n\n \n\n \n link\n \n \n\n bibtex\n \n\n \n \n \n abstract \n \n\n \n\n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n \n\n\n\n

\n

@mastersthesis{romani2015,\n  author     = {Roman, Felipe de Fraga},\n  title      = {{Fault supervision for multi robotics systems}},\n  school     = {Faculdade de Informática, {Pontifícia Universidade Católica do Rio Grande do Sul (PUCRS)}},\n  year       = {2015},\n  address    = {Porto Alegre, Brasil},\n  xxxurl_link   = {http://hdl.handle.net/10923/7732},\n  url_link   = {http://repositorio.pucrs.br/dspace/bitstream/10923/7732/1/000476572-Texto%2bCompleto-0.pdf},\n  keywords   = {LSA,robotics, advised},\n  abstract   = {As robotics becomes more common and people start to use it in routine tasks, dependability becomes more and more relevant to create trustworthy solutions. A commonly used approach to provide reliability and availability is the use of multi robots instead of a single robot. However, in case of a large teams of robots (tens or more), determining the system status can be a challenge. This work presents a runtime monitoring solution for Multi Robotic Systems. It integrates Nagios IT Monitoring tool and ROS robotic middleware. One of the potential advantages of this approach is that the use of a consolidated IT infrastructure tool enables the reuse of several relevant features developed to monitor large datacenters. Another important advantage of that this solution does not require additional software at the robot side. The experimental results demonstrate that the proposed monitoring system has a small performance impact on the robot and the monitoring server can easily support hundreds or even thousands of monitored robots.},\n  note   = {Advisor: Alexandre de Morais Amory}\n}\n\n

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\n \n 2014\n \n \n (1)\n \n \n

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\n \n\n \n \n \n \n \n \n Otimização e análise de algoritmos de ordenamento de redes proteicas.\n \n \n \n \n\n\n \n Kuentzer, F. A.\n\n\n \n\n\n\n Master's thesis, Faculdade de Informática, Pontifícia Universidade Católica do Rio Grande do Sul (PUCRS), Porto Alegre, Brasil, 2014.\n Advisor: Alexandre de Morais Amory\n\n\n\n
\n\n\n\n \n \n $\"Otimização$ link\n \n \n\n \n\n \n link\n \n \n\n bibtex\n \n\n \n \n \n abstract \n \n\n \n\n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n \n \n \n\n\n\n

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@mastersthesis{kuentzer2014,\n  author     = {Kuentzer, Felipe Augusto},\n  title      = {{Otimização e análise de algoritmos de ordenamento de redes proteicas}},\n  school     = {Faculdade de Informática, {Pontifícia Universidade Católica do Rio Grande do Sul (PUCRS)}},\n  year       = {2014},\n  address    = {Porto Alegre, Brasil},\n  xxxurl_link   = {http://hdl.handle.net/10923/6663},\n  url_link   = {http://repositorio.pucrs.br/dspace/bitstream/10923/6663/1/000458957-Texto%2bCompleto-0.pdf},\n  keywords   = {bioinformatics, software optimization, seriation, advised},\n  abstract   = {Analysis by Transcriptogram was developed as a solution to noise reduction, usually present in the microarray measuring technique of the Transcriptome, and has demonstrated potential to be applied as a method of disease diagnostics. The noise reduction in the measure is achived by the protein interaction network ordering, allowing gene expression analysis in whole genome scale. The Transcriptogram's efficiency to noise reduction was analyzed, however, it still lacks an analisys of the ordering quality, so that the best parameter setting for the ordering algorithm is used by the Transcriptogram. So far, this analysis is hindered by the high runtime of the ordering algorithm. In this work, an analysis of the ordering algorithm stages allows some optimizations, and consequent reduction in execution time, also allowing further analysis on which parameters settings have the greatest influence on the ordering quality. Applying the Transcriptogram to a diagnostic problem, the diagnostic measure is used to characterize the influence of the parameters of the ordering algorithm to achive better diagnoses. The results show that the protein network used in previous works doesn't produce the best diagnostics. Moreover, the ordering minimization, achieved by executing the ordering algorithm for longer periods, does not necessarily increase the probability to find better diagnosis compared to random ordering. Eventhough the experimental diagnostic results could not statistically differentiate random ordering from optimized ordering, these results cannot be considered conclusive since a single disease has been evaluated.},\n  note   = {Advisor: Alexandre de Morais Amory}\n}\n\n\n

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\n \n 2011\n \n \n (1)\n \n \n

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\n \n\n \n \n \n \n \n \n Mapeamento dinâmico de aplicações para MPSOCS homogêneos.\n \n \n \n \n\n\n \n Mandelli, M. G.\n\n\n \n\n\n\n Master's thesis, Faculdade de Informática, Pontifícia Universidade Católica do Rio Grande do Sul (PUCRS), Porto Alegre, Brasil, 2011.\n Advisor: Fernando Gehm Moraes, Co-Advisor: Alexandre de Morais Amory\n\n\n\n
\n\n\n\n \n \n $\"Mapeamento$ link\n \n \n\n \n\n \n link\n \n \n\n bibtex\n \n\n \n \n \n abstract \n \n\n \n\n \n \n \n \n \n \n \n\n \n \n \n \n \n \n \n \n \n\n\n\n

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@mastersthesis{mandelli2011,\n  author     = {Mandelli, Marcelo Grandi},\n  title      = {{Mapeamento dinâmico de aplicações para MPSOCS homogêneos}},\n  school     = {Faculdade de Informática, {Pontifícia Universidade Católica do Rio Grande do Sul (PUCRS)}},\n  year       = {2011},\n  address    = {Porto Alegre, Brasil},\n  xxxurl_link   = {http://hdl.handle.net/10923/1634},\n  url_link   = {http://repositorio.pucrs.br/dspace/bitstream/10923/1634/1/000435006-Texto%2bCompleto-0.pdf},\n  keywords   = {GAPH,MPSoC, coadvised},\n  abstract   = {The advance in manufacturing technology of integrated circuits enables smaller transistors, making possible the development of SoCs (System-on-Chip). Many applications require multi-processor SoCs in order to meet their performance requirements. A SoC containing several processing elements (PEs) is called MPSoC. An MPSoC can be classified as homogeneous, when all their PEs has the same architecture; or heterogeneous, when they have different architectures. . As communication infrastructure, the MPSoC can use NoCs as a way to interconnect the PEs. NoCs may be used to replace busses, due to their advantages of higher scalability and communication parallelism.One of the main problems related to MPSoC projects is to define a PE of the system that will run each task. This problem is called task mapping. The mapping can be classified into static, which occurs at design time, and dynamic that occurs at runtime. The dynamic mapping approach requires firstly the mapping of the initial tasks of an application (which does not depend on any other task). The other tasks, in this approach, are mapped dynamically when requested. The mapping can be also classified by the number of tasks running in a PE. The mapping is classified as single task, when only one task is executed by a PE, and as multitask, when multiple tasks can be executed in a same PE.This work proposes new single task and multitask dynamic task mapping heuristics, in order to reduce communication energy. Results are evaluated using the MPSoC HeMPS, which executes application code generated from a model-based simulation environment. These heuristics are compared with mapping heuristic presented in literature, obtaining, in the evaluated scenarios, an average communication energy reduction of 9.8%, for the single task approach, and 18.6%, for the multitask approach. This work also evaluates the inclusion of dynamic load on the system, which makes necessary the implementation of an initial tasks mapping heuristic. This heuristic is an innovative contribution, since a similar approach is not found in any other work in literature.},\n  note   = {Advisor: Fernando Gehm Moraes, Co-Advisor: Alexandre de Morais Amory}\n}\n\n

\n

\n\n\n

\n The advance in manufacturing technology of integrated circuits enables smaller transistors, making possible the development of SoCs (System-on-Chip). Many applications require multi-processor SoCs in order to meet their performance requirements. A SoC containing several processing elements (PEs) is called MPSoC. An MPSoC can be classified as homogeneous, when all their PEs has the same architecture; or heterogeneous, when they have different architectures. . As communication infrastructure, the MPSoC can use NoCs as a way to interconnect the PEs. NoCs may be used to replace busses, due to their advantages of higher scalability and communication parallelism.One of the main problems related to MPSoC projects is to define a PE of the system that will run each task. This problem is called task mapping. The mapping can be classified into static, which occurs at design time, and dynamic that occurs at runtime. The dynamic mapping approach requires firstly the mapping of the initial tasks of an application (which does not depend on any other task). The other tasks, in this approach, are mapped dynamically when requested. The mapping can be also classified by the number of tasks running in a PE. The mapping is classified as single task, when only one task is executed by a PE, and as multitask, when multiple tasks can be executed in a same PE.This work proposes new single task and multitask dynamic task mapping heuristics, in order to reduce communication energy. Results are evaluated using the MPSoC HeMPS, which executes application code generated from a model-based simulation environment. These heuristics are compared with mapping heuristic presented in literature, obtaining, in the evaluated scenarios, an average communication energy reduction of 9.8%, for the single task approach, and 18.6%, for the multitask approach. This work also evaluates the inclusion of dynamic load on the system, which makes necessary the implementation of an initial tasks mapping heuristic. This heuristic is an innovative contribution, since a similar approach is not found in any other work in literature.\n

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