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\n  \n 2024\n \n \n (1)\n \n \n
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\n \n\n \n \n \n \n \n \n On the Interactions between ILP and TLP with Hardware Transactional Memory.\n \n \n \n \n\n\n \n Nicolás-Conesa, V.; Titos-Gil, R.; Fernández-Pascual, R.; Ros, A.; and Acacio, M. E.\n\n\n \n\n\n\n Microprocessors and Microsystems (MICPRO), 104: 104975. February 2024.\n \n\n\n\n
\n\n\n\n \n \n \"OnPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@Article{vnicolas-micpro24,\n  author = \t {V{\\'{\\i}}ctor Nicol{\\'a}s-Conesa and Rub{\\'e}n Titos-Gil and Ricardo Fern{\\'a}ndez-Pascual and Alberto Ros and Manuel E. Acacio},\n  title = \t {On the Interactions between ILP and TLP with Hardware Transactional Memory},\n  journal = \t {Microprocessors and Microsystems (MICPRO)},\n  doi =          {10.1016/j.micpro.2023.104975},\n  year = \t {2024},\n  volume = \t {104},\n  issn =         {0141-9331},\n  pages = \t {104975},\n  month = \t feb,\n  impactfactor = {2.6, 27/54 (Q2) - COMPUTER SCIENCE, HARDWARE & ARCHITECTURE (2022)},\n  url       = {http://ditec.um.es/~rtitos/papers/2024_micpro_ilphtm_vnicolas.pdf},\n}\n\n
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\n  \n 2022\n \n \n (3)\n \n \n
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\n \n\n \n \n \n \n \n \n Analysing software prefetching opportunities in hardware transactional memory.\n \n \n \n \n\n\n \n Shimchenko, M.; Titos-Gil, R.; Fernández-Pascual, R.; Acacio, M. E.; Kaxiras, S.; Ros, A.; and Jimborean, A.\n\n\n \n\n\n\n The Journal of Supercomputing, 78(1): 919–1944. 2022.\n \n\n\n\n
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@article{shimchenko:tmdae:supe:2022,\n  author    = {\tMarina Shimchenko and Rub{\\'{e}}n Titos-Gil and Ricardo Fernández-Pascual and Manuel E. Acacio and Stefanos Kaxiras and Alberto Ros and Alexandra Jimborean},\n  title     = {Analysing software prefetching opportunities in hardware transactional memory},\n  journal   = {The Journal of Supercomputing},\n  volume    = {78},\n  number    = {1},\n  pages     = {919--1944},\n  year      = {2022},\n  url       = {http://ditec.um.es/~rtitos/papers/2022_supe_tmdae_shimchenko.pdf},\n  doi       = {10.1007/s11227-021-03897-z},\n}\n\n\n
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\n \n\n \n \n \n \n \n \n DeTraS: Delaying Stores for Friendly-Fire Mitigation in Hardware Transactional Memory.\n \n \n \n \n\n\n \n Titos-Gil, R.; Fernández-Pascual, R.; Ros, A.; and Acacio, M. E.\n\n\n \n\n\n\n IEEE Trans. Parallel Distrib. Syst., 33(1): 1–13. 2022.\n \n\n\n\n
\n\n\n\n \n \n \"DeTraS:Paper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n  \n \n 9 downloads\n \n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@article{titos:detras:tpds:2022,\n  author    = {Rub{\\'{e}}n Titos-Gil and\n               Ricardo Fern{\\'{a}}ndez-Pascual and\n               Alberto Ros and\n               Manuel E. Acacio},\n  title     = {{DeTraS}: Delaying Stores for Friendly-Fire Mitigation in Hardware Transactional Memory},\n  journal   = {{IEEE} Trans. Parallel Distrib. Syst.},\n  volume    = {33},\n  number    = {1},\n  pages     = {1--13},\n  year      = {2022},\n  url       = {http://ditec.um.es/~rtitos/papers/2021_tpds_detras.pdf},\n  doi       = {10.1109/TPDS.2021.3085210},\n}\n\n\n
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\n \n\n \n \n \n \n \n \n Analysis of the Interactions Between ILP and TLP With Hardware Transactional Memory.\n \n \n \n \n\n\n \n Nicolás-Conesa, V.; Titos-Gil, R.; Fernández-Pascual, R.; Ros, A.; and Acacio, M. E.\n\n\n \n\n\n\n In 30th Euromicro International Conference on Parallel, Distributed and Network-based Processing, PDP 2022, Valladolid, Spain, March 9-11, 2022, pages 157–164, 2022. IEEE\n \n\n\n\n
\n\n\n\n \n \n \"AnalysisPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/pdp/Nicolas-ConesaT22,\n  author       = {V{\\'{\\i}}ctor Nicol{\\'{a}}s{-}Conesa and\n                  Rub{\\'{e}}n Titos-Gil and\n                  Ricardo Fern{\\'{a}}ndez-Pascual and\n                  Alberto Ros and\n                  Manuel E. Acacio},\n  title        = {Analysis of the Interactions Between {ILP} and {TLP} With Hardware\n                  Transactional Memory},\n  booktitle    = {30th Euromicro International Conference on Parallel, Distributed and\n                  Network-based Processing, {PDP} 2022, Valladolid, Spain, March 9-11,\n                  2022},\n  pages        = {157--164},\n  publisher    = {{IEEE}},\n  year         = {2022},\n  url       = {http://ditec.um.es/~rtitos/papers/2022_pdp_ilphtm_vnicolas.pdf},\n  doi          = {10.1109/PDP55904.2022.00032},\n  biburl       = {https://dblp.org/rec/conf/pdp/Nicolas-ConesaT22.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n  \n 2021\n \n \n (1)\n \n \n
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\n \n\n \n \n \n \n \n \n Efficient, Distributed, and Non-Speculative Multi-Address Atomic Operations.\n \n \n \n \n\n\n \n Gómez-Hernández, E. J.; Cebrian, J. M.; Titos-Gil, R.; Kaxiras, S.; and Ros, A.\n\n\n \n\n\n\n In MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture, Virtual Event, Greece, October 18-22, 2021, pages 337–349, 2021. ACM\n \n\n\n\n
\n\n\n\n \n \n \"Efficient,Paper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/micro/Gomez-Hernandez21,\n  author       = {Eduardo Jos{\\'{e}} G{\\'{o}}mez{-}Hern{\\'{a}}ndez and\n                  Juan M. Cebrian and\n                  Rub{\\'{e}}n Titos-Gil and\n                  Stefanos Kaxiras and\n                  Alberto Ros},\n  title        = {Efficient, Distributed, and Non-Speculative Multi-Address Atomic Operations},\n  booktitle    = {{MICRO} '21: 54th Annual {IEEE/ACM} International Symposium on Microarchitecture,\n                  Virtual Event, Greece, October 18-22, 2021},\n  pages        = {337--349},\n  publisher    = {{ACM}},\n  year         = {2021},\n  url       = {http://ditec.um.es/~rtitos/papers/2021_micro_mcas_gomez.pdf},\n  doi          = {10.1145/3466752.3480073},\n}\n\n
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\n  \n 2020\n \n \n (2)\n \n \n
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\n \n\n \n \n \n \n \n \n PfTouch: Concurrent Page-Fault Handling for Intel Restricted Transactional Memory.\n \n \n \n \n\n\n \n Titos-Gil, R.; Fernández-Pascual, R.; Ros, A.; and Acacio, M. E.\n\n\n \n\n\n\n J. Parallel Distrib. Comput., 145: 111–123. 2020.\n \n\n\n\n
\n\n\n\n \n \n \"PfTouch:Paper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n  \n \n 13 downloads\n \n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@article{titos:pftouch:jpdc:2020,\n  author    = {Rub{\\'{e}}n Titos-Gil and\n               Ricardo Fern{\\'{a}}ndez-Pascual and\n               Alberto Ros and\n               Manuel E. Acacio},\n  title     = {{PfTouch}: Concurrent Page-Fault Handling for Intel Restricted Transactional Memory},\n  journal   = {J. Parallel Distrib. Comput.},\n  volume    = {145},\n  pages     = {111--123},\n  year      = {2020},\n  url       = {http://ditec.um.es/~rtitos/papers/2020_jpdc_pftouch.pdf},\n  doi       = {10.1016/j.jpdc.2020.06.009},\n}\n\n
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\n \n\n \n \n \n \n \n \n Concurrent Irrevocability in Best-Effort Hardware Transactional Memory.\n \n \n \n \n\n\n \n Titos-Gil, R.; Fernández-Pascual, R.; Ros, A.; and Acacio, M. E.\n\n\n \n\n\n\n IEEE Trans. Parallel Distrib. Syst., 31(6): 1301–1315. 2020.\n \n\n\n\n
\n\n\n\n \n \n \"ConcurrentPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n  \n \n 12 downloads\n \n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@article{titos:cit:tpds:2019,\n  author    = {Rub{\\'{e}}n Titos-Gil and\n               Ricardo Fern{\\'{a}}ndez-Pascual and\n               Alberto Ros and\n               Manuel E. Acacio},\n  title     = {Concurrent Irrevocability in Best-Effort Hardware Transactional Memory},\n  journal   = {{IEEE} Trans. Parallel Distrib. Syst.},\n  volume    = {31},\n  number    = {6},\n  pages     = {1301--1315},\n  year      = {2020},\n  url       = {http://ditec.um.es/~rtitos/papers/2019_tpds_cit.pdf},\n  doi       = { 10.1109/TPDS.2019.2963030}\n}\n\n
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\n  \n 2019\n \n \n (1)\n \n \n
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\n \n\n \n \n \n \n \n \n Way Combination for an Adaptive and Scalable Coherence Directory.\n \n \n \n \n\n\n \n Titos-Gil, R.; Flores, A.; Fernández-Pascual, R.; Ros, A.; Petit, S.; Sahuquillo, J.; and Acacio, M. E.\n\n\n \n\n\n\n IEEE Trans. Parallel Distrib. Syst., 30(11): 2608–2623. 2019.\n \n\n\n\n
\n\n\n\n \n \n \"WayPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n  \n \n 9 downloads\n \n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@article{DBLP:journals/tpds/GilFPRPSA19,\n  author    = {Rub{\\'{e}}n Titos-Gil and\n               Antonio Flores and\n               Ricardo Fern{\\'{a}}ndez-Pascual and\n               Alberto Ros and\n               Salvador Petit and\n               Julio Sahuquillo and\n               Manuel E. Acacio},\n  title     = {Way Combination for an Adaptive and Scalable Coherence Directory},\n  journal   = {{IEEE} Trans. Parallel Distrib. Syst.},\n  volume    = {30},\n  number    = {11},\n  pages     = {2608--2623},\n  year      = {2019},\n  url       = {http://ditec.um.es/~rtitos/papers/2019_tpds.pdf},\n  doi       = {10.1109/TPDS.2019.2917185},\n  biburl    = {https://dblp.org/rec/bib/journals/tpds/GilFPRPSA19},\n  bibsource = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Way-combining directory: an adaptive and scalable low-cost coherence directory.\n \n \n \n \n\n\n \n Titos-Gil, R.; Flores, A.; Fernández-Pascual, R.; Ros, A.; and Acacio, M. E.\n\n\n \n\n\n\n In Proceedings of the International Conference on Supercomputing, ICS 2017, Chicago, IL, USA, June 14-16, 2017, pages 20:1–20:10, 2017. \n \n\n\n\n
\n\n\n\n \n \n \"Way-combiningPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n  \n \n 3 downloads\n \n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{titos:wcdir:ics:2017,\n  author    = {Rub{\\'{e}}n Titos-Gil and\n               Antonio Flores and\n               Ricardo Fern{\\'{a}}ndez-Pascual and\n               Alberto Ros and\n               Manuel E. Acacio},\n  title     = {Way-combining directory: an adaptive and scalable low-cost coherence\n               directory},\n  booktitle = {Proceedings of the International Conference on Supercomputing, {ICS}\n               2017, Chicago, IL, USA, June 14-16, 2017},\n  pages     = {20:1--20:10},\n  year      = {2017},\n  crossref  = {DBLP:conf/ics/2017},\n  url       = {http://ditec.um.es/~rtitos/papers/2017_ics.pdf},\n  doi       = {10.1145/3079079.3079096},\n  timestamp = {Tue, 06 Nov 2018 11:07:02 +0100},\n  biburl    = {https://dblp.org/rec/bib/conf/ics/GilFPRA17},\n  bibsource = {dblp computer science bibliography, https://dblp.org}\n}\n\n\n\n
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\n  \n 2016\n \n \n (2)\n \n \n
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\n \n\n \n \n \n \n \n \n Architectural support for efficient message passing on shared memory multi-cores.\n \n \n \n \n\n\n \n Titos-Gil, R.; Palomar, O.; Unsal, O. S.; and Cristal, A.\n\n\n \n\n\n\n J. Parallel Distrib. Comput., 95: 92–106. 2016.\n \n\n\n\n
\n\n\n\n \n \n \"ArchitecturalPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n  \n \n 2 downloads\n \n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@article{titos:dimp:jpdc:2016,\n  author    = {Rub{\\'{e}}n Titos-Gil and\n               Oscar Palomar and\n               Osman S. Unsal and\n               Adri{\\'{a}}n Cristal},\n  title     = {Architectural support for efficient message passing on shared memory\n               multi-cores},\n  journal   = {J. Parallel Distrib. Comput.},\n  volume    = {95},\n  pages     = {92--106},\n  year      = {2016},\n  url       = {http://ditec.um.es/~rtitos/papers/2016_jpdc.pdf},\n  doi       = {10.1016/j.jpdc.2016.02.005},\n  timestamp = {Fri, 30 Nov 2018 00:00:00 +0100},\n  biburl    = {https://dblp.org/rec/bib/journals/jpdc/GilPUC16},\n  bibsource = {dblp computer science bibliography, https://dblp.org}\n}\n\n\n\n
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\n \n\n \n \n \n \n \n \n Energy minimization at all layers of the data center: The ParaDIME project.\n \n \n \n \n\n\n \n Palomar, O.; Rethinagiri, S. K.; Yalcin, G.; Titos-Gil, R.; Prieto, P.; Torrella, E.; Unsal, O. S.; Cristal, A.; Felber, P.; Sobe, A.; Hayduk, Y.; Kurpicz, M.; Fetzer, C.; Knauth, T.; Schneegaß, M.; Struckmeier, J.; and Milojevic, D.\n\n\n \n\n\n\n In 2016 Design, Automation & Test in Europe Conference & Exhibition, DATE 2016, Dresden, Germany, March 14-18, 2016, pages 684–689, 2016. \n \n\n\n\n
\n\n\n\n \n \n \"EnergyPaper\n  \n \n\n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{palomar:paradime:date:2016,\n  author    = {Oscar Palomar and\n               Santhosh Kumar Rethinagiri and\n               Gulay Yalcin and\n               Rub{\\'{e}}n Titos-Gil and\n               Pablo Prieto and\n               Emma Torrella and\n               Osman S. Unsal and\n               Adri{\\'{a}}n Cristal and\n               Pascal Felber and\n               Anita Sobe and\n               Yaroslav Hayduk and\n               Mascha Kurpicz and\n               Christof Fetzer and\n               Thomas Knauth and\n               Malte Schneega{\\ss} and\n               Jens Struckmeier and\n               Dragomir Milojevic},\n  title     = {Energy minimization at all layers of the data center: The ParaDIME\n               project},\n  booktitle = {2016 Design, Automation {\\&amp;} Test in Europe Conference {\\&amp;} Exhibition,\n               {DATE} 2016, Dresden, Germany, March 14-18, 2016},\n  pages     = {684--689},\n  year      = {2016},\n  crossref  = {DBLP:conf/date/2016},\n  url       = {http://ditec.um.es/~rtitos/papers/2016_date.pdf},\n  timestamp = {Sun, 30 Apr 2017 01:00:00 +0200},\n  biburl    = {https://dblp.org/rec/bib/conf/date/PalomarRYGPTUCF16},\n  bibsource = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n ParaDIME: Parallel Distributed Infrastructure for Minimization of Energy for data centers.\n \n \n \n \n\n\n \n Rethinagiri, S. K.; Palomar, O.; Sobe, A.; Yalcin, G.; Knauth, T.; Titos-Gil, R.; Prieto, P.; Schneegaß, M.; Cristal, A.; Unsal, O. S.; Felber, P.; Fetzer, C.; and Milojevic, D.\n\n\n \n\n\n\n Microprocessors and Microsystems - Embedded Hardware Design, 39(8): 1174–1189. 2015.\n \n\n\n\n
\n\n\n\n \n \n \"ParaDIME:Paper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n  \n \n 1 download\n \n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@article{rethinagiri:paradime:microproc:2015,\n  author    = {Santhosh Kumar Rethinagiri and\n               Oscar Palomar and\n               Anita Sobe and\n               Gulay Yalcin and\n               Thomas Knauth and\n               Rub{\\'{e}}n Titos-Gil and\n               Pablo Prieto and\n               Malte Schneega{\\ss} and\n               Adri{\\'{a}}n Cristal and\n               Osman S. Unsal and\n               Pascal Felber and\n               Christof Fetzer and\n               Dragomir Milojevic},\n  title     = {ParaDIME: Parallel Distributed Infrastructure for Minimization of\n               Energy for data centers},\n  journal   = {Microprocessors and Microsystems - Embedded Hardware Design},\n  volume    = {39},\n  number    = {8},\n  pages     = {1174--1189},\n  year      = {2015},\n  url       = {http://ditec.um.es/~rtitos/papers/2015_microproc.pdf},\n  doi       = {10.1016/j.micpro.2015.06.005},\n  timestamp = {Fri, 30 Nov 2018 00:00:00 +0100},\n  biburl    = {https://dblp.org/rec/bib/journals/mam/RethinagiriPSYK15},\n  bibsource = {dblp computer science bibliography, https://dblp.org}\n}\n\n\n\n
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\n \n\n \n \n \n \n \n \n DiMP: Architectural Support for Direct Message Passing on Shared Memory Multi-cores.\n \n \n \n \n\n\n \n Titos-Gil, R.; Palomar, O.; Unsal, O. S.; and Cristal, A.\n\n\n \n\n\n\n In 44th International Conference on Parallel Processing, ICPP 2015, Beijing, China, September 1-4, 2015, pages 130–139, 2015. \n \n\n\n\n
\n\n\n\n \n \n \"DiMP:Paper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n  \n \n 1 download\n \n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{titos:dimp:icpp:2015,\n  author    = {Rub{\\'{e}}n Titos-Gil and\n               Oscar Palomar and\n               Osman S. Unsal and\n               Adri{\\'{a}}n Cristal},\n  title     = {DiMP: Architectural Support for Direct Message Passing on Shared Memory\n               Multi-cores},\n  booktitle = {44th International Conference on Parallel Processing, {ICPP} 2015,\n               Beijing, China, September 1-4, 2015},\n  pages     = {130--139},\n  year      = {2015},\n  crossref  = {DBLP:conf/icpp/2015},\n  url       = {http://ditec.um.es/~rtitos/papers/2015_icpp-dimp.pdf},\n  doi       = {10.1109/ICPP.2015.22},\n  timestamp = {Fri, 02 Nov 2018 00:00:00 +0100},\n  biburl    = {https://dblp.org/rec/bib/conf/icpp/GilPUC15},\n  bibsource = {dblp computer science bibliography, https://dblp.org}\n}\n\n\n\n
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\n \n\n \n \n \n \n \n \n Enhancing Garbage Collection Synchronization Using Explicit Bit Barriers.\n \n \n \n \n\n\n \n Hollmann, J.; Titos-Gil, R.; and Stenström, P.\n\n\n \n\n\n\n In 44th International Conference on Parallel Processing, ICPP 2015, Beijing, China, September 1-4, 2015, pages 769–778, 2015. \n \n\n\n\n
\n\n\n\n \n \n \"EnhancingPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{hollmann:barriers:icpp:2015,\n  author    = {Jochen Hollmann and\n               Rub{\\'{e}}n Titos-Gil and\n               Per Stenstr{\\"{o}}m},\n  title     = {Enhancing Garbage Collection Synchronization Using Explicit Bit Barriers},\n  booktitle = {44th International Conference on Parallel Processing, {ICPP} 2015,\n               Beijing, China, September 1-4, 2015},\n  pages     = {769--778},\n  year      = {2015},\n  crossref  = {DBLP:conf/icpp/2015},\n  url       = {http://ditec.um.es/~rtitos/papers/2015_icpp-ebb.pdf},\n  doi       = {10.1109/ICPP.2015.86},\n  timestamp = {Fri, 02 Nov 2018 00:00:00 +0100},\n  biburl    = {https://dblp.org/rec/bib/conf/icpp/HollmannGS15},\n  bibsource = {dblp computer science bibliography, https://dblp.org}\n}\n\n\n
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\n \n\n \n \n \n \n \n \n Hardware Approaches to Transactional Memory in Chip Multiprocessors.\n \n \n \n \n\n\n \n Titos-Gil, R.; and Acacio, M. E.\n\n\n \n\n\n\n In Handbook on Data Centers, pages 805–835. 2015.\n \n\n\n\n
\n\n\n\n \n \n \"HardwarePaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@incollection{titos:htm:datacenters:2015,\n  author    = {Rub{\\'{e}}n Titos-Gil and\n               Manuel E. Acacio},\n  title     = {Hardware Approaches to Transactional Memory in Chip Multiprocessors},\n  booktitle = {Handbook on Data Centers},\n  pages     = {805--835},\n  year      = {2015},\n  crossref  = {DBLP:reference/sp/2015dc},\n  url       = {10.1007/978-1-4939-2092-1\\_27},\n  doi       = {10.1007/978-1-4939-2092-1\\_27},\n  timestamp = {Fri, 02 Nov 2018 00:00:00 +0100},\n  biburl    = {https://dblp.org/rec/bib/reference/sp/GilA15},\n  bibsource = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n  \n 2014\n \n \n (3)\n \n \n
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\n \n\n \n \n \n \n \n \n Selective dynamic serialization for reducing energy consumption in hardware transactional memory systems.\n \n \n \n \n\n\n \n Gaona-Ramírez, E.; Titos-Gil, R.; Fernández, J.; and Acacio, M. E.\n\n\n \n\n\n\n The Journal of Supercomputing, 68(2): 914–934. 2014.\n \n\n\n\n
\n\n\n\n \n \n \"SelectivePaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@article{gaona:selective:supe:2014,\n  author    = {Epifanio Gaona{-}Ram{\\'{\\i}}rez and\n               Rub{\\'{e}}n Titos-Gil and\n               Juan Fern{\\'{a}}ndez and\n               Manuel E. Acacio},\n  title     = {Selective dynamic serialization for reducing energy consumption in\n               hardware transactional memory systems},\n  journal   = {The Journal of Supercomputing},\n  volume    = {68},\n  number    = {2},\n  pages     = {914--934},\n  year      = {2014},\n  url       = {http://ditec.um.es/~rtitos/papers/2014_supe.pdf},\n  doi       = {10.1007/s11227-013-1072-y},\n  timestamp = {Fri, 30 Nov 2018 00:00:00 +0100},\n  biburl    = {https://dblp.org/rec/bib/journals/tjs/Gaona-RamirezGFA14},\n  bibsource = {dblp computer science bibliography, https://dblp.org}\n}\n\n\n\n
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\n \n\n \n \n \n \n \n \n ZEBRA: Data-Centric Contention Management in Hardware Transactional Memory.\n \n \n \n \n\n\n \n Titos-Gil, R.; Negi, A.; Acacio, M. E.; García, J. M.; and Stenström, P.\n\n\n \n\n\n\n IEEE Trans. Parallel Distrib. Syst., 25(5): 1359–1369. 2014.\n \n\n\n\n
\n\n\n\n \n \n \"ZEBRA:Paper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@article{titos:zebra:tpds:2014,\n  author    = {Rub{\\'{e}}n Titos-Gil and\n               Anurag Negi and\n               Manuel E. Acacio and\n               Jos{\\'{e}} M. Garc{\\'{\\i}}a and\n               Per Stenstr{\\"{o}}m},\n  title     = {{ZEBRA:} Data-Centric Contention Management in Hardware Transactional\n               Memory},\n  journal   = {{IEEE} Trans. Parallel Distrib. Syst.},\n  volume    = {25},\n  number    = {5},\n  pages     = {1359--1369},\n  year      = {2014},\n  url       = {http://ditec.um.es/~rtitos/papers/2014_tpds.pdf},\n  doi       = {10.1109/TPDS.2013.262},\n  timestamp = {Fri, 02 Nov 2018 00:00:00 +0100},\n  biburl    = {https://dblp.org/rec/bib/journals/tpds/GilNA0S14},\n  bibsource = {dblp computer science bibliography, https://dblp.org}\n}\n\n\n\n
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\n \n\n \n \n \n \n \n \n Performance and Energy Analysis of the Restricted Transactional Memory Implementation on Haswell.\n \n \n \n \n\n\n \n Goel, B.; Titos-Gil, R.; Negi, A.; McKee, S. A.; and Stenström, P.\n\n\n \n\n\n\n In 2014 IEEE 28th International Parallel and Distributed Processing Symposium, Phoenix, AZ, USA, May 19-23, 2014, pages 615–624, 2014. \n \n\n\n\n
\n\n\n\n \n \n \"PerformancePaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n  \n \n 1 download\n \n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{goel:rtm:ipdps:2014,\n  author    = {Bhavishya Goel and\n               Rub{\\'{e}}n Titos-Gil and\n               Anurag Negi and\n               Sally A. McKee and\n               Per Stenstr{\\"{o}}m},\n  title     = {Performance and Energy Analysis of the Restricted Transactional Memory\n               Implementation on Haswell},\n  booktitle = {2014 {IEEE} 28th International Parallel and Distributed Processing\n               Symposium, Phoenix, AZ, USA, May 19-23, 2014},\n  pages     = {615--624},\n  year      = {2014},\n  crossref  = {DBLP:conf/ipps/2014},\n  url       = {http://ditec.um.es/~rtitos/papers/2014_ipdps.pdf},\n  doi       = {10.1109/IPDPS.2014.70},\n  timestamp = {Fri, 02 Nov 2018 00:00:00 +0100},\n  biburl    = {https://dblp.org/rec/bib/conf/ipps/GoelGNMS14},\n  bibsource = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n  \n 2013\n \n \n (5)\n \n \n
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\n \n\n \n \n \n \n \n \n On the design of energy-efficient hardware transactional memory systems.\n \n \n \n \n\n\n \n Gaona-Ramírez, E.; Titos-Gil, R.; Fernández, J.; and Acacio, M. E.\n\n\n \n\n\n\n Concurrency and Computation: Practice and Experience, 25(6): 862–880. 2013.\n \n\n\n\n
\n\n\n\n \n \n \"OnPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@article{gaona:energyhtm:cpe:2013,\n  author    = {Epifanio Gaona{-}Ram{\\'{\\i}}rez and\n               Rub{\\'{e}}n Titos-Gil and\n               Juan Fern{\\'{a}}ndez and\n               Manuel E. Acacio},\n  title     = {On the design of energy-efficient hardware transactional memory systems},\n  journal   = {Concurrency and Computation: Practice and Experience},\n  volume    = {25},\n  number    = {6},\n  pages     = {862--880},\n  year      = {2013},\n  url       = {http://ditec.um.es/~rtitos/papers/2013_cpe.pdf},\n  doi       = {10.1002/cpe.2866},\n  timestamp = {Fri, 30 Nov 2018 00:00:00 +0100},\n  biburl    = {https://dblp.org/rec/bib/journals/concurrency/Gaona-RamirezGFA13},\n  bibsource = {dblp computer science bibliography, https://dblp.org}\n}\n\n\n\n
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\n \n\n \n \n \n \n \n \n SCIN-cache: Fast speculative versioning in multithreaded cores.\n \n \n \n \n\n\n \n Negi, A.; and Titos-Gil, R.\n\n\n \n\n\n\n TACO, 9(4): 58:1–58:26. 2013.\n \n\n\n\n
\n\n\n\n \n \n \"SCIN-cache:Paper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@article{negi:scincache:taco:2013,\n  author    = {Anurag Negi and\n               Rub{\\'{e}}n Titos-Gil},\n  title     = {SCIN-cache: Fast speculative versioning in multithreaded cores},\n  journal   = {{TACO}},\n  volume    = {9},\n  number    = {4},\n  pages     = {58:1--58:26},\n  year      = {2013},\n  url       = {http://ditec.um.es/~rtitos/papers/2013_taco.pdf},\n  doi       = {10.1145/2400682.2400717},\n  timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},\n  biburl    = {https://dblp.org/rec/bib/journals/taco/NegiG13},\n  bibsource = {dblp computer science bibliography, https://dblp.org}\n}\n\n\n\n
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\n \n\n \n \n \n \n \n \n Techniques to improve performance in requester-wins hardware transactional memory.\n \n \n \n \n\n\n \n Armejach, A.; Titos-Gil, R.; Negi, A.; Unsal, O. S.; and Cristal, A.\n\n\n \n\n\n\n TACO, 10(4): 42:1–42:25. 2013.\n \n\n\n\n
\n\n\n\n \n \n \"TechniquesPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n  \n \n 1 download\n \n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@article{armejach:reqwins:taco:2013,\n  author    = {Adri{\\`{a}} Armejach and\n               Rub{\\'{e}}n Titos-Gil and\n               Anurag Negi and\n               Osman S. Unsal and\n               Adri{\\'{a}}n Cristal},\n  title     = {Techniques to improve performance in requester-wins hardware transactional\n               memory},\n  journal   = {{TACO}},\n  volume    = {10},\n  number    = {4},\n  pages     = {42:1--42:25},\n  year      = {2013},\n  url       = {http://ditec.um.es/~rtitos/papers/2013_taco-reqwins.pdf},\n  doi       = {10.1145/2541228.2555299},\n  timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},\n  biburl    = {https://dblp.org/rec/bib/journals/taco/ArmejachGNUC13},\n  bibsource = {dblp computer science bibliography, https://dblp.org}\n}\n\n\n\n
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\n \n\n \n \n \n \n \n \n Efficient Eager Management of Conflicts for Scalable Hardware Transactional Memory.\n \n \n \n \n\n\n \n Titos-Gil, R.; Acacio, M. E.; and García, J. M.\n\n\n \n\n\n\n IEEE Trans. Parallel Distrib. Syst., 24(1): 59–71. 2013.\n \n\n\n\n
\n\n\n\n \n \n \"EfficientPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@article{titos:dircd:tpds:2013,\n  author    = {Rub{\\'{e}}n Titos-Gil and\n               Manuel E. Acacio and\n               Jos{\\'{e}} M. Garc{\\'{\\i}}a},\n  title     = {Efficient Eager Management of Conflicts for Scalable Hardware Transactional\n               Memory},\n  journal   = {{IEEE} Trans. Parallel Distrib. Syst.},\n  volume    = {24},\n  number    = {1},\n  pages     = {59--71},\n  year      = {2013},\n  url       = {http://ditec.um.es/~rtitos/papers/2013_tpds-dircd.pdf},\n  doi       = {10.1109/TPDS.2012.103},\n  timestamp = {Fri, 02 Nov 2018 00:00:00 +0100},\n  biburl    = {https://dblp.org/rec/bib/journals/tpds/GilAG13},\n  bibsource = {dblp computer science bibliography, https://dblp.org}\n}\n\n\n\n
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\n \n\n \n \n \n \n \n \n Eager Beats Lazy: Improving Store Management in Eager Hardware Transactional Memory.\n \n \n \n \n\n\n \n Titos-Gil, R.; Negi, A.; Acacio, M. E.; García, J. M.; and Stenström, P.\n\n\n \n\n\n\n IEEE Trans. Parallel Distrib. Syst., 24(11): 2192–2201. 2013.\n \n\n\n\n
\n\n\n\n \n \n \"EagerPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n  \n \n 1 download\n \n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@article{titos:eagerbeatslazy:tpds:2013,\n  author    = {Rub{\\'{e}}n Titos-Gil and\n               Anurag Negi and\n               Manuel E. Acacio and\n               Jos{\\'{e}} M. Garc{\\'{\\i}}a and\n               Per Stenstr{\\"{o}}m},\n  title     = {Eager Beats Lazy: Improving Store Management in Eager Hardware Transactional\n               Memory},\n  journal   = {{IEEE} Trans. Parallel Distrib. Syst.},\n  volume    = {24},\n  number    = {11},\n  pages     = {2192--2201},\n  year      = {2013},\n  url       = {http://ditec.um.es/~rtitos/papers/2013_tpds-eagerbeatslazy.pdf},\n  doi       = {10.1109/TPDS.2012.315},\n  timestamp = {Fri, 02 Nov 2018 00:00:00 +0100},\n  biburl    = {https://dblp.org/rec/bib/journals/tpds/GilNAGS13},\n  bibsource = {dblp computer science bibliography, https://dblp.org}\n}\n\n\n\n
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\n  \n 2012\n \n \n (3)\n \n \n
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\n \n\n \n \n \n \n \n \n Hardware transactional memory with software-defined conflicts.\n \n \n \n \n\n\n \n Titos-Gil, R.; Acacio, M. E.; García, J. M.; Harris, T.; Cristal, A.; Unsal, O. S.; Hur, I.; and Valero, M.\n\n\n \n\n\n\n TACO, 8(4): 31:1–31:20. 2012.\n \n\n\n\n
\n\n\n\n \n \n \"HardwarePaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@article{titos:swdef:taco:2012,\n  author    = {Rub{\\'{e}}n Titos-Gil and\n               Manuel E. Acacio and\n               Jos{\\'{e}} M. Garc{\\'{\\i}}a and\n               Tim Harris and\n               Adri{\\'{a}}n Cristal and\n               Osman S. Unsal and\n               Ibrahim Hur and\n               Mateo Valero},\n  title     = {Hardware transactional memory with software-defined conflicts},\n  journal   = {{TACO}},\n  volume    = {8},\n  number    = {4},\n  pages     = {31:1--31:20},\n  year      = {2012},\n  url       = {http://ditec.um.es/~rtitos/papers/2012_taco.pdf},\n  doi       = {10.1145/2086696.2086710},\n  timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},\n  biburl    = {https://dblp.org/rec/bib/journals/taco/GilAGHCUHV12},\n  bibsource = {dblp computer science bibliography, https://dblp.org}\n}\n\n\n\n
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\n \n\n \n \n \n \n \n \n \\(π\\)-TM: Pessimistic invalidation for scalable lazy hardware transactional memory.\n \n \n \n \n\n\n \n Negi, A.; Titos-Gil, R.; Acacio, M. E.; García, J. M.; and Stenström, P.\n\n\n \n\n\n\n In 18th IEEE International Symposium on High Performance Computer Architecture, HPCA 2012, New Orleans, LA, USA, 25-29 February, 2012, pages 141–152, 2012. \n \n\n\n\n
\n\n\n\n \n \n \"\\(π\\)-TM:Paper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n  \n \n 1 download\n \n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{negi:pitm:hpca:2012,\n  author    = {Anurag Negi and\n               Rub{\\'{e}}n Titos-Gil and\n               Manuel E. Acacio and\n               Jos{\\'{e}} M. Garc{\\'{\\i}}a and\n               Per Stenstr{\\"{o}}m},\n  title     = {{\\(\\pi\\)}-TM: Pessimistic invalidation for scalable lazy hardware\n               transactional memory},\n  booktitle = {18th {IEEE} International Symposium on High Performance Computer Architecture,\n               {HPCA} 2012, New Orleans, LA, USA, 25-29 February, 2012},\n  pages     = {141--152},\n  year      = {2012},\n  crossref  = {DBLP:conf/hpca/2012},\n  url       = {http://ditec.um.es/~rtitos/papers/2012_hpca.pdf},\n  doi       = {10.1109/HPCA.2012.6168951},\n  timestamp = {Fri, 02 Nov 2018 00:00:00 +0100},\n  biburl    = {https://dblp.org/rec/bib/conf/hpca/NegiGAGS12},\n  bibsource = {dblp computer science bibliography, https://dblp.org}\n}\n\n\n\n
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\n \n\n \n \n \n \n \n \n Dynamic Serialization: Improving Energy Consumption in Eager-Eager Hardware Transactional Memory Systems.\n \n \n \n \n\n\n \n Gaona-Ramírez, E.; Titos-Gil, R.; Acacio, M. E.; and Fernández, J.\n\n\n \n\n\n\n In Proceedings of the 20th Euromicro International Conference on Parallel, Distributed and Network-Based Processing, PDP 2012, Munich, Germany, February 15-17, 2012, pages 221–228, 2012. \n \n\n\n\n
\n\n\n\n \n \n \"DynamicPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/pdp/Gaona-RamirezGAF12,\n  author    = {Epifanio Gaona{-}Ram{\\'{\\i}}rez and\n               Rub{\\'{e}}n Titos-Gil and\n               Manuel E. Acacio and\n               Juan Fern{\\'{a}}ndez},\n  title     = {Dynamic Serialization: Improving Energy Consumption in Eager-Eager\n               Hardware Transactional Memory Systems},\n  booktitle = {Proceedings of the 20th Euromicro International Conference on Parallel,\n               Distributed and Network-Based Processing, {PDP} 2012, Munich, Germany,\n               February 15-17, 2012},\n  pages     = {221--228},\n  year      = {2012},\n  crossref  = {DBLP:conf/pdp/2012},\n  url       = {http://ditec.um.es/~rtitos/papers/2012_pdp.pdf},\n  doi       = {10.1109/PDP.2012.76},\n  timestamp = {Fri, 02 Nov 2018 00:00:00 +0100},\n  biburl    = {https://dblp.org/rec/bib/conf/pdp/Gaona-RamirezGAF12},\n  bibsource = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n  \n 2011\n \n \n (5)\n \n \n
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\n \n\n \n \n \n \n \n \n Pi-TM: Pessimistic Invalidation for Scalable Lazy Hardware Transactional Memory.\n \n \n \n \n\n\n \n Negi, A.; Stenström, P.; Titos-Gil, R.; Acacio, M. E.; and García, J. M.\n\n\n \n\n\n\n In 2011 International Conference on Parallel Architectures and Compilation Techniques, PACT 2011, Galveston, TX, USA, October 10-14, 2011, pages 203–204, 2011. \n \n\n\n\n
\n\n\n\n \n \n \"Pi-TM:Paper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{negi:pitm:pact:2011,\n  author    = {Anurag Negi and\n               Per Stenstr{\\"{o}}m and\n               Rub{\\'{e}}n Titos-Gil and\n               Manuel E. Acacio and\n               Jos{\\'{e}} M. Garc{\\'{\\i}}a},\n  title     = {Pi-TM: Pessimistic Invalidation for Scalable Lazy Hardware Transactional\n               Memory},\n  booktitle = {2011 International Conference on Parallel Architectures and Compilation\n               Techniques, {PACT} 2011, Galveston, TX, USA, October 10-14, 2011},\n  pages     = {203--204},\n  year      = {2011},\n  crossref  = {DBLP:conf/IEEEpact/2011},\n  url       = {http://ditec.um.es/~rtitos/papers/2011_pact-poster.pdf},\n  doi       = {10.1109/PACT.2011.41},\n  timestamp = {Fri, 02 Nov 2018 00:00:00 +0100},\n  biburl    = {https://dblp.org/rec/bib/conf/IEEEpact/NegiSGAG11},\n  bibsource = {dblp computer science bibliography, https://dblp.org}\n}\n\n\n\n
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\n \n\n \n \n \n \n \n \n Using a Reconfigurable L1 Data Cache for Efficient Version Management in Hardware Transactional Memory.\n \n \n \n \n\n\n \n Armejach, A.; Seyedi, A.; Titos-Gil, R.; Hur, I.; Cristal, A.; Unsal, O. S.; and Valero, M.\n\n\n \n\n\n\n In 2011 International Conference on Parallel Architectures and Compilation Techniques, PACT 2011, Galveston, TX, USA, October 10-14, 2011, pages 361–371, 2011. \n \n\n\n\n
\n\n\n\n \n \n \"UsingPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{armejach:reconfig:pact:2011,\n  author    = {Adri{\\`{a}} Armejach and\n               Azam Seyedi and\n               Rub{\\'{e}}n Titos-Gil and\n               Ibrahim Hur and\n               Adri{\\'{a}}n Cristal and\n               Osman S. Unsal and\n               Mateo Valero},\n  title     = {Using a Reconfigurable {L1} Data Cache for Efficient Version Management\n               in Hardware Transactional Memory},\n  booktitle = {2011 International Conference on Parallel Architectures and Compilation\n               Techniques, {PACT} 2011, Galveston, TX, USA, October 10-14, 2011},\n  pages     = {361--371},\n  year      = {2011},\n  crossref  = {DBLP:conf/IEEEpact/2011},\n  url       = {http://ditec.um.es/~rtitos/papers/2011_pact.pdf},\n  doi       = {10.1109/PACT.2011.67},\n  timestamp = {Fri, 02 Nov 2018 00:00:00 +0100},\n  biburl    = {https://dblp.org/rec/bib/conf/IEEEpact/ArmejachSGHCUV11},\n  bibsource = {dblp computer science bibliography, https://dblp.org}\n}\n\n\n\n
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\n \n\n \n \n \n \n \n \n Eager Meets Lazy: The Impact of Write-Buffering on Hardware Transactional Memory.\n \n \n \n \n\n\n \n Negi, A.; Titos-Gil, R.; Acacio, M. E.; García, J. M.; and Stenström, P.\n\n\n \n\n\n\n In International Conference on Parallel Processing, ICPP 2011, Taipei, Taiwan, September 13-16, 2011, pages 73–82, 2011. \n \n\n\n\n
\n\n\n\n \n \n \"EagerPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n  \n \n 1 download\n \n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{negi:eagermeetslazy:icpp:2011,\n  author    = {Anurag Negi and\n               Rub{\\'{e}}n Titos-Gil and\n               Manuel E. Acacio and\n               Jos{\\'{e}} M. Garc{\\'{\\i}}a and\n               Per Stenstr{\\"{o}}m},\n  title     = {Eager Meets Lazy: The Impact of Write-Buffering on Hardware Transactional\n               Memory},\n  booktitle = {International Conference on Parallel Processing, {ICPP} 2011, Taipei,\n               Taiwan, September 13-16, 2011},\n  pages     = {73--82},\n  year      = {2011},\n  crossref  = {DBLP:conf/icpp/2011},\n  url       = {http://ditec.um.es/~rtitos/papers/2011_icpp.pdf},\n  doi       = {10.1109/ICPP.2011.63},\n  timestamp = {Fri, 02 Nov 2018 00:00:00 +0100},\n  biburl    = {https://dblp.org/rec/bib/conf/icpp/NegiGAGS11},\n  bibsource = {dblp computer science bibliography, https://dblp.org}\n}\n\n\n\n
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\n \n\n \n \n \n \n \n \n ZEBRA: a data-centric, hybrid-policy hardware transactional memory design.\n \n \n \n \n\n\n \n Titos-Gil, R.; Negi, A.; Acacio, M. E.; García, J. M.; and Stenström, P.\n\n\n \n\n\n\n In Proceedings of the 25th International Conference on Supercomputing, 2011, Tucson, AZ, USA, May 31 - June 04, 2011, pages 53–62, 2011. \n \n\n\n\n
\n\n\n\n \n \n \"ZEBRA:Paper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n  \n \n 2 downloads\n \n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{titos:zebra:ics:2011,\n  author    = {Rub{\\'{e}}n Titos-Gil and\n               Anurag Negi and\n               Manuel E. Acacio and\n               Jos{\\'{e}} M. Garc{\\'{\\i}}a and\n               Per Stenstr{\\"{o}}m},\n  title     = {{ZEBRA:} a data-centric, hybrid-policy hardware transactional memory\n               design},\n  booktitle = {Proceedings of the 25th International Conference on Supercomputing,\n               2011, Tucson, AZ, USA, May 31 - June 04, 2011},\n  pages     = {53--62},\n  year      = {2011},\n  crossref  = {DBLP:conf/ics/2011},\n  url       = {http://ditec.um.es/~rtitos/papers/2011_ics.pdf},\n  doi       = {10.1145/1995896.1995906},\n  timestamp = {Tue, 06 Nov 2018 11:07:03 +0100},\n  biburl    = {https://dblp.org/rec/bib/conf/ics/GilNAGS11},\n  bibsource = {dblp computer science bibliography, https://dblp.org}\n}\n\n\n\n
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\n \n\n \n \n \n \n \n \n The Impact of Non-coherent Buffers on Lazy Hardware Transactional Memory Systems.\n \n \n \n \n\n\n \n Negi, A.; Titos-Gil, R.; Acacio, M. E.; García, J. M.; and Stenström, P.\n\n\n \n\n\n\n In 25th IEEE International Symposium on Parallel and Distributed Processing, IPDPS 2011, Anchorage, Alaska, USA, 16-20 May 2011 - Workshop Proceedings, pages 700–707, 2011. \n \n\n\n\n
\n\n\n\n \n \n \"ThePaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{negi:impact:ipdpsw:2011,\n  author    = {Anurag Negi and\n               Rub{\\'{e}}n Titos-Gil and\n               Manuel E. Acacio and\n               Jos{\\'{e}} M. Garc{\\'{\\i}}a and\n               Per Stenstr{\\"{o}}m},\n  title     = {The Impact of Non-coherent Buffers on Lazy Hardware Transactional\n               Memory Systems},\n  booktitle = {25th {IEEE} International Symposium on Parallel and Distributed Processing,\n               {IPDPS} 2011, Anchorage, Alaska, USA, 16-20 May 2011 - Workshop Proceedings},\n  pages     = {700--707},\n  year      = {2011},\n  crossref  = {DBLP:conf/ipps/2011w},\n  url       = {http://ditec.um.es/~rtitos/papers/2011_ipdpsw.pdf},\n  doi       = {10.1109/IPDPS.2011.205},\n  timestamp = {Fri, 02 Nov 2018 00:00:00 +0100},\n  biburl    = {https://dblp.org/rec/bib/conf/ipps/NegiGAGS11},\n  bibsource = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n  \n 2010\n \n \n (1)\n \n \n
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\n \n\n \n \n \n \n \n \n Characterizing Energy Consumption in Hardware Transactional Memory Systems.\n \n \n \n \n\n\n \n Gaona-Ramírez, E.; Titos-Gil, R.; Fernández, J.; and Acacio, M. E.\n\n\n \n\n\n\n In 22st International Symposium on Computer Architecture and High Performance Computing, SBAC-PAD 2010, Petropolis, Brazil, October 27-30, 2010, pages 9–16, 2010. \n \n\n\n\n
\n\n\n\n \n \n \"CharacterizingPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{gaona:charact:sbac-pad:2010,\n  author    = {Epifanio Gaona{-}Ram{\\'{\\i}}rez and\n               Rub{\\'{e}}n Titos-Gil and\n               Juan Fern{\\'{a}}ndez and\n               Manuel E. Acacio},\n  title     = {Characterizing Energy Consumption in Hardware Transactional Memory\n               Systems},\n  booktitle = {22st International Symposium on Computer Architecture and High Performance\n               Computing, {SBAC-PAD} 2010, Petropolis, Brazil, October 27-30, 2010},\n  pages     = {9--16},\n  year      = {2010},\n  crossref  = {DBLP:conf/sbac-pad/2010},\n  url       = {http://ditec.um.es/~rtitos/papers/2010_sbac-pad.pdf},\n  doi       = {10.1109/SBAC-PAD.2010.11},\n  timestamp = {Fri, 02 Nov 2018 00:00:00 +0100},\n  biburl    = {https://dblp.org/rec/bib/conf/sbac-pad/Gaona-RamirezTFA10},\n  bibsource = {dblp computer science bibliography, https://dblp.org}\n}\n\n\n
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\n  \n 2009\n \n \n (1)\n \n \n
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\n \n\n \n \n \n \n \n \n Speculation-based conflict resolution in hardware transactional memory.\n \n \n \n \n\n\n \n Titos-Gil, R.; Acacio, M. E.; and Carrasco, J. M. G.\n\n\n \n\n\n\n In 23rd IEEE International Symposium on Parallel and Distributed Processing, IPDPS 2009, Rome, Italy, May 23-29, 2009, pages 1–12, 2009. \n \n\n\n\n
\n\n\n\n \n \n \"Speculation-basedPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n  \n \n 2 downloads\n \n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{titos:speculation:ipdps:2009,\n  author    = {Rub{\\'{e}}n Titos-Gil and\n               Manuel E. Acacio and\n               Jos{\\'{e}} Manuel Garc{\\'{\\i}}a Carrasco},\n  title     = {Speculation-based conflict resolution in hardware transactional memory},\n  booktitle = {23rd {IEEE} International Symposium on Parallel and Distributed Processing,\n               {IPDPS} 2009, Rome, Italy, May 23-29, 2009},\n  pages     = {1--12},\n  year      = {2009},\n  crossref  = {DBLP:conf/ipps/2009},\n  url       = {http://ditec.um.es/~rtitos/papers/2009_ipdps.pdf},\n  doi       = {10.1109/IPDPS.2009.5161021},\n  timestamp = {Fri, 02 Nov 2018 00:00:00 +0100},\n  biburl    = {https://dblp.org/rec/bib/conf/ipps/GilAC09},\n  bibsource = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n  \n 2008\n \n \n (2)\n \n \n
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\n \n\n \n \n \n \n \n \n Directory-Based Conflict Detection in Hardware Transactional Memory.\n \n \n \n \n\n\n \n Titos-Gil, R.; Acacio, M. E.; and García, J. M.\n\n\n \n\n\n\n In High Performance Computing - HiPC 2008, 15th International Conference, Bangalore, India, December 17-20, 2008. Proceedings, pages 541–554, 2008. \n \n\n\n\n
\n\n\n\n \n \n \"Directory-BasedPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{titos:dircd:hipc:2008,\n  author    = {Rub{\\'{e}}n Titos-Gil and\n               Manuel E. Acacio and\n               Jos{\\'{e}} M. Garc{\\'{\\i}}a},\n  title     = {Directory-Based Conflict Detection in Hardware Transactional Memory},\n  booktitle = {High Performance Computing - HiPC 2008, 15th International Conference,\n               Bangalore, India, December 17-20, 2008. Proceedings},\n  pages     = {541--554},\n  year      = {2008},\n  crossref  = {DBLP:conf/hipc/2008},\n  url       = {http://ditec.um.es/~rtitos/papers/2008_hipc.pdf},\n  doi       = {10.1007/978-3-540-89894-8\\_47},\n  timestamp = {Fri, 02 Nov 2018 00:00:00 +0100},\n  biburl    = {https://dblp.org/rec/bib/conf/hipc/GilAG08},\n  bibsource = {dblp computer science bibliography, https://dblp.org}\n}\n\n\n\n
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\n \n\n \n \n \n \n \n \n Characterization of Conflicts in Log-Based Transactional Memory (LogTM).\n \n \n \n \n\n\n \n Titos-Gil, R.; Acacio, M. E.; and Carrasco, J. M. G.\n\n\n \n\n\n\n In 16th Euromicro International Conference on Parallel, Distributed and Network-Based Processing (PDP 2008), 13-15 February 2008, Toulouse, France, pages 30–37, 2008. \n \n\n\n\n
\n\n\n\n \n \n \"CharacterizationPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{titos:characterization:pdp:2008,\n  author    = {Rub{\\'{e}}n Titos-Gil and\n               Manuel E. Acacio and\n               Jos{\\'{e}} Manuel Garc{\\'{\\i}}a Carrasco},\n  title     = {Characterization of Conflicts in Log-Based Transactional Memory (LogTM)},\n  booktitle = {16th Euromicro International Conference on Parallel, Distributed and\n               Network-Based Processing {(PDP} 2008), 13-15 February 2008, Toulouse,\n               France},\n  pages     = {30--37},\n  year      = {2008},\n  crossref  = {DBLP:conf/pdp/2008},\n  url       = {http://ditec.um.es/~rtitos/papers/2008_pdp.pdf},\n  doi       = {10.1109/PDP.2008.63},\n  timestamp = {Fri, 02 Nov 2018 00:00:00 +0100},\n  biburl    = {https://dblp.org/rec/bib/conf/pdp/GilSC08},\n  bibsource = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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