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\n  \n 2023\n \n \n (3)\n \n \n
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\n \n\n \n \n \n \n \n EnergyAnalyzer: Using Static WCET Analysis Techniques to Estimate the Energy Consumption of Embedded Applications.\n \n \n \n\n\n \n Wegener, S.; Nikov, K. K.; Núñez-Yáñez, J. L.; and Eder, K.\n\n\n \n\n\n\n , 114: 9:1–9:14. 2023.\n Accepted for publication\n\n\n\n
\n\n\n\n \n\n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@article{WegenerNNE2023,\r\nauthor = {Simon Wegener and\r\nKris K. Nikov and\r\nJos{\\'{e}} L. N{\\'{u}}{\\~{n}}ez{-}Y{\\'{a}}{\\~{n}}ez and Kerstin Eder}, title = {EnergyAnalyzer: Using Static {WCET} Analysis Techniques to Estimate the Energy Consumption of Embedded Applications}, booktitle = {21th International Workshop on Worst-Case Execution Time Analysis (WCET 2023)}, pages = {9:1--9:14}, series = {OpenAccess Series in Informatics (OASIcs)}, year = {2023}, volume = {114}, editor = {Peter W{\\"a}gemann}, publisher = {Schloss Dagstuhl--Leibniz-Zentrum fuer Informatik}, address = {Dagstuhl, Germany}, note = {Accepted for publication} }\r\n\r\n\r\n
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\n \n\n \n \n \n \n \n Efficient and Effective Multi-Objective Optimization for Real-Time Multi-Task Systems.\n \n \n \n\n\n \n Jadhav, S.; and Falk, H.\n\n\n \n\n\n\n In 21st International Workshop on Worst-Case Execution Time Analysis (WCET 2023), Vienna, Austria, July 2023. \n Accepted for publication.\n\n\n\n
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@inproceedings{jadhav2023wcetefficient,\r\n  title={Efficient and Effective Multi-Objective Optimization for Real-Time Multi-Task Systems},\r\n  author={Jadhav, Shashank and Falk, Heiko},\r\n  booktitle={21st International Workshop on Worst-Case Execution Time Analysis (WCET 2023)},\r\n  month= {July},\r\n  year={2023},\r\n  address = {Vienna, Austria},\r\n  note = {Accepted for publication.}\r\n}\r\n\r\n
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\n \n\n \n \n \n \n \n The TeamPlay Project: Analysing and Optimising Time, Energy, and Security for Cyber-Physical Systems.\n \n \n \n\n\n \n Rouxel, B.; Brown, C.; Ebeid, E.; Eder, K.; Falk, H.; Grelck, C.; Holst, J.; Jadhav, S.; Marquer, Y.; Alejandro, M. M. D.; Nikov, K.; Sahafi, A.; Lundquist, U. P. S.; Seewald, A.; Vassalos, V.; Wegener, S.; and Zendra, O.\n\n\n \n\n\n\n In Proceedings of DATE '23: Design, Automation and Test in Europe, Antwerp , Belgium, April 2023. \n Accepted for publication.\n\n\n\n
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@inproceedings{teamplay-date-23,\r\n  title = {The {TeamPlay} Project: Analysing and Optimising Time, Energy, and Security for Cyber-Physical Systems},\r\n  author = {Benjamin Rouxel and Christopher Brown and Emad Ebeid and Kerstin Eder and Heiko Falk and Clemens Grelck and Jesper Holst and Shashank Jadhav and Yoann Marquer and Marcos Martinez De Alejandro and Kris Nikov and Ali Sahafi and Ulrik Pagh Schultz Lundquist and Adam Seewald and Vangelis Vassalos and Simon Wegener and Olivier Zendra},\r\n  booktitle = {Proceedings of DATE '23: Design, Automation and Test in Europe},\r\n month = {April},\r\n  year = 2023,\r\n  address = {Antwerp , Belgium},\r\n  note = {Accepted for publication.},\r\n}\r\n\r\n
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\n  \n 2022\n \n \n (1)\n \n \n
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\n \n\n \n \n \n \n \n Approximating WCET and energy consumption for fast multi-objective memory allocation.\n \n \n \n\n\n \n Jadhav, S.; and Falk, H.\n\n\n \n\n\n\n In Proceedings of the 30th International Conference on Real-Time Networks and Systems, pages 162–172, 2022. \n \n\n\n\n
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@inproceedings{jadhav2022approximating,\r\n  title={Approximating WCET and energy consumption for fast multi-objective memory allocation},\r\n  author={Jadhav, Shashank and Falk, Heiko},\r\n  booktitle={Proceedings of the 30th International Conference on Real-Time Networks and Systems},\r\n  pages={162--172},\r\n  year={2022}\r\n}\r\n\r\n
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\n  \n 2021\n \n \n (5)\n \n \n
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\n \n\n \n \n \n \n \n \n Power Passports for Fault Tolerance: Anomaly Detection in Industrial CPS Using Electrical EFB.\n \n \n \n \n\n\n \n Odyurt, U.; Roeder, J.; Pimentel, A. D.; Alonso, I. G.; and de Laat, C.\n\n\n \n\n\n\n In 2021 4th IEEE International Conference on Industrial Cyber-Physical Systems (ICPS), pages 152–157, 2021. \n \n\n\n\n
\n\n\n\n \n \n \"PowerPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n  \n \n 7 downloads\n \n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{9468262,\r\n  title = {Power Passports for Fault Tolerance: Anomaly Detection in Industrial CPS Using Electrical EFB},\r\n  author = {Odyurt, Uraz and Roeder, Julius and Pimentel, Andy D. and Alonso, Ignacio Gonzalez and de Laat, Cees},\r\n  year = 2021,\r\n  booktitle = {2021 4th IEEE International Conference on Industrial Cyber-Physical Systems (ICPS)},\r\n  pages = {152--157},\r\n  doi = {10.1109/ICPS49255.2021.9468262},\r\n  url = {https://staff.fnwi.uva.nl/a.d.pimentel/artemis/ieee_icps_paper.pdf}\r\n}\r\n\r\n
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\n \n\n \n \n \n \n \n \n GR712RC LEON3 Power Model Data.\n \n \n \n \n\n\n \n Nikov, K.; Martinez, M.; Vallejo, P.; Balbis, A.; Nunez-Yanez, J.; and Eder, K.\n\n\n \n\n\n\n IEEE Dataport, 2021.\n \n\n\n\n
\n\n\n\n \n \n \"GR712RCPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n  \n \n 12 downloads\n \n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@misc{l3fgrainmodeldata,\r\n  title = {{GR712RC} {LEON3} {P}ower {M}odel {D}ata},\r\n  author = {Nikov, Kris and Martinez, Marcos and Vallejo, Pedro and Balbis, Abel and Nunez-Yanez, Jose and Eder, Kerstin},\r\n  year = 2021,\r\n  doi = {10.21227/1y7r-am78},\r\n  url = {https://dx.doi.org/10.21227/1y7r-am78},\r\n  howpublished = {IEEE Dataport}\r\n}\r\n\r\n
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\n \n\n \n \n \n \n \n \n Energy-Aware Scheduling of Multi-Version Tasks on Heterogeneous Real-Time Systems.\n \n \n \n \n\n\n \n Roeder, J.; Rouxel, B.; Altmeyer, S.; and Grelck, C.\n\n\n \n\n\n\n In Proceedings of the 36th Annual ACM Symposium on Applied Computing, of SAC '21, pages 501–510, New York, NY, USA, 2021. Association for Computing Machinery\n \n\n\n\n
\n\n\n\n \n \n \"Energy-AwarePaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n  \n \n abstract \n \n\n \n  \n \n 4 downloads\n \n \n\n \n \n \n \n \n \n \n\n  \n \n \n \n \n \n \n \n \n \n \n\n\n\n
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@inproceedings{10.1145/3412841.3441930,\r\n  title = {Energy-Aware Scheduling of Multi-Version Tasks on Heterogeneous Real-Time Systems},\r\n  author = {Roeder, Julius and Rouxel, Benjamin and Altmeyer, Sebastian and Grelck, Clemens},\r\n  year = 2021,\r\n  booktitle = {Proceedings of the 36th Annual ACM Symposium on Applied Computing},\r\n  location = {Virtual Event, Republic of Korea},\r\n  publisher = {Association for Computing Machinery},\r\n  address = {New York, NY, USA},\r\n  series = {SAC '21},\r\n  pages = {501–510},\r\n  doi = {10.1145/3412841.3441930},\r\n  isbn = 9781450381048,\r\n  url = {https://www.lexuor.net/publications/SAC_2021__Energy_aware_heterogeneous_scheduling.pdf},\r\n  abstract = {The emergence of battery-powered devices has led to an increase of interest in the energy consumption of computing devices. For embedded systems, dispatching the workload on different computing units enables the optimisation of the overall energy consumption on high-performance heterogeneous platforms. However, to use the full power of heterogeneity, architecture specific binary blocks are required, each with different energy/time trade-offs. Finding a scheduling strategy that minimises the energy consumption, while guaranteeing timing constraints creates new challenges. These challenges can only be met by using the full heterogeneous capacity of the platform (e.g. heterogeneous CPU, GPU, DVFS, dynamic frequency changes from within an application).We propose an off-line scheduling algorithm for dependent multiversion tasks based on Forward List Scheduling to minimise the overall energy consumption. Our heuristic accounts for Dynamic Voltage and Frequency Scaling (DVFS) and enables applications to dynamically adapt voltage and frequency during run time. We demonstrate the benefits of multi-version task models coupled with an energy-aware scheduler. We observe that selecting the most energy efficient version for each task does not lead to the lowest energy consumption for the whole application. Then we show that our approach produces schedules that are on average 45.6% more energy efficient than schedules produced by a state-of-the-art scheduling algorithm. Next we compare our heuristic against an optimal solution derived by an Integer Linear Programming (ILP) formulation (deviation of 1.6% on average). Lastly, we empirically show that the energy consumption predicted by our scheduler is close to the actual measured energy consumption on a Odroid-XU4 board (at most-15.8%).},\r\n  numpages = 10,\r\n  keywords = {energy-aware scheduling, DAG, multi-version, DVFS}\r\n}\r\n\r\n
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\n The emergence of battery-powered devices has led to an increase of interest in the energy consumption of computing devices. For embedded systems, dispatching the workload on different computing units enables the optimisation of the overall energy consumption on high-performance heterogeneous platforms. However, to use the full power of heterogeneity, architecture specific binary blocks are required, each with different energy/time trade-offs. Finding a scheduling strategy that minimises the energy consumption, while guaranteeing timing constraints creates new challenges. These challenges can only be met by using the full heterogeneous capacity of the platform (e.g. heterogeneous CPU, GPU, DVFS, dynamic frequency changes from within an application).We propose an off-line scheduling algorithm for dependent multiversion tasks based on Forward List Scheduling to minimise the overall energy consumption. Our heuristic accounts for Dynamic Voltage and Frequency Scaling (DVFS) and enables applications to dynamically adapt voltage and frequency during run time. We demonstrate the benefits of multi-version task models coupled with an energy-aware scheduler. We observe that selecting the most energy efficient version for each task does not lead to the lowest energy consumption for the whole application. Then we show that our approach produces schedules that are on average 45.6% more energy efficient than schedules produced by a state-of-the-art scheduling algorithm. Next we compare our heuristic against an optimal solution derived by an Integer Linear Programming (ILP) formulation (deviation of 1.6% on average). Lastly, we empirically show that the energy consumption predicted by our scheduler is close to the actual measured energy consumption on a Odroid-XU4 board (at most-15.8%).\n
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\n \n\n \n \n \n \n \n \n Robust and accurate fine-grain power models for embedded systems with no on-chip PMU.\n \n \n \n \n\n\n \n Nikov, K.; Martinez, M.; Chamski, Z.; Georgiou, K.; Nunez-Yanez, J.; and Eder, K.\n\n\n \n\n\n\n arXiv preprint:2106.00565. 2021.\n \n\n\n\n
\n\n\n\n \n \n \"RobustPaper\n  \n \n\n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n  \n \n 7 downloads\n \n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@article{nikov2021robust,\r\n  title = {Robust and accurate fine-grain power models for embedded systems with no on-chip {PMU}},\r\n  author = {Nikov, Kris and Martinez, Marcos and Chamski, Zbigniew and Georgiou, Kyriakos and Nunez-Yanez, Jose and Eder, Kerstin},\r\n  year = 2021,\r\n  journal = {arXiv preprint:2106.00565},\r\n  url = {https://arxiv.org/abs/2106.00565}\r\n}\r\n\r\n
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\n \n\n \n \n \n \n \n \n Scheduling DAGs of Multi-version Multi-phase Tasks on Heterogeneous Real-time Systems.\n \n \n \n \n\n\n \n Roeder, J.; Rouxel, B.; and Grelck, C.\n\n\n \n\n\n\n In 14th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC 2021), Singapore, 2021. IEEE\n to appear\n\n\n\n
\n\n\n\n \n \n \"SchedulingPaper\n  \n \n\n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{RoedRouxGrel21,\r\n  title = {Scheduling DAGs of Multi-version Multi-phase Tasks on Heterogeneous Real-time Systems},\r\n  author = {Julius Roeder and Benjamin Rouxel and Clemens Grelck},\r\n  year = 2021,\r\n  booktitle = {14th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC 2021), Singapore},\r\n  publisher = {IEEE},\r\n  url = {https://staff.fnwi.uva.nl/c.u.grelck/publications/2021_MCSoC21_multi_phase_scheduling.pdf},\r\n  note = {to appear}\r\n}\r\n\r\n
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\n  \n 2020\n \n \n (14)\n \n \n
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\n \n\n \n \n \n \n \n \n When Parallel Speedups Hit the Memory Wall.\n \n \n \n \n\n\n \n Furtunato, A. F. A.; Georgiou, K.; Eder, K.; and Xavier-De-Souza, S.\n\n\n \n\n\n\n IEEE Access, 8: 79225–79238. 2020.\n \n\n\n\n
\n\n\n\n \n \n \"WhenPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n  \n \n 15 downloads\n \n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@article{9078685,\r\n  title = {When Parallel Speedups Hit the Memory Wall},\r\n  author = {A. F. A. {Furtunato} and K. {Georgiou} and K. {Eder} and S. {Xavier-De-Souza}},\r\n  year = 2020,\r\n  journal = {IEEE Access},\r\n  volume = 8,\r\n  pages = {79225--79238},\r\n  doi = {10.1109/ACCESS.2020.2990418},\r\n  url = {https://arxiv.org/abs/1905.01234}\r\n}\r\n
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\n \n\n \n \n \n \n \n \n A Hole in the Ladder: Interleaved Variables in Iterative Conditional Branching.\n \n \n \n \n\n\n \n Marquer, Y.; and Richmond, T.\n\n\n \n\n\n\n In Proceedings of the 27th IEEE Symposium on Computer Arithmetic, ARITH-2020, pages 56–63, 2020. IEEE Xplore\n \n\n\n\n
\n\n\n\n \n \n \"APaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n  \n \n abstract \n \n\n \n  \n \n 5 downloads\n \n \n\n \n \n \n \n \n \n \n\n  \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n\n\n
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@inproceedings{MR20,\r\n  title = {{A Hole in the Ladder: Interleaved Variables in Iterative Conditional Branching}},\r\n  author = {Marquer, Yoann and Richmond, Tania},\r\n  year = 2020,\r\n  booktitle = {Proceedings of the 27th IEEE Symposium on Computer Arithmetic, ARITH-2020},\r\n  pages = {56--63},\r\n  doi = {10.1109/ARITH48897.2020.00017},\r\n  url = {https://hal.archives-ouvertes.fr/hal-02889212v1},\r\n  abstract = {The modular exponentiation is crucial to the RSA cryptographic protocol, and variants inspired by the Montgomery ladder have been studied to provide more secure algorithms. In this paper, we abstract away the iterative conditional branching used in the Montgomery ladder, and formalize systems of equations necessary to obtain what we call the semi-interleaved and fully-interleaved ladder properties. In particular, we design fault-injection attacks able to obtain bits of the secret against semi-interleaved ladders, including the Montgomery ladder, but not against fully-interleaved ladders that are more secure. We also apply these equations to extend the Montgomery ladder for both the semi- and fully-interleaved cases, thus proposing novel and more secure algorithms to compute the modular exponentiation.},\r\n  keywords = {Cryptography, Countermeasures (computer), Fault detection, Iterative algorithms, Public-key cryptography, Security, Side-channel attacks},\r\n  organization = {IEEE Xplore}\r\n}\r\n\r\n
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\n The modular exponentiation is crucial to the RSA cryptographic protocol, and variants inspired by the Montgomery ladder have been studied to provide more secure algorithms. In this paper, we abstract away the iterative conditional branching used in the Montgomery ladder, and formalize systems of equations necessary to obtain what we call the semi-interleaved and fully-interleaved ladder properties. In particular, we design fault-injection attacks able to obtain bits of the secret against semi-interleaved ladders, including the Montgomery ladder, but not against fully-interleaved ladders that are more secure. We also apply these equations to extend the Montgomery ladder for both the semi- and fully-interleaved cases, thus proposing novel and more secure algorithms to compute the modular exponentiation.\n
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\n \n\n \n \n \n \n \n \n Beyond Traditional Energy Planning: the Weight of Computations in Planetary Exploration.\n \n \n \n \n\n\n \n Seewald, A.\n\n\n \n\n\n\n In Proceedings of the IROS Workshop on Planetary Exploration Robots: Challenges and Opportunities (PlanRobo'20), pages 3, 2020. ETH Zürich\n \n\n\n\n
\n\n\n\n \n \n \"BeyondPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n  \n \n 4 downloads\n \n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{seewald2020beyond,\r\n  title = {Beyond Traditional Energy Planning: the Weight of Computations in Planetary Exploration},\r\n  author = {Seewald, Adam},\r\n  year = 2020,\r\n  booktitle = {Proceedings of the IROS Workshop on Planetary Exploration Robots: Challenges and Opportunities (PlanRobo'20)},\r\n  publisher = {ETH Z\\"urich},\r\n  pages = 3,\r\n  doi = {10.3929/ethz-b-000450120},\r\n  url = {https://adamseewald.cc/short/beyond2020}\r\n}\r\n\r\n
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\n \n\n \n \n \n \n \n \n Compiling for the Worst Case: Memory Allocation for Multi-task and Multi-core Hard Real-Time Systems.\n \n \n \n \n\n\n \n Luppold, A.; Oehlert, D.; and Falk, H.\n\n\n \n\n\n\n ACM Transactions on Embedded Computing Systems (TECS), 19(2). 2020.\n \n\n\n\n
\n\n\n\n \n \n \"CompilingPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n  \n \n 3 downloads\n \n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@article{Luppold:2020:TECS,\r\n  title = {{Compiling for the Worst Case: Memory Allocation for Multi-task and Multi-core Hard Real-Time Systems}},\r\n  author = {Luppold, Arno and Oehlert, Dominic and Falk, Heiko},\r\n  year = 2020,\r\n  journal = {ACM Transactions on Embedded Computing Systems (TECS)},\r\n  volume = 19,\r\n  number = 2,\r\n  doi = {10.1145/3381752},\r\n  url = {https://tore.tuhh.de/handle/11420/5356}\r\n}\r\n\r\n
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\n \n\n \n \n \n \n \n \n Intrinsic Resiliency of S-boxes Against Side-Channel Attacks - Best And Worst Scenarios.\n \n \n \n \n\n\n \n Carlet, C.; de Chérisey, É.; Guilley, S.; Kavut, S.; and Tang, D.\n\n\n \n\n\n\n IEEE Trans. Information Forensics and Security,16. 2020.\n \n\n\n\n
\n\n\n\n \n \n \"IntrinsicPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n  \n \n 11 downloads\n \n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@article{T-IFS-10757-2019,\r\n  title = {{Intrinsic Resiliency of S-boxes Against Side-Channel Attacks - Best And Worst Scenarios}},\r\n  author = {Claude Carlet and de Ch\\'erisey, \\'Eloi and Sylvain Guilley and Sel\\c{c}uk Kavut and Deng Tang},\r\n  year = 2020,\r\n  journal = {{IEEE} Trans. Information Forensics and Security},\r\n  pages = 16,\r\n  doi = {10.1109/TIFS.2020.3006399},\r\n  url = {https://hal-cnrs.archives-ouvertes.fr/hal-02915674}\r\n}\r\n\r\n
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\n \n\n \n \n \n \n \n \n Lost In Translation: Exposing Hidden Compiler Optimization Opportunities.\n \n \n \n \n\n\n \n Georgiou, K.; Chamski, Z.; Amaya Garcia, A.; May, D.; and Eder, K.\n\n\n \n\n\n\n The Computer Journal. 08 2020.\n bxaa103\n\n\n\n
\n\n\n\n \n \n Paper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n  \n \n abstract \n \n\n \n  \n \n 1 download\n \n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@article{10.1093/comjnl/bxaa103,\r\n  title = {{Lost In Translation: Exposing Hidden Compiler Optimization Opportunities}},\r\n  author = {Georgiou, Kyriakos and Chamski, Zbigniew and Amaya Garcia, Andres and May, David and Eder, Kerstin},\r\n  year = 2020,\r\n  month = {08},\r\n  journal = {The Computer Journal},\r\n  doi = {10.1093/comjnl/bxaa103},\r\n  issn = {0010-4620},\r\n  url = {https://arxiv.org/abs/1903.11397},\r\n  note = {bxaa103},\r\n  abstract = {{Existing iterative compilation and machine learning-based optimization techniques have been proven very successful in achieving better optimizations than the standard optimization levels of a compiler. However, they were not engineered to support the tuning of a compiler’s optimizer as part of the compiler’s daily development cycle. In this paper, we first establish the required properties that a technique must exhibit to enable such tuning. We then introduce an enhancement to the classic nightly routine testing of compilers, which exhibits all the required properties and thus is capable of driving the improvement and tuning of the compiler’s common optimizer. This is achieved by leveraging resource usage and compilation information collected while systematically exploiting prefixes of the transformations applied at standard optimization levels. Experimental evaluation using the LLVM v6.0.1 compiler demonstrated that the new approach was able to reveal hidden cross-architecture and architecture-dependent potential optimizations on two popular processors: the Intel i5-6300U and the Arm Cortex-A53-based Broadcom BCM2837 used in the Raspberry Pi 3B+. As a case study, we demonstrate how the insights from our approach enabled us to identify and remove a significant shortcoming of the CFG simplification pass of the LLVM v6.0.1 compiler.}},\r\n  eprint = {https://academic.oup.com/comjnl/advance-article-pdf/doi/10.1093/comjnl/bxaa103/33575064/bxaa103.pdf}\r\n}\r\n\r\n
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\n Existing iterative compilation and machine learning-based optimization techniques have been proven very successful in achieving better optimizations than the standard optimization levels of a compiler. However, they were not engineered to support the tuning of a compiler’s optimizer as part of the compiler’s daily development cycle. In this paper, we first establish the required properties that a technique must exhibit to enable such tuning. We then introduce an enhancement to the classic nightly routine testing of compilers, which exhibits all the required properties and thus is capable of driving the improvement and tuning of the compiler’s common optimizer. This is achieved by leveraging resource usage and compilation information collected while systematically exploiting prefixes of the transformations applied at standard optimization levels. Experimental evaluation using the LLVM v6.0.1 compiler demonstrated that the new approach was able to reveal hidden cross-architecture and architecture-dependent potential optimizations on two popular processors: the Intel i5-6300U and the Arm Cortex-A53-based Broadcom BCM2837 used in the Raspberry Pi 3B+. As a case study, we demonstrate how the insights from our approach enabled us to identify and remove a significant shortcoming of the CFG simplification pass of the LLVM v6.0.1 compiler.\n
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\n \n\n \n \n \n \n \n \n Detecting Faults in Inner Product Masking Scheme IPM-FD: IPM with Fault Detection (Extended version).\n \n \n \n \n\n\n \n Carlet, C.; Cheng, W.; Goli, K.; Danger, J.; and Guilley, S.\n\n\n \n\n\n\n Journal of Cryptographic Engineering,15. May 30 2020.\n DOI: 10.1007/s13389-020-00227-6\n\n\n\n
\n\n\n\n \n \n \"DetectingPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n  \n \n 4 downloads\n \n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@article{JCEN20_IPM,\r\n  title = {Detecting Faults in Inner Product Masking Scheme IPM-FD: IPM with Fault Detection (Extended version)},\r\n  author = {Claude Carlet and Wei Cheng and Kouassi Goli and Jean-Luc Danger and Sylvain Guilley},\r\n  year = 2020,\r\n  month = {May 30},\r\n  journal = {Journal of Cryptographic Engineering},\r\n  pages = 15,\r\n  doi = {10.1007/s13389-020-00227-6},\r\n  url = {https://hal-cnrs.archives-ouvertes.fr/hal-02915673},\r\n  note = {DOI: 10.1007/s13389-020-00227-6}\r\n}\r\n\r\n
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\n \n\n \n \n \n \n \n \n Energy-Aware Design of Vision-Based Autonomous Tracking and Landing of a UAV.\n \n \n \n \n\n\n \n Zamanakos, G.; Seewald, A.; Midtiby, H. S.; and Schultz, U. P.\n\n\n \n\n\n\n In 2020 Fourth IEEE International Conference on Robotic Computing (IRC), pages 294–297, 2020. IEEE\n \n\n\n\n
\n\n\n\n \n \n \"Energy-AwarePaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n  \n \n 4 downloads\n \n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{zamanakos2020energy,\r\n  title = {Energy-Aware Design of Vision-Based Autonomous Tracking and Landing of a UAV},\r\n  author = {Zamanakos, Georgios and Seewald, Adam and Midtiby, Henrik Skov and Schultz, Ulrik Pagh},\r\n  year = 2020,\r\n  booktitle = {2020 Fourth IEEE International Conference on Robotic Computing (IRC)},\r\n  pages = {294--297},\r\n  doi = {10.1109/IRC.2020.00054},\r\n  url = {https://adamseewald.cc/short/energy2020},\r\n  organization = {IEEE}\r\n}\r\n\r\n
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\n \n\n \n \n \n \n \n \n Mechanical and Computational Energy Estimation of a Fixed-Wing Drone.\n \n \n \n \n\n\n \n Seewald, A.; Garcia de Marina, H.; Midtiby, H. S.; and Schultz, U. P.\n\n\n \n\n\n\n In 2020 Fourth IEEE International Conference on Robotic Computing (IRC), pages 135–142, 2020. IEEE\n \n\n\n\n
\n\n\n\n \n \n \"MechanicalPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n  \n \n 4 downloads\n \n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{seewald2020mechanical,\r\n  title = {Mechanical and Computational Energy Estimation of a Fixed-Wing Drone},\r\n  author = {Seewald, Adam and Garcia de Marina, Hector and Midtiby, Henrik Skov and Schultz, Ulrik Pagh},\r\n  year = 2020,\r\n  booktitle = {2020 Fourth IEEE International Conference on Robotic Computing (IRC)},\r\n  pages = {135--142},\r\n  doi = {10.1109/IRC.2020.00028},\r\n  url = {https://adamseewald.cc/short/mechanical2020},\r\n  organization = {IEEE}\r\n}\r\n\r\n
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\n \n\n \n \n \n \n \n \n Performance and Energy Trade-Offs for Parallel Applications on Heterogeneous Multi-Processing Systems.\n \n \n \n \n\n\n \n Coutinho Demetrios, A. M.; De Sensi, D.; Lorenzon, A. F.; Georgiou, K.; Nunez-Yanez, J.; Eder, K.; and Xavier-de-Souza, S.\n\n\n \n\n\n\n Energies, 13(9). 2020.\n \n\n\n\n
\n\n\n\n \n \n \"PerformancePaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n  \n \n abstract \n \n\n \n  \n \n 9 downloads\n \n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@article{en13092409,\r\n  title = {Performance and Energy Trade-Offs for Parallel Applications on Heterogeneous Multi-Processing Systems},\r\n  author = {Coutinho Demetrios, A. M. and De Sensi, Daniele and Lorenzon, Arthur Francisco and Georgiou, Kyriakos and Nunez-Yanez, Jose and Eder, Kerstin and Xavier-de-Souza, Samuel},\r\n  year = 2020,\r\n  journal = {Energies},\r\n  volume = 13,\r\n  number = 9,\r\n  doi = {10.3390/en13092409},\r\n  issn = {1996-1073},\r\n  url = {https://www.mdpi.com/1996-1073/13/9/2409},\r\n  article-number = 2409,\r\n  abstract = {This work proposes a methodology to find performance and energy trade-offs for parallel applications running on Heterogeneous Multi-Processing systems with a single instruction-set architecture. These offer flexibility in the form of different core types and voltage and frequency pairings, defining a vast design space to explore. Therefore, for a given application, choosing a configuration that optimizes the performance and energy consumption is not straightforward. Our method proposes novel analytical models for performance and power consumption whose parameters can be fitted using only a few strategically sampled offline measurements. These models are then used to estimate an application&rsquo;s performance and energy consumption for the whole configuration space. In turn, these offline predictions define the choice of estimated Pareto-optimal configurations of the model, which are used to inform the selection of the configuration that the application should be executed on. The methodology was validated on an ODROID-XU3 board for eight programs from the PARSEC Benchmark, Phoronix Test Suite and Rodinia applications. The generated Pareto-optimal configuration space represented a 99% reduction of the universe of all available configurations. Energy savings of up to 59.77%, 61.38% and 17.7% were observed when compared to the performance, ondemand and powersave Linux governors, respectively, with higher or similar performance.}\r\n}\r\n\r\n
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\n This work proposes a methodology to find performance and energy trade-offs for parallel applications running on Heterogeneous Multi-Processing systems with a single instruction-set architecture. These offer flexibility in the form of different core types and voltage and frequency pairings, defining a vast design space to explore. Therefore, for a given application, choosing a configuration that optimizes the performance and energy consumption is not straightforward. Our method proposes novel analytical models for performance and power consumption whose parameters can be fitted using only a few strategically sampled offline measurements. These models are then used to estimate an application’s performance and energy consumption for the whole configuration space. In turn, these offline predictions define the choice of estimated Pareto-optimal configurations of the model, which are used to inform the selection of the configuration that the application should be executed on. The methodology was validated on an ODROID-XU3 board for eight programs from the PARSEC Benchmark, Phoronix Test Suite and Rodinia applications. The generated Pareto-optimal configuration space represented a 99% reduction of the universe of all available configurations. Energy savings of up to 59.77%, 61.38% and 17.7% were observed when compared to the performance, ondemand and powersave Linux governors, respectively, with higher or similar performance.\n
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\n \n\n \n \n \n \n \n \n PReGO: a generative methodology for satisfying real-time requirements on COTS-based systems: Definition and experience report.\n \n \n \n \n\n\n \n Rouxel, B.; Schultz, U. P.; Akesson, B.; Holst, J.; Jorgensen, O.; and Grelck, C.\n\n\n \n\n\n\n In 19th ACM SIGPLAN International Conference on Generative Programming: Concepts and Experiences (GPCE 2020), Chicago, USA, pages 70–83, 2020. ACM\n \n\n\n\n
\n\n\n\n \n \n \"PReGO:Paper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n  \n \n 1 download\n \n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{RouxPaghAkes+20,\r\n  title = {{PReGO}: a generative methodology for satisfying real-time requirements on COTS-based systems: Definition and experience report},\r\n  author = {Benjamin Rouxel and Ulrik Pagh Schultz and Benny Akesson and Jesper Holst and Ole Jorgensen and Clemens Grelck},\r\n  year = 2020,\r\n  booktitle = {19th ACM SIGPLAN International Conference on Generative Programming: Concepts and Experiences (GPCE 2020), Chicago, USA},\r\n  publisher = {ACM},\r\n  pages = {70--83},\r\n  doi = {10.1145/3425898.3426954},\r\n  url = {https://www.lexuor.net/publications/Drone_Use_Case_preprint.pdf}\r\n}\r\n\r\n
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\n \n\n \n \n \n \n \n \n Q-learning for Statically Scheduling DAGs.\n \n \n \n \n\n\n \n Roeder, J.; Rouxel, B.; and Grelck, C.\n\n\n \n\n\n\n In 8th IEEE International Conference on Big Data (BigData 2020), Atlanta, USA, 2020. IEEE\n \n\n\n\n
\n\n\n\n \n \n \"Q-learningPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n  \n \n 1 download\n \n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{RoedRouxGrel20,\r\n  title = {Q-learning for Statically Scheduling DAGs},\r\n  author = {Julius Roeder and Benjamin Rouxel and Clemens Grelck},\r\n  year = 2020,\r\n  booktitle = {8th IEEE International Conference on Big Data (BigData 2020), Atlanta, USA},\r\n  publisher = {IEEE},\r\n  doi = {10.1109/BigData50022.2020.9378062},\r\n  url = {https://staff.fnwi.uva.nl/c.u.grelck/publications/2020_BigData20_qlearning_for_dag_scheduling.pdf}\r\n}\r\n\r\n
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\n \n\n \n \n \n \n \n \n Run-Time Power Modelling in Embedded GPUs with Dynamic Voltage and Frequency Scaling.\n \n \n \n \n\n\n \n Nunez-Yanez, J.; Nikov, K.; Eder, K.; and Hosseinabady, M.\n\n\n \n\n\n\n In Proceedings of the 11th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures / 9th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms, New York, NY, USA, 2020. Association for Computing Machinery\n \n\n\n\n
\n\n\n\n \n \n \"Run-TimePaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n  \n \n abstract \n \n\n \n  \n \n 4 downloads\n \n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{nunezyanez2020runtime,\r\n  title = {Run-Time Power Modelling in Embedded GPUs with Dynamic Voltage and Frequency Scaling},\r\n  author = {Jose Nunez-Yanez and Kris Nikov and Kerstin Eder and Mohammad Hosseinabady},\r\n  year = 2020,\r\n  doi = {10.1145/3381427.3381429},\r\n  isbn = {9781450375450},\r\n  publisher = {Association for Computing Machinery},\r\n  address = {New York, NY, USA},\r\n  doi = {10.1145/3381427.3381429},\r\n  abstract = {This paper investigates the application of a robust CPU-based power modelling methodology that performs an automatic search of explanatory events derived from performance counters to embedded GPUs. A 64-bit Tegra TX1 SoC is configured with DVFS enabled and multiple CUDA benchmarks are used to train and test models optimized for each frequency and voltage point. These optimized models are then compared with a simpler unified model that uses a single set of model coefficients for all frequency and voltage points of interest. To obtain this unified model, a number of experiments are conducted to extract information on idle, clock and static power to derive power usage from a single reference equation. The results show that the unified model offers competitive accuracy with an average 5% error with four explanatory variables on the test data set and it is capable to correctly predict the impact of voltage, frequency and temperature on power consumption. This model could be used to replace direct power measurements when these are not available due to hardware limitations or worst-case analysis in emulation platforms.},\r\n  booktitle = {Proceedings of the 11th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures / 9th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms},\r\n  articleno = {2},\r\n  numpages = {6},\r\n  url = {https://arxiv.org/abs/2006.12176},\r\n  eprint = {2006.12176},\r\n  archiveprefix = {arXiv},\r\n  primaryclass = {cs.OH}\r\n}\r\n\r\n
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\n This paper investigates the application of a robust CPU-based power modelling methodology that performs an automatic search of explanatory events derived from performance counters to embedded GPUs. A 64-bit Tegra TX1 SoC is configured with DVFS enabled and multiple CUDA benchmarks are used to train and test models optimized for each frequency and voltage point. These optimized models are then compared with a simpler unified model that uses a single set of model coefficients for all frequency and voltage points of interest. To obtain this unified model, a number of experiments are conducted to extract information on idle, clock and static power to derive power usage from a single reference equation. The results show that the unified model offers competitive accuracy with an average 5% error with four explanatory variables on the test data set and it is capable to correctly predict the impact of voltage, frequency and temperature on power consumption. This model could be used to replace direct power measurements when these are not available due to hardware limitations or worst-case analysis in emulation platforms.\n
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\n \n\n \n \n \n \n \n \n Towards Energy-, Time- and Security-aware Multi-core Coordination.\n \n \n \n \n\n\n \n Roeder, J.; Rouxel, B.; Altmeyer, S.; and Grelck, C.\n\n\n \n\n\n\n In Bliudze, S.; and Bocchi, L., editor(s), 22nd International Conference on Coordination Models and Languages (COORDINATION 2020), Malta, volume 12134, of Lecture Notes in Computer Science, pages 57–74, 2020. Springer\n \n\n\n\n
\n\n\n\n \n \n \"TowardsPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n  \n \n 1 download\n \n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{RoedRouxAltm+20,\r\n  title = {Towards Energy-, Time- and Security-aware Multi-core Coordination},\r\n  author = {Julius Roeder and Benjamin Rouxel and Sebastian Altmeyer and Clemens Grelck},\r\n  year = 2020,\r\n  booktitle = {22nd International Conference on Coordination Models and Languages (COORDINATION 2020), Malta},\r\n  publisher = {Springer},\r\n  series = {Lecture Notes in Computer Science},\r\n  volume = 12134,\r\n  pages = {57--74},\r\n  doi = {10.1007/978-3-030-50029-0_4},\r\n  editor = {Bliudze, Simon and Bocchi, Laura},\r\n  url = {https://www.lexuor.net/publications/Coordination2020.pdf},\r\n}\r\n\r\n
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\n \n\n \n \n \n \n \n \n Energy-Optimal Configurations for Single-Node HPC Applications.\n \n \n \n \n\n\n \n Silva, V. R. G.; Furtunato, A. F. A.; Georgiou, K.; Sakuyama, C. A. V.; Eder, K.; and Xavier-de-Souza, S.\n\n\n \n\n\n\n In 2019 International Conference on High Performance Computing Simulation (HPCS), pages 448–454, 2019. \n \n\n\n\n
\n\n\n\n \n \n \"Energy-OptimalPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n  \n \n 1 download\n \n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{9188110,\r\n  title = {Energy-Optimal Configurations for Single-Node HPC Applications},\r\n  author = {Silva, Vitor R. G. and Furtunato, Alex F. A. and Georgiou, Kyriakos and Sakuyama, Carlos A. V. and Eder, Kerstin and Xavier-de-Souza, Samuel},\r\n  year = 2019,\r\n  booktitle = {2019 International Conference on High Performance Computing   Simulation (HPCS)},\r\n  pages = {448--454},\r\n  doi = {10.1109/HPCS48598.2019.9188110},\r\n  url = {http://arxiv.org/abs/1805.00998}\r\n}\r\n\r\n
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\n \n\n \n \n \n \n \n \n A Time-, Energy- and Security-aware Coordination Approach.\n \n \n \n \n\n\n \n Roeder, J.; Rouxel, B.; Altmeyer, S.; and Grelck, C.\n\n\n \n\n\n\n In 10th International Workshop on Analysis Tools and Methodologies for Embedded Real-Time Systems (WATERS 2019), 31st Euromicro Conference on Real-Time Systems (ECRTS 2019), 2019. Euromicro, ECRTS\n \n\n\n\n
\n\n\n\n \n \n \"APaper\n  \n \n\n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n  \n \n 1 download\n \n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{RoedRouxAltm+19b,\r\n  title = {A Time-, Energy- and Security-aware Coordination Approach},\r\n  author = {Julius Roeder and Benjamin Rouxel and Sebastian Altmeyer and Clemens Grelck},\r\n  year = 2019,\r\n  booktitle = {10th International Workshop on Analysis Tools and Methodologies for Embedded Real-Time Systems (WATERS 2019), 31st Euromicro Conference on Real-Time Systems (ECRTS 2019)},\r\n  publisher = {Euromicro, ECRTS},\r\n  url = {https://www.lexuor.net/publications/Rouxel_WATERS2019.pdf}\r\n}\r\n\r\n
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\n \n\n \n \n \n \n \n \n Favorable Adjustment of Periods for Reduced Hyperperiods in Real-Time Systems.\n \n \n \n \n\n\n \n Oehlert, D.; Luppold, A.; and Falk, H.\n\n\n \n\n\n\n In Proceedings of the 22nd International Workshop on Software and Compilers for Embedded Systems, of SCOPES '19, pages 82–85, New York, NY, USA, 2019. ACM\n \n\n\n\n
\n\n\n\n \n \n \"FavorablePaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n  \n \n 3 downloads\n \n \n\n \n \n \n \n \n \n \n\n  \n \n \n \n \n \n \n \n \n\n\n\n
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@inproceedings{Oehlert:2019:SCOPES,\r\n  title = {{Favorable Adjustment of Periods for Reduced Hyperperiods in Real-Time Systems}},\r\n  author = {Oehlert, Dominic and Luppold, Arno and Falk, Heiko},\r\n  year = 2019,\r\n  booktitle = {Proceedings of the 22nd International Workshop on Software and Compilers for Embedded Systems},\r\n  location = {Sankt Goar, Germany},\r\n  publisher = {ACM},\r\n  address = {New York, NY, USA},\r\n  series = {SCOPES '19},\r\n  pages = {82--85},\r\n  doi = {10.1145/3323439.3323975},\r\n  url = {https://tore.tuhh.de/bitstream/11420/2548/1/201905-scopes-oehlert.pdf},\r\n  numpages = 4,\r\n  keywords = {hyperperiod, real-time, integer linear programming}\r\n}\r\n\r\n
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\n \n\n \n \n \n \n \n \n Interdependent Multi-version Scheduling in Heterogeneous Energy-aware Embedded Systems.\n \n \n \n \n\n\n \n Roeder, J.; Rouxel, B.; Altmeyer, S.; and Grelck, C.\n\n\n \n\n\n\n In Rouxel, B.; and Paolillo, A., editor(s), 13th Junior Researcher Workshop on Real-Time Computing (JRWRTC 2019), part of the 27th International Conference on Real-Time Networks and Systems (RTNS 2019), Toulouse, France, pages 45–48, 2019. INP ENSEEIHT\n \n\n\n\n
\n\n\n\n \n \n \"InterdependentPaper\n  \n \n\n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
\n 
@inproceedings{RoedRouxAltm+19a,\r\n  title = {Interdependent Multi-version Scheduling in Heterogeneous Energy-aware Embedded Systems},\r\n  author = {Julius Roeder and Benjamin Rouxel and Sebastian Altmeyer and Clemens Grelck},\r\n  year = 2019,\r\n  booktitle = {13th Junior Researcher Workshop on Real-Time Computing (JRWRTC 2019), part of the 27th International Conference on Real-Time Networks and Systems (RTNS 2019), Toulouse, France},\r\n  publisher = {INP ENSEEIHT},\r\n  pages = {45--48},\r\n  editor = {B. Rouxel and A. Paolillo},\r\n  url = {https://hdl.handle.net/11245.1/fc811fd8-3eb7-4327-8ec0-370074b75b28}\r\n}\r\n\r\n
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\n \n\n \n \n \n \n \n \n Multi-Objective Optimization for the Compiler of Real-Time Systems based on Flower Pollination Algorithm.\n \n \n \n \n\n\n \n Jadhav, S.; and Falk, H.\n\n\n \n\n\n\n In Proceedings of the 22nd International Workshop on Software and Compilers for Embedded Systems, of SCOPES '19, pages 45–48, New York, NY, USA, 2019. ACM\n \n\n\n\n
\n\n\n\n \n \n \"Multi-ObjectivePaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n  \n \n 4 downloads\n \n \n\n \n \n \n \n \n \n \n\n  \n \n \n \n \n \n \n \n \n \n \n\n\n\n
\n 
@inproceedings{Jadhav:2019:SCOPES,\r\n  title = {{Multi-Objective Optimization for the Compiler of Real-Time Systems based on Flower Pollination Algorithm}},\r\n  author = {Jadhav, Shashank and Falk, Heiko},\r\n  year = 2019,\r\n  booktitle = {Proceedings of the 22nd International Workshop on Software and Compilers for Embedded Systems},\r\n  location = {Sankt Goar, Germany},\r\n  publisher = {ACM},\r\n  address = {New York, NY, USA},\r\n  series = {SCOPES '19},\r\n  pages = {45--48},\r\n  doi = {10.1145/3323439.3323977},\r\n  url = {https://tore.tuhh.de/bitstream/11420/2724/1/201905-scopes-jadhav.pdf},\r\n  numpages = 4,\r\n  keywords = {compiler, multi-objective, optimization, flower pollination algorithm}\r\n}\r\n\r\n
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\n \n\n \n \n \n \n \n \n Reasoning about non-functional properties using compiler intrinsic function annotations.\n \n \n \n \n\n\n \n Jadhav, S.; Roth, M.; Falk, H.; Brown, C.; and Barwell, A.\n\n\n \n\n\n\n In Proceedings of the 13th Junior Researcher Workshop on Real-Time Computing, of JRWRTC '19, pages 25–28, 2019. \n \n\n\n\n
\n\n\n\n \n \n \"ReasoningPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n  \n \n 1 download\n \n \n\n \n \n \n \n \n \n \n\n  \n \n \n \n \n \n \n \n \n \n \n\n\n\n
\n 
@inproceedings{Jadhav:2019:JRWRTC,\r\n  title = {{Reasoning about non-functional properties using compiler intrinsic function annotations}},\r\n  author = {Jadhav, Shashank and Roth, Mikko and Falk, Heiko and Brown, Christopher and Barwell, Adam},\r\n  year = 2019,\r\n  booktitle = {Proceedings of the 13th Junior Researcher Workshop on Real-Time Computing},\r\n  location = {Toulouse, France},\r\n  series = {JRWRTC '19},\r\n  pages = {25--28},\r\n  doi = {10.15480/882.2545},\r\n  url = {https://doi.org/10.15480/882.2545},\r\n  numpages = 4,\r\n  keywords = {Compilation, Annotations, Non-functional Properties, Function Inlining}\r\n}\r\n\r\n
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\n \n\n \n \n \n \n \n \n A Trustworthy Framework for Resource-Aware Embedded Programming.\n \n \n \n \n\n\n \n Barwell, A. D.; and Brown, C.\n\n\n \n\n\n\n In Proceedings of the 31st Symposium on Implementation and Application of Functional Languages, of IFL '19, New York, NY, USA, 2019. Association for Computing Machinery\n \n\n\n\n
\n\n\n\n \n \n \"APaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n  \n \n abstract \n \n\n \n  \n \n 2 downloads\n \n \n\n \n \n \n \n \n \n \n\n  \n \n \n \n \n \n \n \n \n \n \n \n \n\n\n\n
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@inproceedings{10.1145/3412932.3412944,\r\n  title = {A Trustworthy Framework for Resource-Aware Embedded Programming},\r\n  author = {Barwell, Adam D. and Brown, Christopher},\r\n  year = 2019,\r\n  booktitle = {Proceedings of the 31st Symposium on Implementation and Application of Functional Languages},\r\n  location = {Singapore, Singapore},\r\n  publisher = {Association for Computing Machinery},\r\n  address = {New York, NY, USA},\r\n  series = {IFL '19},\r\n  doi = {10.1145/3412932.3412944},\r\n  isbn = 9781450375627,\r\n  url = {https://www.researchgate.net/profile/Christopher-Brown-89/publication/343416568_A_Trustworthy_Framework_for_Resource-Aware_Embedded_Programming/links/5f291a34299bf134049edae9/A-Trustworthy-Framework-for-Resource-Aware-Embedded-Programming.pdf},\r\n  abstract = {Systems with non-functional requirements, such as Energy, Time and Security (ETS), are of increasing importance due to the proliferation of embedded devices with limited resources such as drones, wireless sensors, and tablet computers. Currently, however, there are little to no programmer supported methodologies or frameworks to allow them to reason about ETS properties in their source code. Drive is one such existing framework supporting the developer by lifting non-functional properties to the source-level through the Contract Specification Language (CSL), allowing non-functional properties to be first-class citizens, and supporting programmer-written code-level contracts to guarantee the non-functional specifications of the program are met. In this paper, we extend the Drive system by providing rigorous implementations of the underlying proof-engine, modeling the specification of the annotations and assertions from CSL for a representative subset of C, called Imp. We define both an improved abstract interpretation that automatically derives proofs of assertions, and define inference algorithms for the derivation of both abstract interpretations and the context over which the interpretation is indexed. We use the dependently-typed programming language, Idris, to give a formal definition, and implementation, of our abstract interpretation. Finally, we show our well-formed abstract interpretation over some representative exemplars demonstrating provable assertions of ETS.},\r\n  articleno = 12,\r\n  numpages = 12,\r\n  keywords = {lightweight verification, idris, non-functional properties, dependent types, embedded systems}\r\n}\r\n\r\n
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\n Systems with non-functional requirements, such as Energy, Time and Security (ETS), are of increasing importance due to the proliferation of embedded devices with limited resources such as drones, wireless sensors, and tablet computers. Currently, however, there are little to no programmer supported methodologies or frameworks to allow them to reason about ETS properties in their source code. Drive is one such existing framework supporting the developer by lifting non-functional properties to the source-level through the Contract Specification Language (CSL), allowing non-functional properties to be first-class citizens, and supporting programmer-written code-level contracts to guarantee the non-functional specifications of the program are met. In this paper, we extend the Drive system by providing rigorous implementations of the underlying proof-engine, modeling the specification of the annotations and assertions from CSL for a representative subset of C, called Imp. We define both an improved abstract interpretation that automatically derives proofs of assertions, and define inference algorithms for the derivation of both abstract interpretations and the context over which the interpretation is indexed. We use the dependently-typed programming language, Idris, to give a formal definition, and implementation, of our abstract interpretation. Finally, we show our well-formed abstract interpretation over some representative exemplars demonstrating provable assertions of ETS.\n
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\n \n\n \n \n \n \n \n \n Cache-Timing Attack Detection and Prevention.\n \n \n \n \n\n\n \n Carré, S.; Facon, A.; Guilley, S.; Takarabt, S.; Schaub, A.; and Souissi, Y.\n\n\n \n\n\n\n In Polian, I.; and Stöttinger, M., editor(s), Constructive Side-Channel Analysis and Secure Design, pages 13–21, Cham, 2019. Springer International Publishing\n \n\n\n\n
\n\n\n\n \n \n \"Cache-TimingPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n  \n \n abstract \n \n\n \n  \n \n 3 downloads\n \n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{10.1007/978-3-030-16350-1_2,\r\n  title = {Cache-Timing Attack Detection and Prevention},\r\n  author = {Carr{\\'e}, S{\\'e}bastien and Facon, Adrien and Guilley, Sylvain and Takarabt, Sofiane and Schaub, Alexander and Souissi, Youssef},\r\n  year = 2019,\r\n  booktitle = {Constructive Side-Channel Analysis and Secure Design},\r\n  publisher = {Springer International Publishing},\r\n  address = {Cham},\r\n  pages = {13--21},\r\n  doi = {10.1007/978-3-030-16350-1_2},\r\n  isbn = {978-3-030-16350-1},\r\n  url = {https://hal-cnrs.archives-ouvertes.fr/hal-02915644},\r\n  editor = {Polian, Ilia and St{\\"o}ttinger, Marc},\r\n  abstract = {With the publication of Spectre {\\&} Meltdown attacks, cache-timing exploitation techniques have received a wealth of attention recently. On the one hand, it is now well understood which patterns in the source code create observable unbalances in terms of timing. On the other hand, some practical attacks have also been reported. But the exact relation between vulnerabilities and exploitations is not enough studied as of today. In this article, we put forward a methodology to characterize the leakage induced by a ``non-constant-time'' construct in the source code. This methodology allows us to recover known attacks and to warn about possible new ones, possibly devastating.}\r\n}\r\n\r\n
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\n With the publication of Spectre & Meltdown attacks, cache-timing exploitation techniques have received a wealth of attention recently. On the one hand, it is now well understood which patterns in the source code create observable unbalances in terms of timing. On the other hand, some practical attacks have also been reported. But the exact relation between vulnerabilities and exploitations is not enough studied as of today. In this article, we put forward a methodology to characterize the leakage induced by a ``non-constant-time'' construct in the source code. This methodology allows us to recover known attacks and to warn about possible new ones, possibly devastating.\n
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\n \n\n \n \n \n \n \n \n Cache-Timing Attacks Still Threaten IoT Devices.\n \n \n \n \n\n\n \n Takarabt, S.; Schaub, A.; Facon, A.; Guilley, S.; Sauvage, L.; Souissi, Y.; and Mathieu, Y.\n\n\n \n\n\n\n In Carlet, C.; Guilley, S.; Nitaj, A.; and Souidi, E. M., editor(s), Codes, Cryptology and Information Security, pages 13–30, Cham, 2019. Springer International Publishing\n \n\n\n\n
\n\n\n\n \n \n \"Cache-TimingPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n  \n \n abstract \n \n\n \n  \n \n 2 downloads\n \n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{10.1007/978-3-030-16458-4_2,\r\n  title = {Cache-Timing Attacks Still Threaten IoT Devices},\r\n  author = {Takarabt, Sofiane and Schaub, Alexander and Facon, Adrien and Guilley, Sylvain and Sauvage, Laurent and Souissi, Youssef and Mathieu, Yves},\r\n  year = 2019,\r\n  booktitle = {Codes, Cryptology and Information Security},\r\n  publisher = {Springer International Publishing},\r\n  address = {Cham},\r\n  pages = {13--30},\r\n  doi = {10.1007/978-3-030-16458-4_2},\r\n  isbn = {978-3-030-16458-4},\r\n  url = {https://hal-cnrs.archives-ouvertes.fr/hal-02319488},\r\n  editor = {Carlet, Claude and Guilley, Sylvain and Nitaj, Abderrahmane and Souidi, El Mamoun},\r\n  abstract = {Deployed widely and embedding sensitive data, The security of IoT devices depend on the reliability of cryptographic libraries to protect user information. However when implemented on real systems, cryptographic algorithms are vulnerable to side-channel attacks based on their execution behavior, which can be revealed by measurements of physical quantities such as timing or power consumption. Some countermeasures can be implemented in order to prevent those attacks. However those countermeasures are generally designed at high level description, and when implemented, some residual leakage may persist. In this article we propose a methodology to assess the robustness of the MbedTLS library against timing and cache-timing attacks. This comprehensive study of side-channel security allows us to identify the most frequent weaknesses in software cryptographic code and how those might be fixed. This methodology checks the whole source code, from the top level routines to low level primitives, that are used for the final application. We retrieve hundreds of lines of code that leak sensitive information.}\r\n}\r\n\r\n
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\n Deployed widely and embedding sensitive data, The security of IoT devices depend on the reliability of cryptographic libraries to protect user information. However when implemented on real systems, cryptographic algorithms are vulnerable to side-channel attacks based on their execution behavior, which can be revealed by measurements of physical quantities such as timing or power consumption. Some countermeasures can be implemented in order to prevent those attacks. However those countermeasures are generally designed at high level description, and when implemented, some residual leakage may persist. In this article we propose a methodology to assess the robustness of the MbedTLS library against timing and cache-timing attacks. This comprehensive study of side-channel security allows us to identify the most frequent weaknesses in software cryptographic code and how those might be fixed. This methodology checks the whole source code, from the top level routines to low level primitives, that are used for the final application. We retrieve hundreds of lines of code that leak sensitive information.\n
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\n \n\n \n \n \n \n \n \n Coarse-Grained Computation-Oriented Energy Modeling for Heterogeneous Parallel Embedded Systems.\n \n \n \n \n\n\n \n Seewald, A.; Schultz, U. P.; Ebeid, E.; and Midtiby, H. S.\n\n\n \n\n\n\n International Journal of Parallel Programming, 49(2): 136–157. 2019.\n \n\n\n\n
\n\n\n\n \n \n \"Coarse-GrainedPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n  \n \n 4 downloads\n \n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
\n 
@article{seewald2019coarse,\r\n  title = {Coarse-Grained Computation-Oriented Energy Modeling for Heterogeneous Parallel Embedded Systems},\r\n  author = {Seewald, Adam and Schultz, Ulrik Pagh and Ebeid, Emad and Midtiby, Henrik Skov},\r\n  year = 2019,\r\n  journal = {International Journal of Parallel Programming},\r\n  publisher = {Springer},\r\n  volume = 49,\r\n  number = 2,\r\n  pages = {136--157},\r\n  doi = {10.1007/s10766-019-00645-y},\r\n  issn = {0885-7458},\r\n  url = {https://adamseewald.cc/short/coarse2019}\r\n}\r\n\r\n
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\n \n\n \n \n \n \n \n \n Code-Inherent Traffic Shaping for Hard Real-Time Systems.\n \n \n \n \n\n\n \n Oehlert, D.; Saidi, S.; and Falk, H.\n\n\n \n\n\n\n ACM Trans. Embed. Comput. Syst., 18(5s). October 2019.\n \n\n\n\n
\n\n\n\n \n \n \"Code-InherentPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n  \n \n abstract \n \n\n \n  \n \n 2 downloads\n \n \n\n \n \n \n \n \n \n \n\n  \n \n \n \n \n \n \n \n \n \n \n\n\n\n
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@article{10.1145/3358215,\r\n  title = {Code-Inherent Traffic Shaping for Hard Real-Time Systems},\r\n  author = {Oehlert, Dominic and Saidi, Selma and Falk, Heiko},\r\n  year = 2019,\r\n  month = oct,\r\n  journal = {ACM Trans. Embed. Comput. Syst.},\r\n  publisher = {Association for Computing Machinery},\r\n  address = {New York, NY, USA},\r\n  volume = 18,\r\n  number = {5s},\r\n  doi = {10.1145/3358215},\r\n  issn = {1539-9087},\r\n  url = {https://tore.tuhh.de/handle/11420/4381},\r\n  issue_date = {October 2019},\r\n  abstract = {Modern hard real-time systems evolved from isolated single-core architectures to complex multi-core architectures which are often connected in a distributed manner. With the increasing influence of interconnections in hard real-time systems, the access behavior to shared resources of single tasks or cores becomes a crucial factor for the system’s overall worst-case timing properties. Traffic shaping is a powerful technique to decrease contention in a network and deliver guarantees on network streams. In this paper we present a novel approach to automatically integrate a traffic shaping behavior into the code of a program for different traffic shaping profiles while being as least invasive as possible. As this approach is solely depending on modifying programs on a code-level, it does not rely on any additional hardware or operating system-based functions.We show how different traffic shaping profiles can be implemented into programs using a greedy heuristic and an evolutionary algorithm, as well as their influences on the modified programs. It is demonstrated that the presented approaches can be used to decrease worst-case execution times in multi-core systems and lower buffer requirements in distributed systems.},\r\n  articleno = 108,\r\n  numpages = 21,\r\n  keywords = {traffic shaping, multi-core, Real-time, event arrival functions}\r\n}\r\n\r\n
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\n Modern hard real-time systems evolved from isolated single-core architectures to complex multi-core architectures which are often connected in a distributed manner. With the increasing influence of interconnections in hard real-time systems, the access behavior to shared resources of single tasks or cores becomes a crucial factor for the system’s overall worst-case timing properties. Traffic shaping is a powerful technique to decrease contention in a network and deliver guarantees on network streams. In this paper we present a novel approach to automatically integrate a traffic shaping behavior into the code of a program for different traffic shaping profiles while being as least invasive as possible. As this approach is solely depending on modifying programs on a code-level, it does not rely on any additional hardware or operating system-based functions.We show how different traffic shaping profiles can be implemented into programs using a greedy heuristic and an evolutionary algorithm, as well as their influences on the modified programs. It is demonstrated that the presented approaches can be used to decrease worst-case execution times in multi-core systems and lower buffer requirements in distributed systems.\n
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\n \n\n \n \n \n \n \n \n Component-based computation-energy modeling for embedded systems.\n \n \n \n \n\n\n \n Seewald, A.; Schultz, U. P.; Roeder, J.; Rouxel, B.; and Grelck, C.\n\n\n \n\n\n\n In Proceedings Companion of the 2019 ACM SIGPLAN International Conference on Systems, Programming, Languages, and Applications: Software for Humanity, pages 5–6, 2019. ACM\n \n\n\n\n
\n\n\n\n \n \n \"Component-basedPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n  \n \n 4 downloads\n \n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{seewald2019component,\r\n  title = {Component-based computation-energy modeling for embedded systems},\r\n  author = {Seewald, Adam and Schultz, Ulrik Pagh and Roeder, Julius and Rouxel, Benjamin and Grelck, Clemens},\r\n  year = 2019,\r\n  booktitle = {Proceedings Companion of the 2019 ACM SIGPLAN International Conference on Systems, Programming, Languages, and Applications: Software for Humanity},\r\n  pages = {5--6},\r\n  doi = {10.1145/3359061.3362775},\r\n  url = {https://adamseewald.cc/short/component2019},\r\n  organization = {ACM}\r\n}\r\n\r\n
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\n \n\n \n \n \n \n \n \n Fault Analysis Assisted by Simulation.\n \n \n \n \n\n\n \n Chibani, K.; Facon, A.; Guilley, S.; Marion, D.; Mathieu, Y.; Sauvage, L.; Souissi, Y.; and Takarabt, S.\n\n\n \n\n\n\n ,263–277. 2019.\n \n\n\n\n
\n\n\n\n \n \n \"FaultPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n  \n \n 19 downloads\n \n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@article{Chibani2019,\r\n  title = {Fault Analysis Assisted by Simulation},\r\n  author = {Chibani, Kais and Facon, Adrien and Guilley, Sylvain and Marion, Damien and Mathieu, Yves and Sauvage, Laurent and Souissi, Youssef and Takarabt, Sofiane},\r\n  year = 2019,\r\n  booktitle = {Automated Methods in Cryptographic Fault Analysis},\r\n  publisher = {Springer International Publishing},\r\n  address = {Cham},\r\n  pages = {263--277},\r\n  doi = {10.1007/978-3-030-11333-9_12},\r\n  isbn = {978-3-030-11333-9},\r\n  url = {https://hal-cnrs.archives-ouvertes.fr/hal-02915671},\r\n  editor = {Breier, Jakub and Hou, Xiaolu and Bhasin, Shivam}\r\n}\r\n\r\n
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\n \n\n \n \n \n \n \n \n Programming Heterogeneous Parallel machines using Refactoring and Monte-Carlo Tree Search.\n \n \n \n \n\n\n \n Brown, C.; Janjic, V.; and McCall, J.\n\n\n \n\n\n\n In 12th International Symposium on High-Level Parallel Programming and Applications (HLPP), 2019. \n \n\n\n\n
\n\n\n\n \n \n \"ProgrammingPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n  \n \n 2 downloads\n \n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{brownhlpp2019,\r\n  title = {Programming Heterogeneous Parallel machines using Refactoring and Monte-Carlo Tree Search},\r\n  author = {Christopher Brown and Vladimir Janjic and John McCall},\r\n  year = 2019,\r\n  booktitle = {12th International Symposium on High-Level Parallel Programming and Applications (HLPP)},\r\n  doi = {10.1007/s10766-020-00665-z},\r\n  url = {https://doi.org/10.1007/s10766-020-00665-z}\r\n}\r\n\r\n
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\n \n\n \n \n \n \n \n \n Proof-Carrying Plans.\n \n \n \n \n\n\n \n Schwaab, C.; Komendantskaya, E.; Hill, A.; Farka, F.; Petrick, R. P. A.; Wells, J.; and Hammond, K.\n\n\n \n\n\n\n In Alferes, J. J.; and Johansson, M., editor(s), Practical Aspects of Declarative Languages, pages 204–220, Cham, 2019. Springer International Publishing\n \n\n\n\n
\n\n\n\n \n \n \"Proof-CarryingPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n  \n \n abstract \n \n\n \n  \n \n 1 download\n \n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{10.1007/978-3-030-05998-9_13,\r\n  title = {Proof-Carrying Plans},\r\n  author = {Schwaab, Christopher and Komendantskaya, Ekaterina and Hill, Alasdair and Farka, Franti{\\v{s}}ek and Petrick, Ronald P. A. and Wells, Joe and Hammond, Kevin},\r\n  year = 2019,\r\n  booktitle = {Practical Aspects of Declarative Languages},\r\n  publisher = {Springer International Publishing},\r\n  address = {Cham},\r\n  pages = {204--220},\r\n  doi = {10.1007/978-3-030-05998-9_13},\r\n  isbn = {978-3-030-05998-9},\r\n  url = {https://research-repository.st-andrews.ac.uk/handle/10023/16855},\r\n  editor = {Alferes, Jos{\\'e} J{\\'u}lio and Johansson, Moa},\r\n  abstract = {It is becoming increasingly important to verify safety and security of AI applications. While declarative languages (of the kind found in automated planners and model checkers) are traditionally used for verifying AI systems, a big challenge is to design methods that generate verified executable programs. A good example of such a ``verification to implementation'' cycle is given by automated planning languages like PDDL, where plans are found via a model search in a declarative language, but then interpreted or compiled into executable code in an imperative language. In this paper, we show that this method can itself be verified. We present a formal framework and a prototype Agda implementation that represent PDDL plans as executable functions that inhabit types that are given by formulae describing planning problems. By exploiting the well-known Curry-Howard correspondence, type-checking then automatically ensures that the generated program corresponds precisely to the specification of the planning problem.}\r\n}\r\n\r\n
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\n It is becoming increasingly important to verify safety and security of AI applications. While declarative languages (of the kind found in automated planners and model checkers) are traditionally used for verifying AI systems, a big challenge is to design methods that generate verified executable programs. A good example of such a ``verification to implementation'' cycle is given by automated planning languages like PDDL, where plans are found via a model search in a declarative language, but then interpreted or compiled into executable code in an imperative language. In this paper, we show that this method can itself be verified. We present a formal framework and a prototype Agda implementation that represent PDDL plans as executable functions that inhabit types that are given by formulae describing planning problems. By exploiting the well-known Curry-Howard correspondence, type-checking then automatically ensures that the generated program corresponds precisely to the specification of the planning problem.\n
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\n \n\n \n \n \n \n \n \n Refactoring for Introducing and Tuning Parallelism for Heterogeneous Multicore Machiens in Erlang.\n \n \n \n \n\n\n \n Brown, C.; Janjic, V.; Barwell, A.; and Hammond, K.\n\n\n \n\n\n\n In Journal of Concurrency and Computation: Practice and Experience CCPE, 2019. \n \n\n\n\n
\n\n\n\n \n \n \"RefactoringPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n  \n \n 2 downloads\n \n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
\n 
@inproceedings{DBLP:conf/padl/SchwaabKHFPWH19-refactoring,\r\n  title = {Refactoring for Introducing and Tuning Parallelism for Heterogeneous Multicore Machiens in Erlang},\r\n  author = {Christopher Brown and Vladimir Janjic and Adam Barwell and Kevin Hammond},\r\n  year = 2019,\r\n  booktitle = {Journal of Concurrency and Computation: Practice and Experience CCPE},\r\n  doi = {10.1002/cpe.5420},\r\n  url = {https://risweb.st-andrews.ac.uk/portal/en/researchoutput/refactoring-for-introducing-and-tuning-parallelism-for-heterogeneous-multicore-machines-in-erlang(f31ae458-56ad-48b8-9df9-132877165e0f).html}\r\n}\r\n\r\n
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\n \n\n \n \n \n \n \n \n Refactoring GrPPI: Generic Refactoring for Generic Parallelism in C++.\n \n \n \n \n\n\n \n Brown, C.; Janjic, V.; Barwell, A.; and Garcia, J. D.\n\n\n \n\n\n\n In 12th International Symposium on High-Level Parallel Programming and Applications, 2019. \n \n\n\n\n
\n\n\n\n \n \n \"RefactoringPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n  \n \n 4 downloads\n \n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{brownhlpp2019-2,\r\n  title = {Refactoring GrPPI: Generic Refactoring for Generic Parallelism in C++},\r\n  author = {Christopher Brown and Vladimir Janjic and Adam Barwell and Jose Daniel Garcia},\r\n  year = 2019,\r\n  booktitle = {12th International Symposium on High-Level Parallel Programming and Applications},\r\n  doi = {10.1007/s10766-020-00667-x},\r\n  url = {https://risweb.st-andrews.ac.uk/portal/en/researchoutput/refactoring-grppi(84dd2979-e2bf-456c-9991-73e3cd996a17).html}\r\n}\r\n\r\n
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\n \n\n \n \n \n \n \n \n Security Evaluation Against Side-Channel Analysis at Compilation Time.\n \n \n \n \n\n\n \n Bruneau, N.; Christen, C.; Danger, J.; Facon, A.; and Guilley, S.\n\n\n \n\n\n\n In Gueye, C. T.; Persichetti, E.; Cayrel, P.; and Buchmann, J., editor(s), Algebra, Codes and Cryptology, pages 129–148, Cham, 2019. Springer International Publishing\n \n\n\n\n
\n\n\n\n \n \n \"SecurityPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n  \n \n abstract \n \n\n \n  \n \n 2 downloads\n \n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
\n 
@inproceedings{10.1007/978-3-030-36237-9_8,\r\n  title = {Security Evaluation Against Side-Channel Analysis at Compilation Time},\r\n  author = {Bruneau, Nicolas and Christen, Charles and Danger, Jean-Luc and Facon, Adrien and Guilley, Sylvain},\r\n  year = 2019,\r\n  booktitle = {Algebra, Codes and Cryptology},\r\n  publisher = {Springer International Publishing},\r\n  address = {Cham},\r\n  pages = {129--148},\r\n  doi = {10.1007/978-3-030-36237-9_8},\r\n  isbn = {978-3-030-36237-9},\r\n  url = {https://hal-cnrs.archives-ouvertes.fr/hal-02915643},\r\n  editor = {Gueye, Cheikh Thiecoumba and Persichetti, Edoardo and Cayrel, Pierre-Louis and Buchmann, Johannes},\r\n  abstract = {Masking countermeasure is implemented to thwart side-channel attacks. The maturity of high-order masking schemes has reached the level where the concepts are sound and proven. For instance, Rivain and Prouff proposed a full-fledged AES at CHES 2010. Some non-trivial fixes regarding refresh functions were needed though. Now, industry is adopting such solutions, and for the sake of both quality and certification requirements, masked cryptographic code shall be checked for correctness using the same model as that of the theoretical protection rationale (for instance the probing leakage model).}\r\n}\r\n\r\n
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\n Masking countermeasure is implemented to thwart side-channel attacks. The maturity of high-order masking schemes has reached the level where the concepts are sound and proven. For instance, Rivain and Prouff proposed a full-fledged AES at CHES 2010. Some non-trivial fixes regarding refresh functions were needed though. Now, industry is adopting such solutions, and for the sake of both quality and certification requirements, masked cryptographic code shall be checked for correctness using the same model as that of the theoretical protection rationale (for instance the probing leakage model).\n
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\n \n\n \n \n \n \n \n \n Type-Driven Verification of Non-Functional Properties.\n \n \n \n \n\n\n \n Brown, C.; Barwell, A. D.; Marquer, Y.; Minh, C.; and Zendra, O.\n\n\n \n\n\n\n In Proceedings of the 21st International Symposium on Principles and Practice of Declarative Programming, of PPDP '19, New York, NY, USA, 2019. Association for Computing Machinery\n \n\n\n\n
\n\n\n\n \n \n \"Type-DrivenPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n  \n \n abstract \n \n\n \n  \n \n 9 downloads\n \n \n\n \n \n \n \n \n \n \n\n  \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n\n\n
\n 
@inproceedings{10.1145/3354166.3354171,\r\n  title = {Type-Driven Verification of Non-Functional Properties},\r\n  author = {Brown, Christopher and Barwell, Adam D. and Marquer, Yoann and Minh, C\\'{e}line and Zendra, Olivier},\r\n  year = 2019,\r\n  booktitle = {Proceedings of the 21st International Symposium on Principles and Practice of Declarative Programming},\r\n  location = {Porto, Portugal},\r\n  publisher = {Association for Computing Machinery},\r\n  address = {New York, NY, USA},\r\n  series = {PPDP '19},\r\n  doi = {10.1145/3354166.3354171},\r\n  isbn = 9781450372497,\r\n  url = {https://hal.inria.fr/hal-02314723/document},\r\n  abstract = {Energy, Time and Security (ETS) properties of programs are becoming increasingly prioritised by developers, especially where applications are running on ETS sensitive systems, such as embedded devices or the Internet of Things. Moreover, developers currently lack tools and language properties to allow them to reason about ETS. In this paper, we introduce a new contract specification framework, called Drive, which allows a developer to reason about ETS or other non-functional properties of their programs as first-class properties of the language. Furthermore, we introduce a contract specification language, allowing developers to reason about these first-class ETS properties by expressing contracts that are proved correct by an underlying formal type system. Finally, we show our contract framework over a number of representable examples, demonstrating provable worst-case ETS properties.},\r\n  articleno = 6,\r\n  numpages = 15,\r\n  keywords = {contracts, energy, verification, non-functional properties, proofs, security, time, C, IDRIS}\r\n}\r\n\r\n
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\n Energy, Time and Security (ETS) properties of programs are becoming increasingly prioritised by developers, especially where applications are running on ETS sensitive systems, such as embedded devices or the Internet of Things. Moreover, developers currently lack tools and language properties to allow them to reason about ETS. In this paper, we introduce a new contract specification framework, called Drive, which allows a developer to reason about ETS or other non-functional properties of their programs as first-class properties of the language. Furthermore, we introduce a contract specification language, allowing developers to reason about these first-class ETS properties by expressing contracts that are proved correct by an underlying formal type system. Finally, we show our contract framework over a number of representable examples, demonstrating provable worst-case ETS properties.\n
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\n  \n 2018\n \n \n (5)\n \n \n
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\n \n\n \n \n \n \n \n \n Technology-agnostic power optimization for AES block cipher.\n \n \n \n \n\n\n \n Chibani, K.; Facon, A.; Guilley, S.; and Souissi, Y.\n\n\n \n\n\n\n In 2018 25th IEEE International Conference on Electronics, Circuits and Systems (ICECS), pages 397–400, 2018. \n \n\n\n\n
\n\n\n\n \n \n \"Technology-agnosticPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n  \n \n 2 downloads\n \n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{8617921,\r\n  title = {Technology-agnostic power optimization for AES block cipher},\r\n  author = {K. {Chibani} and A. {Facon} and S. {Guilley} and Y. {Souissi}},\r\n  year = 2018,\r\n  booktitle = {2018 25th IEEE International Conference on Electronics, Circuits and Systems (ICECS)},\r\n  pages = {397--400},\r\n  doi = 10.1109/ICECS.2018.8617921,\r\n  url = {https://hal-cnrs.archives-ouvertes.fr/hal-02915635}\r\n}\r\n\r\n
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\n \n\n \n \n \n \n \n \n Measuring and Modeling Energy Consumption of Embedded Systems for Optimizing Compilers.\n \n \n \n \n\n\n \n Roth, M.; Luppold, A.; and Falk, H.\n\n\n \n\n\n\n In Proceedings of the 21st International Workshop on Software and Compilers for Embedded Systems, of SCOPES '18, pages 86–89, New York, NY, USA, 2018. ACM\n \n\n\n\n
\n\n\n\n \n \n \"MeasuringPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n  \n \n 5 downloads\n \n \n\n \n \n \n \n \n \n \n\n  \n \n \n \n \n \n \n \n \n \n \n\n\n\n
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@inproceedings{Roth:2018:SCOPES:3207719.3207729,\r\n  title = {{Measuring and Modeling Energy Consumption of Embedded Systems for Optimizing Compilers}},\r\n  author = {Roth, Mikko and Luppold, Arno and Falk, Heiko},\r\n  year = 2018,\r\n  booktitle = {Proceedings of the 21st International Workshop on Software and Compilers for Embedded Systems},\r\n  location = {Sankt Goar, Germany},\r\n  publisher = {ACM},\r\n  address = {New York, NY, USA},\r\n  series = {SCOPES '18},\r\n  pages = {86--89},\r\n  doi = {10.1145/3207719.3207729},\r\n  isbn = {978-1-4503-5780-7},\r\n  url = {https://tore.tuhh.de/bitstream/11420/1754/1/20180529-scopes-roth.pdf},\r\n  numpages = 4,\r\n  keywords = {compiler, energy, analysis, measuring}\r\n}\r\n\r\n
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\n \n\n \n \n \n \n \n \n A survey of Open-Source UAV flight controllers and flight simulators.\n \n \n \n \n\n\n \n Ebeid, E.; Skriver, M.; Terkildsen, K. H.; Jensen, K.; and Schultz, U. P.\n\n\n \n\n\n\n Microprocessors and Microsystems, 61: 11–20. 2018.\n \n\n\n\n
\n\n\n\n \n \n \"APaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n  \n \n 1 download\n \n \n\n \n \n \n \n \n \n \n\n  \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n\n\n
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@article{EBEID201811,\r\n  title = {A survey of Open-Source UAV flight controllers and flight simulators},\r\n  author = {Emad Ebeid and Martin Skriver and Kristian Husum Terkildsen and Kjeld Jensen and Ulrik Pagh Schultz},\r\n  year = 2018,\r\n  journal = {Microprocessors and Microsystems},\r\n  volume = 61,\r\n  pages = {11--20},\r\n  doi = {10.1016/j.micpro.2018.05.002},\r\n  issn = {0141-9331},\r\n  url = {https://www.researchgate.net/publication/325134452_A_Survey_of_Open-Source_UAV_Flight_Controllers_and_Flight_Simulators},\r\n  keywords = {Unmanned Aerial Vehicle (UAV), Drones, Flight controllers, Drone simulators, Open platforms, Survey}\r\n}\r\n\r\n
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\n \n\n \n \n \n \n \n \n Evaluating the Performance of Solvers for Integer-Linear Programming.\n \n \n \n \n\n\n \n Luppold, A.; Oehlert, D.; and Falk, H.\n\n\n \n\n\n\n Technical Report Hamburg University of Technology, Hamburg, Germany, 2018.\n \n\n\n\n
\n\n\n\n \n \n \"EvaluatingPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
\n 
@techreport{LOF18,\r\n  title = {Evaluating the Performance of Solvers for Integer-Linear Programming},\r\n  author = {Luppold, Arno and Oehlert, Dominic and Falk, Heiko},\r\n  year = 2018,\r\n  address = {Hamburg, Germany},\r\n  doi = {10.15480/882.1839},\r\n  url = {https://doi.org/10.15480/882.1839},\r\n  institution = {Hamburg University of Technology}\r\n}\r\n\r\n
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\n \n\n \n \n \n \n \n \n Less is More: Exploiting the Standard Compiler Optimization Levels for Better Performance and Energy Consumption.\n \n \n \n \n\n\n \n Georgiou, K.; Blackmore, C.; Xavier-de-Souza, S.; and Eder, K.\n\n\n \n\n\n\n In Proceedings of the 21st International Workshop on Software and Compilers for Embedded Systems, of SCOPES '18, pages 35–42, New York, NY, USA, 2018. ACM\n \n\n\n\n
\n\n\n\n \n \n \"LessPaper\n  \n \n \n \"Less data\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n  \n \n 5 downloads\n \n \n\n \n \n \n \n \n \n \n\n  \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n\n\n\n
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@inproceedings{Georgiou:2018:LME:3207719.3207727,\r\n  title = {Less is More: Exploiting the Standard Compiler Optimization Levels for Better Performance and Energy Consumption},\r\n  author = {Georgiou, Kyriakos and Blackmore, Craig and Xavier-de-Souza, Samuel and Eder, Kerstin},\r\n  year = 2018,\r\n  booktitle = {Proceedings of the 21st International Workshop on Software and Compilers for Embedded Systems},\r\n  location = {Sankt Goar, Germany},\r\n  publisher = {ACM},\r\n  address = {New York, NY, USA},\r\n  series = {SCOPES '18},\r\n  pages = {35--42},\r\n  doi = {10.1145/3207719.3207727},\r\n  isbn = {978-1-4503-5780-7},\r\n  url = {https://arxiv.org/abs/1802.09845},\r\n  numpages = 8,\r\n  acmid = 3207727,\r\n  keywords = {autotuning, compiler optimizations, embedded systems, energy consumption, execution time, phase-ordering},\r\n  url_data = {https://doi.org/10.5281/zenodo.1451736}\r\n}\r\n\r\n
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