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\n  \n 2023\n \n \n (12)\n \n \n
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\n \n\n \n \n \n \n \n \n A Comprehensive Framework for Systemic Security Management in NoC-Based Many-Cores.\n \n \n \n \n\n\n \n Faccenda, R. F.; Comarú, G.; Caimi, L. L.; and Moraes, F. G.\n\n\n \n\n\n\n IEEE Access, 11: 131836–131847. 2023.\n \n\n\n\n
\n\n\n\n \n \n \"APaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@article{DBLP:journals/access/FaccendaCCM23,\n  author       = {Rafael Follmann Faccenda and\n                  Gustavo Comar{\\'{u}} and\n                  Luciano Lores Caimi and\n                  Fernando Gehm Moraes},\n  title        = {A Comprehensive Framework for Systemic Security Management in NoC-Based\n                  Many-Cores},\n  journal      = {{IEEE} Access},\n  volume       = {11},\n  pages        = {131836--131847},\n  year         = {2023},\n  url          = {https://doi.org/10.1109/ACCESS.2023.3336565},\n  doi          = {10.1109/ACCESS.2023.3336565},\n  timestamp    = {Sun, 10 Dec 2023 00:00:00 +0100},\n  biburl       = {https://dblp.org/rec/journals/access/FaccendaCCM23.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n SeMAP - A Method to Secure the Communication in NoC-Based Many-Cores.\n \n \n \n \n\n\n \n Faccenda, R. F.; Comarú, G.; Caimi, L. L.; and Moraes, F. G.\n\n\n \n\n\n\n IEEE Des. Test, 40(5): 42–51. 2023.\n \n\n\n\n
\n\n\n\n \n \n \"SeMAPPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@article{DBLP:journals/dt/FaccendaCCM23,\n  author       = {Rafael Follmann Faccenda and\n                  Gustavo Comar{\\'{u}} and\n                  Luciano Lores Caimi and\n                  Fernando Gehm Moraes},\n  title        = {SeMAP - {A} Method to Secure the Communication in NoC-Based Many-Cores},\n  journal      = {{IEEE} Des. Test},\n  volume       = {40},\n  number       = {5},\n  pages        = {42--51},\n  year         = {2023},\n  url          = {https://doi.org/10.1109/MDAT.2023.3277813},\n  doi          = {10.1109/MDAT.2023.3277813},\n  timestamp    = {Sun, 17 Dec 2023 00:00:00 +0100},\n  biburl       = {https://dblp.org/rec/journals/dt/FaccendaCCM23.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n From CNN to DNN Hardware Accelerators: A Survey on Design, Exploration, Simulation, and Frameworks.\n \n \n \n \n\n\n \n Juracy, L. R.; Garibotti, R.; and Moraes, F. G.\n\n\n \n\n\n\n Found. Trends Electron. Des. Autom., 13(4): 270–344. 2023.\n \n\n\n\n
\n\n\n\n \n \n \"FromPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@article{DBLP:journals/fteda/JuracyGM23,\n  author       = {Leonardo Rezende Juracy and\n                  Rafael Garibotti and\n                  Fernando Gehm Moraes},\n  title        = {From {CNN} to {DNN} Hardware Accelerators: {A} Survey on Design, Exploration,\n                  Simulation, and Frameworks},\n  journal      = {Found. Trends Electron. Des. Autom.},\n  volume       = {13},\n  number       = {4},\n  pages        = {270--344},\n  year         = {2023},\n  url          = {https://doi.org/10.1561/1000000060},\n  doi          = {10.1561/1000000060},\n  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},\n  biburl       = {https://dblp.org/rec/journals/fteda/JuracyGM23.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n A Comprehensive Evaluation of Convolutional Hardware Accelerators.\n \n \n \n \n\n\n \n Juracy, L. R.; Amory, A. M.; and Moraes, F.\n\n\n \n\n\n\n IEEE Trans. Circuits Syst. II Express Briefs, 70(3): 1149–1153. 2023.\n \n\n\n\n
\n\n\n\n \n \n \"APaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@article{DBLP:journals/tcasII/JuracyAM23,\n  author       = {Leonardo Rezende Juracy and\n                  Alexandre M. Amory and\n                  Fernando Moraes},\n  title        = {A Comprehensive Evaluation of Convolutional Hardware Accelerators},\n  journal      = {{IEEE} Trans. Circuits Syst. {II} Express Briefs},\n  volume       = {70},\n  number       = {3},\n  pages        = {1149--1153},\n  year         = {2023},\n  url          = {https://doi.org/10.1109/TCSII.2022.3223925},\n  doi          = {10.1109/TCSII.2022.3223925},\n  timestamp    = {Tue, 28 Mar 2023 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/journals/tcasII/JuracyAM23.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Lightweight Authentication for Secure IO Communication in NoC-based Many-cores.\n \n \n \n \n\n\n \n Faccenda, R. F.; Comarú, G.; Caimi, L. L.; and Moraes, F. G.\n\n\n \n\n\n\n In IEEE International Symposium on Circuits and Systems, ISCAS 2023, Monterey, CA, USA, May 21-25, 2023, pages 1–5, 2023. IEEE\n \n\n\n\n
\n\n\n\n \n \n \"LightweightPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/iscas/FaccendaCCM23,\n  author       = {Rafael Follmann Faccenda and\n                  Gustavo Comar{\\'{u}} and\n                  Luciano Lores Caimi and\n                  Fernando Gehm Moraes},\n  title        = {Lightweight Authentication for Secure {IO} Communication in NoC-based\n                  Many-cores},\n  booktitle    = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2023,\n                  Monterey, CA, USA, May 21-25, 2023},\n  pages        = {1--5},\n  publisher    = {{IEEE}},\n  year         = {2023},\n  url          = {https://doi.org/10.1109/ISCAS46773.2023.10181962},\n  doi          = {10.1109/ISCAS46773.2023.10181962},\n  timestamp    = {Sun, 17 Dec 2023 00:00:00 +0100},\n  biburl       = {https://dblp.org/rec/conf/iscas/FaccendaCCM23.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Assessment of Communication Protocols' Latency in Co-processing Robotic Systems.\n \n \n \n \n\n\n \n Pereira, E.; Luza, L.; Moura, N.; Ost, L.; Calazans, N.; Moraes, F. G.; and Garibotti, R.\n\n\n \n\n\n\n In 21st IEEE Interregional NEWCAS Conference, NEWCAS 2023, Edinburgh, United Kingdom, June 26-28, 2023, pages 1–5, 2023. IEEE\n \n\n\n\n
\n\n\n\n \n \n \"AssessmentPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/newcas/PereiraLMOCMG23,\n  author       = {Eduardo Pereira and\n                  Lucas Luza and\n                  Nicolas Moura and\n                  Luciano Ost and\n                  Ney Calazans and\n                  Fernando Gehm Moraes and\n                  Rafael Garibotti},\n  title        = {Assessment of Communication Protocols' Latency in Co-processing Robotic\n                  Systems},\n  booktitle    = {21st {IEEE} Interregional {NEWCAS} Conference, {NEWCAS} 2023, Edinburgh,\n                  United Kingdom, June 26-28, 2023},\n  pages        = {1--5},\n  publisher    = {{IEEE}},\n  year         = {2023},\n  url          = {https://doi.org/10.1109/NEWCAS57931.2023.10198085},\n  doi          = {10.1109/NEWCAS57931.2023.10198085},\n  timestamp    = {Tue, 15 Aug 2023 11:43:59 +0200},\n  biburl       = {https://dblp.org/rec/conf/newcas/PereiraLMOCMG23.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Secure Network Interface for Protecting IO Communication in Many-cores.\n \n \n \n \n\n\n \n Comarú, G.; Faccenda, R. F.; Caimi, L. L.; and Moraes, F. G.\n\n\n \n\n\n\n In 36th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design, SBCCI 2023, Rio de Janeiro, Brazil, August 28 - Sept. 1, 2023, pages 1–6, 2023. IEEE\n \n\n\n\n
\n\n\n\n \n \n \"SecurePaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/sbcci/ComaruFCM23,\n  author       = {Gustavo Comar{\\'{u}} and\n                  Rafael Follmann Faccenda and\n                  Luciano Lores Caimi and\n                  Fernando Gehm Moraes},\n  title        = {Secure Network Interface for Protecting {IO} Communication in Many-cores},\n  booktitle    = {36th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems\n                  Design, {SBCCI} 2023, Rio de Janeiro, Brazil, August 28 - Sept. 1,\n                  2023},\n  pages        = {1--6},\n  publisher    = {{IEEE}},\n  year         = {2023},\n  url          = {https://doi.org/10.1109/SBCCI60457.2023.10261655},\n  doi          = {10.1109/SBCCI60457.2023.10261655},\n  timestamp    = {Sun, 12 Nov 2023 00:00:00 +0100},\n  biburl       = {https://dblp.org/rec/conf/sbcci/ComaruFCM23.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Improving the Efficiency of Cryptography Algorithms on Resource-Constrained Embedded Systems via RISC-V Instruction Set Extensions.\n \n \n \n \n\n\n \n de Araujo Gewehr, C. G.; and Moraes, F. G.\n\n\n \n\n\n\n In 36th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design, SBCCI 2023, Rio de Janeiro, Brazil, August 28 - Sept. 1, 2023, pages 1–6, 2023. IEEE\n \n\n\n\n
\n\n\n\n \n \n \"ImprovingPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/sbcci/GewehrM23,\n  author       = {Carlos Gabriel de Araujo Gewehr and\n                  Fernando Gehm Moraes},\n  title        = {Improving the Efficiency of Cryptography Algorithms on Resource-Constrained\n                  Embedded Systems via {RISC-V} Instruction Set Extensions},\n  booktitle    = {36th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems\n                  Design, {SBCCI} 2023, Rio de Janeiro, Brazil, August 28 - Sept. 1,\n                  2023},\n  pages        = {1--6},\n  publisher    = {{IEEE}},\n  year         = {2023},\n  url          = {https://doi.org/10.1109/SBCCI60457.2023.10261964},\n  doi          = {10.1109/SBCCI60457.2023.10261964},\n  timestamp    = {Wed, 11 Oct 2023 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/conf/sbcci/GewehrM23.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Assessment of Lightweight Cryptography Algorithms on ARM Cortex-M Processors.\n \n \n \n \n\n\n \n Moura, N.; Lucena, J.; Pereira, E.; Calazans, N.; Ost, L.; Moraes, F.; and Garibotti, R.\n\n\n \n\n\n\n In 36th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design, SBCCI 2023, Rio de Janeiro, Brazil, August 28 - Sept. 1, 2023, pages 1–6, 2023. IEEE\n \n\n\n\n
\n\n\n\n \n \n \"AssessmentPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/sbcci/MouraLPCOMG23,\n  author       = {Nicolas Moura and\n                  Joaquim Lucena and\n                  Eduardo Pereira and\n                  Ney Calazans and\n                  Luciano Ost and\n                  Fernando Moraes and\n                  Rafael Garibotti},\n  title        = {Assessment of Lightweight Cryptography Algorithms on {ARM} Cortex-M\n                  Processors},\n  booktitle    = {36th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems\n                  Design, {SBCCI} 2023, Rio de Janeiro, Brazil, August 28 - Sept. 1,\n                  2023},\n  pages        = {1--6},\n  publisher    = {{IEEE}},\n  year         = {2023},\n  url          = {https://doi.org/10.1109/SBCCI60457.2023.10261962},\n  doi          = {10.1109/SBCCI60457.2023.10261962},\n  timestamp    = {Wed, 11 Oct 2023 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/conf/sbcci/MouraLPCOMG23.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Validating an Automated Asynchronous Synthesis Environment with a Challenging Design: RISC-V.\n \n \n \n \n\n\n \n Nunes, W. A.; Sartori, M. L. L.; Moreira, M. T.; Moraes, F. G.; and Calazans, N. L. V.\n\n\n \n\n\n\n In 36th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design, SBCCI 2023, Rio de Janeiro, Brazil, August 28 - Sept. 1, 2023, pages 1–6, 2023. IEEE\n \n\n\n\n
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@inproceedings{DBLP:conf/sbcci/NunesSMMC23,\n  author       = {Willian Analdo Nunes and\n                  Marcos Luiggi Lemos Sartori and\n                  Matheus Trevisan Moreira and\n                  Fernando Gehm Moraes and\n                  Ney Laert Vilar Calazans},\n  title        = {Validating an Automated Asynchronous Synthesis Environment with a\n                  Challenging Design: {RISC-V}},\n  booktitle    = {36th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems\n                  Design, {SBCCI} 2023, Rio de Janeiro, Brazil, August 28 - Sept. 1,\n                  2023},\n  pages        = {1--6},\n  publisher    = {{IEEE}},\n  year         = {2023},\n  url          = {https://doi.org/10.1109/SBCCI60457.2023.10261656},\n  doi          = {10.1109/SBCCI60457.2023.10261656},\n  timestamp    = {Wed, 11 Oct 2023 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/conf/sbcci/NunesSMMC23.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Deploying Machine Learning in Resource-Constrained Devices for Human Activity Recognition.\n \n \n \n \n\n\n \n Reusch, R. S.; Juracy, L. R.; and Moraes, F. G.\n\n\n \n\n\n\n In XIII Brazilian Symposium on Computing Systems Engineering, SBESC 2023, Porto Alegre, Brazil, November 21-24, 2023, pages 1–6, 2023. IEEE\n \n\n\n\n
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@inproceedings{DBLP:conf/sbesc/ReuschJM23,\n  author       = {Rafael Schild Reusch and\n                  Leonardo Rezende Juracy and\n                  Fernando Gehm Moraes},\n  title        = {Deploying Machine Learning in Resource-Constrained Devices for Human\n                  Activity Recognition},\n  booktitle    = {{XIII} Brazilian Symposium on Computing Systems Engineering, {SBESC}\n                  2023, Porto Alegre, Brazil, November 21-24, 2023},\n  pages        = {1--6},\n  publisher    = {{IEEE}},\n  year         = {2023},\n  url          = {https://doi.org/10.1109/SBESC60926.2023.10324073},\n  doi          = {10.1109/SBESC60926.2023.10324073},\n  timestamp    = {Sat, 02 Dec 2023 14:05:35 +0100},\n  biburl       = {https://dblp.org/rec/conf/sbesc/ReuschJM23.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n FLEA - FIT-Aware Heuristic for Application Allocation in Many-Cores based on Q-Learning.\n \n \n \n \n\n\n \n Weber, I. I.; Zanini, V. B.; and Moraes, F. G.\n\n\n \n\n\n\n In XIII Brazilian Symposium on Computing Systems Engineering, SBESC 2023, Porto Alegre, Brazil, November 21-24, 2023, pages 1–6, 2023. IEEE\n \n\n\n\n
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@inproceedings{DBLP:conf/sbesc/WeberZM23,\n  author       = {Ia{\\c{c}}an{\\~{a}} I. Weber and\n                  Vitor Balbinot Zanini and\n                  Fernando Gehm Moraes},\n  title        = {{FLEA} - FIT-Aware Heuristic for Application Allocation in Many-Cores\n                  based on Q-Learning},\n  booktitle    = {{XIII} Brazilian Symposium on Computing Systems Engineering, {SBESC}\n                  2023, Porto Alegre, Brazil, November 21-24, 2023},\n  pages        = {1--6},\n  publisher    = {{IEEE}},\n  year         = {2023},\n  url          = {https://doi.org/10.1109/SBESC60926.2023.10324296},\n  doi          = {10.1109/SBESC60926.2023.10324296},\n  timestamp    = {Sat, 02 Dec 2023 00:00:00 +0100},\n  biburl       = {https://dblp.org/rec/conf/sbesc/WeberZM23.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n  \n 2022\n \n \n (10)\n \n \n
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\n \n\n \n \n \n \n \n \n Guest Editors' Introduction: SBCCI 2020.\n \n \n \n \n\n\n \n Moraes, F. G.; and Torres, F. S.\n\n\n \n\n\n\n IEEE Des. Test, 39(2): 5–6. 2022.\n \n\n\n\n
\n\n\n\n \n \n \"GuestPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@article{DBLP:journals/dt/MoraesT22,\n  author       = {Fernando Gehm Moraes and\n                  Frank Sill Torres},\n  title        = {Guest Editors' Introduction: {SBCCI} 2020},\n  journal      = {{IEEE} Des. Test},\n  volume       = {39},\n  number       = {2},\n  pages        = {5--6},\n  year         = {2022},\n  url          = {https://doi.org/10.1109/MDAT.2022.3140270},\n  doi          = {10.1109/MDAT.2022.3140270},\n  timestamp    = {Fri, 01 Apr 2022 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/journals/dt/MoraesT22.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n A Fast, Accurate, and Comprehensive PPA Estimation of Convolutional Hardware Accelerators.\n \n \n \n \n\n\n \n Juracy, L. R.; de Morais Amory, A.; and Moraes, F. G.\n\n\n \n\n\n\n IEEE Trans. Circuits Syst. I Regul. Pap., 69(12): 5171–5184. 2022.\n \n\n\n\n
\n\n\n\n \n \n \"APaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@article{DBLP:journals/tcasI/JuracyAM22,\n  author       = {Leonardo Rezende Juracy and\n                  Alexandre de Morais Amory and\n                  Fernando Gehm Moraes},\n  title        = {A Fast, Accurate, and Comprehensive {PPA} Estimation of Convolutional\n                  Hardware Accelerators},\n  journal      = {{IEEE} Trans. Circuits Syst. {I} Regul. Pap.},\n  volume       = {69},\n  number       = {12},\n  pages        = {5171--5184},\n  year         = {2022},\n  url          = {https://doi.org/10.1109/TCSI.2022.3204932},\n  doi          = {10.1109/TCSI.2022.3204932},\n  timestamp    = {Sun, 15 Jan 2023 00:00:00 +0100},\n  biburl       = {https://dblp.org/rec/journals/tcasI/JuracyAM22.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Leveraging NoC-based Many-core Performance Through Runtime Mapping Defragmentation.\n \n \n \n \n\n\n \n Dalzotto, A. E.; da Silva Borges, C.; Ruaro, M.; and Moraes, F. G.\n\n\n \n\n\n\n In 29th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2022, Glasgow, United Kingdom, October 24-26, 2022, pages 1–4, 2022. IEEE\n \n\n\n\n
\n\n\n\n \n \n \"LeveragingPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/icecsys/DalzottoBRM22,\n  author       = {Angelo Elias Dalzotto and\n                  Caroline da Silva Borges and\n                  Marcelo Ruaro and\n                  Fernando Gehm Moraes},\n  title        = {Leveraging NoC-based Many-core Performance Through Runtime Mapping\n                  Defragmentation},\n  booktitle    = {29th {IEEE} International Conference on Electronics, Circuits and\n                  Systems, {ICECS} 2022, Glasgow, United Kingdom, October 24-26, 2022},\n  pages        = {1--4},\n  publisher    = {{IEEE}},\n  year         = {2022},\n  url          = {https://doi.org/10.1109/ICECS202256217.2022.9970841},\n  doi          = {10.1109/ICECS202256217.2022.9970841},\n  timestamp    = {Fri, 23 Dec 2022 17:47:32 +0100},\n  biburl       = {https://dblp.org/rec/conf/icecsys/DalzottoBRM22.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Design-Time Scheduling of Periodic, Hard Real-Time Flows for NoC-based Systems.\n \n \n \n \n\n\n \n Domingues, A. R. P.; Filho, S. J.; de Morais Amory, A.; Ost, L.; and Moraes, F. G.\n\n\n \n\n\n\n In 29th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2022, Glasgow, United Kingdom, October 24-26, 2022, pages 1–4, 2022. IEEE\n \n\n\n\n
\n\n\n\n \n \n \"Design-TimePaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/icecsys/DominguesFAOM22,\n  author       = {Anderson R. P. Domingues and\n                  Sergio Johann Filho and\n                  Alexandre de Morais Amory and\n                  Luciano Ost and\n                  Fernando Gehm Moraes},\n  title        = {Design-Time Scheduling of Periodic, Hard Real-Time Flows for NoC-based\n                  Systems},\n  booktitle    = {29th {IEEE} International Conference on Electronics, Circuits and\n                  Systems, {ICECS} 2022, Glasgow, United Kingdom, October 24-26, 2022},\n  pages        = {1--4},\n  publisher    = {{IEEE}},\n  year         = {2022},\n  url          = {https://doi.org/10.1109/ICECS202256217.2022.9970868},\n  doi          = {10.1109/ICECS202256217.2022.9970868},\n  timestamp    = {Fri, 23 Dec 2022 00:00:00 +0100},\n  biburl       = {https://dblp.org/rec/conf/icecsys/DominguesFAOM22.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Reliability Assessment of Many-Core Dynamic Thermal Management.\n \n \n \n \n\n\n \n da Silva, A. H. L.; Weber, I. I.; Martins, A. L. D. M.; and Moraes, F. G.\n\n\n \n\n\n\n In IEEE International Symposium on Circuits and Systems, ISCAS 2022, Austin, TX, USA, May 27 - June 1, 2022, pages 1590–1594, 2022. IEEE\n \n\n\n\n
\n\n\n\n \n \n \"ReliabilityPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/iscas/SilvaWMM22,\n  author       = {Alzemiro Henrique Lucas da Silva and\n                  Ia{\\c{c}}an{\\~{a}} I. Weber and\n                  Andr{\\'{e}} Lu{\\'{\\i}}s Del Mestre Martins and\n                  Fernando Gehm Moraes},\n  title        = {Reliability Assessment of Many-Core Dynamic Thermal Management},\n  booktitle    = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2022,\n                  Austin, TX, USA, May 27 - June 1, 2022},\n  pages        = {1590--1594},\n  publisher    = {{IEEE}},\n  year         = {2022},\n  url          = {https://doi.org/10.1109/ISCAS48785.2022.9937286},\n  doi          = {10.1109/ISCAS48785.2022.9937286},\n  timestamp    = {Thu, 17 Nov 2022 15:59:17 +0100},\n  biburl       = {https://dblp.org/rec/conf/iscas/SilvaWMM22.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Design-Time Analysis of Real-Time Traffic for Networks-on-Chip using Constraint Models.\n \n \n \n \n\n\n \n Domingues, A. R. P.; Filho, S. J.; de Morais Amory, A.; and Moraes, F. G.\n\n\n \n\n\n\n In 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design, SBCCI 2022, Porto Alegre, Brazil, August 22-26, 2022, pages 1–6, 2022. IEEE\n \n\n\n\n
\n\n\n\n \n \n \"Design-TimePaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/sbcci/DominguesFAM22,\n  author       = {Anderson R. P. Domingues and\n                  Sergio Johann Filho and\n                  Alexandre de Morais Amory and\n                  Fernando Gehm Moraes},\n  title        = {Design-Time Analysis of Real-Time Traffic for Networks-on-Chip using\n                  Constraint Models},\n  booktitle    = {35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems\n                  Design, {SBCCI} 2022, Porto Alegre, Brazil, August 22-26, 2022},\n  pages        = {1--6},\n  publisher    = {{IEEE}},\n  year         = {2022},\n  url          = {https://doi.org/10.1109/SBCCI55532.2022.9893222},\n  doi          = {10.1109/SBCCI55532.2022.9893222},\n  timestamp    = {Thu, 06 Oct 2022 22:35:09 +0200},\n  biburl       = {https://dblp.org/rec/conf/sbcci/DominguesFAM22.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Secure Communication with Peripherals in NoC-based Many-cores.\n \n \n \n \n\n\n \n Faccenda, R. F.; Comarú, G.; Caimi, L. L.; and Moraes, F. G.\n\n\n \n\n\n\n In 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design, SBCCI 2022, Porto Alegre, Brazil, August 22-26, 2022, pages 1–6, 2022. IEEE\n \n\n\n\n
\n\n\n\n \n \n \"SecurePaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/sbcci/FaccendaCCM22,\n  author       = {Rafael Follmann Faccenda and\n                  Gustavo Comar{\\'{u}} and\n                  Luciano Lores Caimi and\n                  Fernando Gehm Moraes},\n  title        = {Secure Communication with Peripherals in NoC-based Many-cores},\n  booktitle    = {35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems\n                  Design, {SBCCI} 2022, Porto Alegre, Brazil, August 22-26, 2022},\n  pages        = {1--6},\n  publisher    = {{IEEE}},\n  year         = {2022},\n  url          = {https://doi.org/10.1109/SBCCI55532.2022.9893244},\n  doi          = {10.1109/SBCCI55532.2022.9893244},\n  timestamp    = {Sun, 17 Dec 2023 00:00:00 +0100},\n  biburl       = {https://dblp.org/rec/conf/sbcci/FaccendaCCM22.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n A High-level Model to Leverage NoC-based Many-core Research.\n \n \n \n \n\n\n \n Weber, I. I.; Dalzotto, A. E.; and Moraes, F. G.\n\n\n \n\n\n\n In 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design, SBCCI 2022, Porto Alegre, Brazil, August 22-26, 2022, pages 1–6, 2022. IEEE\n \n\n\n\n
\n\n\n\n \n \n \"APaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n  \n \n 1 download\n \n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/sbcci/WeberDM22,\n  author       = {Iacana Ianiski Weber and\n                  Angelo Elias Dalzotto and\n                  Fernando Gehm Moraes},\n  title        = {A High-level Model to Leverage NoC-based Many-core Research},\n  booktitle    = {35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems\n                  Design, {SBCCI} 2022, Porto Alegre, Brazil, August 22-26, 2022},\n  pages        = {1--6},\n  publisher    = {{IEEE}},\n  year         = {2022},\n  url          = {https://doi.org/10.1109/SBCCI55532.2022.9893235},\n  doi          = {10.1109/SBCCI55532.2022.9893235},\n  timestamp    = {Thu, 06 Oct 2022 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/conf/sbcci/WeberDM22.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Non-intrusive Monitoring Framework for NoC-based Many-Cores.\n \n \n \n \n\n\n \n Dalzotto, A. E.; da Silva Borges, C.; Ruaro, M.; and Moraes, F. G.\n\n\n \n\n\n\n In XII Brazilian Symposium on Computing Systems Engineering, SBESC 2022, Fortaleza, CE, Brazil, November 21-24, 2022, pages 1–7, 2022. IEEE\n \n\n\n\n
\n\n\n\n \n \n \"Non-intrusivePaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/sbesc/DalzottoBRM22,\n  author       = {Angelo Elias Dalzotto and\n                  Caroline da Silva Borges and\n                  Marcelo Ruaro and\n                  Fernando Gehm Moraes},\n  title        = {Non-intrusive Monitoring Framework for NoC-based Many-Cores},\n  booktitle    = {{XII} Brazilian Symposium on Computing Systems Engineering, {SBESC}\n                  2022, Fortaleza, CE, Brazil, November 21-24, 2022},\n  pages        = {1--7},\n  publisher    = {{IEEE}},\n  year         = {2022},\n  url          = {https://doi.org/10.1109/SBESC56799.2022.9965177},\n  doi          = {10.1109/SBESC56799.2022.9965177},\n  timestamp    = {Fri, 09 Dec 2022 16:46:51 +0100},\n  biburl       = {https://dblp.org/rec/conf/sbesc/DalzottoBRM22.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Assessment and Optimization of 1D CNN Model for Human Activity Recognition.\n \n \n \n \n\n\n \n Reusch, R. S.; Juracy, L. R.; and Moraes, F. G.\n\n\n \n\n\n\n In XII Brazilian Symposium on Computing Systems Engineering, SBESC 2022, Fortaleza, CE, Brazil, November 21-24, 2022, pages 1–7, 2022. IEEE\n \n\n\n\n
\n\n\n\n \n \n \"AssessmentPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/sbesc/ReuschJM22,\n  author       = {Rafael Schild Reusch and\n                  Leonardo Rezende Juracy and\n                  Fernando Gehm Moraes},\n  title        = {Assessment and Optimization of 1D {CNN} Model for Human Activity Recognition},\n  booktitle    = {{XII} Brazilian Symposium on Computing Systems Engineering, {SBESC}\n                  2022, Fortaleza, CE, Brazil, November 21-24, 2022},\n  pages        = {1--7},\n  publisher    = {{IEEE}},\n  year         = {2022},\n  url          = {https://doi.org/10.1109/SBESC56799.2022.9964520},\n  doi          = {10.1109/SBESC56799.2022.9964520},\n  timestamp    = {Fri, 09 Dec 2022 00:00:00 +0100},\n  biburl       = {https://dblp.org/rec/conf/sbesc/ReuschJM22.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n  \n 2021\n \n \n (10)\n \n \n
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\n \n\n \n \n \n \n \n \n Detection and Countermeasures of Security Attacks and Faults on NoC-Based Many-Cores.\n \n \n \n \n\n\n \n Faccenda, R. F.; Caimi, L. L.; and Moraes, F. G.\n\n\n \n\n\n\n IEEE Access, 9: 153142–153152. 2021.\n \n\n\n\n
\n\n\n\n \n \n \"DetectionPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@article{DBLP:journals/access/FaccendaCM21,\n  author       = {Rafael Follmann Faccenda and\n                  Luciano L. Caimi and\n                  Fernando Gehm Moraes},\n  title        = {Detection and Countermeasures of Security Attacks and Faults on NoC-Based\n                  Many-Cores},\n  journal      = {{IEEE} Access},\n  volume       = {9},\n  pages        = {153142--153152},\n  year         = {2021},\n  url          = {https://doi.org/10.1109/ACCESS.2021.3127468},\n  doi          = {10.1109/ACCESS.2021.3127468},\n  timestamp    = {Sun, 17 Dec 2023 00:00:00 +0100},\n  biburl       = {https://dblp.org/rec/journals/access/FaccendaCM21.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Hardware Accelerator for Runtime Temperature Estimation in Many-Cores.\n \n \n \n \n\n\n \n da Silva, A. L.; Weber, I. I.; Martins, A. L. D. M.; and Moraes, F. G.\n\n\n \n\n\n\n IEEE Des. Test, 38(4): 62–69. 2021.\n \n\n\n\n
\n\n\n\n \n \n \"HardwarePaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@article{DBLP:journals/dt/SilvaWMM21,\n  author       = {Alzemiro Lucas da Silva and\n                  Iacana Ianiski Weber and\n                  Andr{\\'{e}} Lu{\\'{\\i}}s Del Mestre Martins and\n                  Fernando Gehm Moraes},\n  title        = {Hardware Accelerator for Runtime Temperature Estimation in Many-Cores},\n  journal      = {{IEEE} Des. Test},\n  volume       = {38},\n  number       = {4},\n  pages        = {62--69},\n  year         = {2021},\n  url          = {https://doi.org/10.1109/MDAT.2021.3068914},\n  doi          = {10.1109/MDAT.2021.3068914},\n  timestamp    = {Thu, 16 Sep 2021 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/journals/dt/SilvaWMM21.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Security Vulnerabilities and Countermeasures in MPSoCs.\n \n \n \n \n\n\n \n Sant'Ana, A. C.; Medina, H. M.; and Moraes, F. G.\n\n\n \n\n\n\n IEEE Des. Test, 38(4): 70–77. 2021.\n \n\n\n\n
\n\n\n\n \n \n \"SecurityPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@article{DBLP:journals/dt/SantAnaMM21,\n  author       = {Anderson Camargo Sant'Ana and\n                  Henrique Martins Medina and\n                  Fernando Gehm Moraes},\n  title        = {Security Vulnerabilities and Countermeasures in MPSoCs},\n  journal      = {{IEEE} Des. Test},\n  volume       = {38},\n  number       = {4},\n  pages        = {70--77},\n  year         = {2021},\n  url          = {https://doi.org/10.1109/MDAT.2021.3049710},\n  doi          = {10.1109/MDAT.2021.3049710},\n  timestamp    = {Mon, 28 Aug 2023 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/journals/dt/SantAnaMM21.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Evaluation of the soft error assessment consistency of a JIT-based virtual platform simulator.\n \n \n \n \n\n\n \n Abich, G.; Garibotti, R.; Bandeira, V. V.; da Rosa, F.; Gava, J.; Bortolon, F. T.; Medeiros, G.; Moraes, F.; Reis, R.; and Ost, L.\n\n\n \n\n\n\n IET Comput. Digit. Tech., 15(2): 125–142. 2021.\n \n\n\n\n
\n\n\n\n \n \n \"EvaluationPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@article{DBLP:journals/iet-cdt/AbichGBRGBM00O21,\n  author       = {Geancarlo Abich and\n                  Rafael Garibotti and\n                  Vitor V. Bandeira and\n                  Felipe da Rosa and\n                  Jonas Gava and\n                  Felipe T. Bortolon and\n                  Guilherme Medeiros and\n                  Fernando Moraes and\n                  Ricardo Reis and\n                  Luciano Ost},\n  title        = {Evaluation of the soft error assessment consistency of a JIT-based\n                  virtual platform simulator},\n  journal      = {{IET} Comput. Digit. Tech.},\n  volume       = {15},\n  number       = {2},\n  pages        = {125--142},\n  year         = {2021},\n  url          = {https://doi.org/10.1049/cdt2.12017},\n  doi          = {10.1049/CDT2.12017},\n  timestamp    = {Thu, 13 Oct 2022 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/journals/iet-cdt/AbichGBRGBM00O21.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n A High-Level Modeling Framework for Estimating Hardware Metrics of CNN Accelerators.\n \n \n \n \n\n\n \n Juracy, L. R.; Moreira, M. T.; de Morais Amory, A.; Hampel, A. F.; and Moraes, F. G.\n\n\n \n\n\n\n IEEE Trans. Circuits Syst. I Regul. Pap., 68(11): 4783–4795. 2021.\n \n\n\n\n
\n\n\n\n \n \n \"APaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@article{DBLP:journals/tcasI/JuracyMAHM21,\n  author       = {Leonardo Rezende Juracy and\n                  Matheus Trevisan Moreira and\n                  Alexandre de Morais Amory and\n                  Alexandre F. Hampel and\n                  Fernando Gehm Moraes},\n  title        = {A High-Level Modeling Framework for Estimating Hardware Metrics of\n                  {CNN} Accelerators},\n  journal      = {{IEEE} Trans. Circuits Syst. {I} Regul. Pap.},\n  volume       = {68},\n  number       = {11},\n  pages        = {4783--4795},\n  year         = {2021},\n  url          = {https://doi.org/10.1109/TCSI.2021.3104644},\n  doi          = {10.1109/TCSI.2021.3104644},\n  timestamp    = {Wed, 15 Dec 2021 00:00:00 +0100},\n  biburl       = {https://dblp.org/rec/journals/tcasI/JuracyMAHM21.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Dynamic Mapping for Many-cores using Management Application Organization.\n \n \n \n \n\n\n \n Dalzotto, A. E.; Ruaro, M.; Erthal, L. V.; and Moraes, F. G.\n\n\n \n\n\n\n In 28th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2021, Dubai, United Arab Emirates, November 28 - Dec. 1, 2021, pages 1–6, 2021. IEEE\n \n\n\n\n
\n\n\n\n \n \n \"DynamicPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/icecsys/DalzottoREM21,\n  author       = {Angelo Elias Dalzotto and\n                  Marcelo Ruaro and\n                  Leonardo Vian Erthal and\n                  Fernando Gehm Moraes},\n  title        = {Dynamic Mapping for Many-cores using Management Application Organization},\n  booktitle    = {28th {IEEE} International Conference on Electronics, Circuits, and\n                  Systems, {ICECS} 2021, Dubai, United Arab Emirates, November 28 -\n                  Dec. 1, 2021},\n  pages        = {1--6},\n  publisher    = {{IEEE}},\n  year         = {2021},\n  url          = {https://doi.org/10.1109/ICECS53924.2021.9665547},\n  doi          = {10.1109/ICECS53924.2021.9665547},\n  timestamp    = {Sun, 02 Oct 2022 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/conf/icecsys/DalzottoREM21.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Dynamic Thermal Management in Many-Core Systems Leveraged by Abstract Modeling.\n \n \n \n \n\n\n \n da Silva, A. H. L.; Weber, I. I.; Martins, A. L. D. M.; and Moraes, F. G.\n\n\n \n\n\n\n In IEEE International Symposium on Circuits and Systems, ISCAS 2021, Daegu, South Korea, May 22-28, 2021, pages 1–5, 2021. IEEE\n \n\n\n\n
\n\n\n\n \n \n \"DynamicPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/iscas/SilvaWMM21,\n  author       = {Alzemiro Henrique Lucas da Silva and\n                  Ia{\\c{c}}an{\\~{a}} I. Weber and\n                  Andr{\\'{e}} Lu{\\'{\\i}}s Del Mestre Martins and\n                  Fernando Gehm Moraes},\n  title        = {Dynamic Thermal Management in Many-Core Systems Leveraged by Abstract\n                  Modeling},\n  booktitle    = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2021,\n                  Daegu, South Korea, May 22-28, 2021},\n  pages        = {1--5},\n  publisher    = {{IEEE}},\n  year         = {2021},\n  url          = {https://doi.org/10.1109/ISCAS51556.2021.9401414},\n  doi          = {10.1109/ISCAS51556.2021.9401414},\n  timestamp    = {Sun, 02 Oct 2022 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/conf/iscas/SilvaWMM21.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n A TensorFlow and System Simulator Integration Approach to Estimate Hardware Metrics of Convolution Accelerators.\n \n \n \n \n\n\n \n Juracy, L. R.; Moreira, M. T.; Amory, A. M.; and Moraes, F. G.\n\n\n \n\n\n\n In 12th IEEE Latin America Symposium on Circuits and System, LASCAS 2021, Arequipa, Peru, February 21-24, 2021, pages 1–4, 2021. IEEE\n \n\n\n\n
\n\n\n\n \n \n \"APaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/lascas/JuracyMAM21,\n  author       = {Leonardo Rezende Juracy and\n                  Matheus T. Moreira and\n                  Alexandre M. Amory and\n                  Fernando Gehm Moraes},\n  title        = {A TensorFlow and System Simulator Integration Approach to Estimate\n                  Hardware Metrics of Convolution Accelerators},\n  booktitle    = {12th {IEEE} Latin America Symposium on Circuits and System, {LASCAS}\n                  2021, Arequipa, Peru, February 21-24, 2021},\n  pages        = {1--4},\n  publisher    = {{IEEE}},\n  year         = {2021},\n  url          = {https://doi.org/10.1109/LASCAS51355.2021.9459183},\n  doi          = {10.1109/LASCAS51355.2021.9459183},\n  timestamp    = {Sun, 02 Oct 2022 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/conf/lascas/JuracyMAM21.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Chronos: An Abstract NoC-based Manycore with Preserved Temporal and Spatial Traffic Distribution.\n \n \n \n \n\n\n \n Lopes, G.; Weber, I. I.; Marcon, C. A. M.; and Moraes, F. G.\n\n\n \n\n\n\n In 12th IEEE Latin America Symposium on Circuits and System, LASCAS 2021, Arequipa, Peru, February 21-24, 2021, pages 1–4, 2021. IEEE\n \n\n\n\n
\n\n\n\n \n \n \"Chronos:Paper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/lascas/LopesWMM21,\n  author       = {Geaninne Lopes and\n                  Ia{\\c{c}}an{\\~{a}} I. Weber and\n                  C{\\'{e}}sar A. M. Marcon and\n                  Fernando Gehm Moraes},\n  title        = {Chronos: An Abstract NoC-based Manycore with Preserved Temporal and\n                  Spatial Traffic Distribution},\n  booktitle    = {12th {IEEE} Latin America Symposium on Circuits and System, {LASCAS}\n                  2021, Arequipa, Peru, February 21-24, 2021},\n  pages        = {1--4},\n  publisher    = {{IEEE}},\n  year         = {2021},\n  url          = {https://doi.org/10.1109/LASCAS51355.2021.9459124},\n  doi          = {10.1109/LASCAS51355.2021.9459124},\n  timestamp    = {Sun, 02 Oct 2022 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/conf/lascas/LopesWMM21.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n ORCA RT-Bench: A Reference Architecture for Real-Time Scheduling Simulators.\n \n \n \n \n\n\n \n Domingues, A. R. P.; Benno, J.; Amory, A. M.; and Moraes, F. G.\n\n\n \n\n\n\n In XI Brazilian Symposium on Computing Systems Engineering, SBESC 2021, Florianopolis, Brazil, November 22-26, 2021, pages 1–6, 2021. IEEE\n \n\n\n\n
\n\n\n\n \n \n \"ORCAPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/sbesc/DominguesBAM21,\n  author       = {Anderson R. P. Domingues and\n                  Jo{\\~{a}}o Benno and\n                  Alexandre M. Amory and\n                  Fernando Gehm Moraes},\n  title        = {{ORCA} RT-Bench: {A} Reference Architecture for Real-Time Scheduling\n                  Simulators},\n  booktitle    = {{XI} Brazilian Symposium on Computing Systems Engineering, {SBESC}\n                  2021, Florianopolis, Brazil, November 22-26, 2021},\n  pages        = {1--6},\n  publisher    = {{IEEE}},\n  year         = {2021},\n  url          = {https://doi.org/10.1109/SBESC53686.2021.9628369},\n  doi          = {10.1109/SBESC53686.2021.9628369},\n  timestamp    = {Sun, 02 Oct 2022 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/conf/sbesc/DominguesBAM21.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n  \n 2020\n \n \n (9)\n \n \n
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\n \n\n \n \n \n \n \n \n A Systemic and Secure SDN Framework for NoC-Based Many-Cores.\n \n \n \n \n\n\n \n Ruaro, M.; Caimi, L. L.; and Moraes, F. G.\n\n\n \n\n\n\n IEEE Access, 8: 105997–106008. 2020.\n \n\n\n\n
\n\n\n\n \n \n \"APaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@article{DBLP:journals/access/RuaroCM20,\n  author       = {Marcelo Ruaro and\n                  Luciano L. Caimi and\n                  Fernando Gehm Moraes},\n  title        = {A Systemic and Secure {SDN} Framework for NoC-Based Many-Cores},\n  journal      = {{IEEE} Access},\n  volume       = {8},\n  pages        = {105997--106008},\n  year         = {2020},\n  url          = {https://doi.org/10.1109/ACCESS.2020.3000457},\n  doi          = {10.1109/ACCESS.2020.3000457},\n  timestamp    = {Thu, 14 Oct 2021 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/journals/access/RuaroCM20.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n SDN-Based Secure Application Admission and Execution for Many-Cores.\n \n \n \n \n\n\n \n Ruaro, M.; Caimi, L. L.; and Moraes, F. G.\n\n\n \n\n\n\n IEEE Access, 8: 177296–177306. 2020.\n \n\n\n\n
\n\n\n\n \n \n \"SDN-BasedPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@article{DBLP:journals/access/RuaroCM20a,\n  author       = {Marcelo Ruaro and\n                  Luciano L. Caimi and\n                  Fernando Gehm Moraes},\n  title        = {SDN-Based Secure Application Admission and Execution for Many-Cores},\n  journal      = {{IEEE} Access},\n  volume       = {8},\n  pages        = {177296--177306},\n  year         = {2020},\n  url          = {https://doi.org/10.1109/ACCESS.2020.3025206},\n  doi          = {10.1109/ACCESS.2020.3025206},\n  timestamp    = {Tue, 20 Oct 2020 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/journals/access/RuaroCM20a.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Modular and Distributed Management of Many-Core SoCs.\n \n \n \n \n\n\n \n Ruaro, M.; Sant'Ana, A. C.; Jantsch, A.; and Moraes, F. G.\n\n\n \n\n\n\n ACM Trans. Comput. Syst., 38(1-2): 1:1–1:16. 2020.\n \n\n\n\n
\n\n\n\n \n \n \"ModularPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@article{DBLP:journals/tocs/RuaroSJM21,\n  author       = {Marcelo Ruaro and\n                  Anderson Camargo Sant'Ana and\n                  Axel Jantsch and\n                  Fernando Gehm Moraes},\n  title        = {Modular and Distributed Management of Many-Core SoCs},\n  journal      = {{ACM} Trans. Comput. Syst.},\n  volume       = {38},\n  number       = {1-2},\n  pages        = {1:1--1:16},\n  year         = {2020},\n  url          = {https://doi.org/10.1145/3458511},\n  doi          = {10.1145/3458511},\n  timestamp    = {Fri, 18 Nov 2022 00:00:00 +0100},\n  biburl       = {https://dblp.org/rec/journals/tocs/RuaroSJM21.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Lightweight Cryptographic Instruction Set Extension on Xtensa Processor.\n \n \n \n \n\n\n \n Eisenkraemer, G. H.; Moraes, F. G.; de Oliveira, L. L.; and Carara, E.\n\n\n \n\n\n\n In IEEE International Symposium on Circuits and Systems, ISCAS 2020, Sevilla, Spain, October 10-21, 2020, pages 1–5, 2020. IEEE\n \n\n\n\n
\n\n\n\n \n \n \"LightweightPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/iscas/EisenkraemerMOC20,\n  author       = {Gabriel H. Eisenkraemer and\n                  Fernando Gehm Moraes and\n                  Leonardo L. de Oliveira and\n                  Everton Carara},\n  title        = {Lightweight Cryptographic Instruction Set Extension on Xtensa Processor},\n  booktitle    = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2020,\n                  Sevilla, Spain, October 10-21, 2020},\n  pages        = {1--5},\n  publisher    = {{IEEE}},\n  year         = {2020},\n  url          = {https://doi.org/10.1109/ISCAS45731.2020.9180579},\n  doi          = {10.1109/ISCAS45731.2020.9180579},\n  timestamp    = {Sun, 02 Oct 2022 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/conf/iscas/EisenkraemerMOC20.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Open-Source NoC-Based Many-Core for Evaluating Hardware Trojan Detection Methods.\n \n \n \n \n\n\n \n Weber, I. I.; Marchezan, G.; Caimi, L. L.; Marcon, C. A. M.; and Moraes, F. G.\n\n\n \n\n\n\n In IEEE International Symposium on Circuits and Systems, ISCAS 2020, Sevilla, Spain, October 10-21, 2020, pages 1–5, 2020. IEEE\n \n\n\n\n
\n\n\n\n \n \n \"Open-SourcePaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/iscas/WeberMCMM20,\n  author       = {Ia{\\c{c}}an{\\~{a}} I. Weber and\n                  Geaninne Marchezan and\n                  Luciano L. Caimi and\n                  C{\\'{e}}sar A. M. Marcon and\n                  Fernando Gehm Moraes},\n  title        = {Open-Source NoC-Based Many-Core for Evaluating Hardware Trojan Detection\n                  Methods},\n  booktitle    = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2020,\n                  Sevilla, Spain, October 10-21, 2020},\n  pages        = {1--5},\n  publisher    = {{IEEE}},\n  year         = {2020},\n  url          = {https://doi.org/10.1109/ISCAS45731.2020.9180578},\n  doi          = {10.1109/ISCAS45731.2020.9180578},\n  timestamp    = {Sun, 02 Oct 2022 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/conf/iscas/WeberMCMM20.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Multiple-objective Management based on a Distributed SDN Architecture for Many-cores.\n \n \n \n \n\n\n \n Ruaro, M.; and Moraes, F. G.\n\n\n \n\n\n\n In 33rd Symposium on Integrated Circuits and Systems Design, SBCCI 2020, Campinas, Brazil, August 24-28, 2020, pages 1–6, 2020. IEEE\n \n\n\n\n
\n\n\n\n \n \n \"Multiple-objectivePaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/sbcci/RuaroM20,\n  author       = {Marcelo Ruaro and\n                  Fernando Gehm Moraes},\n  title        = {Multiple-objective Management based on a Distributed {SDN} Architecture\n                  for Many-cores},\n  booktitle    = {33rd Symposium on Integrated Circuits and Systems Design, {SBCCI}\n                  2020, Campinas, Brazil, August 24-28, 2020},\n  pages        = {1--6},\n  publisher    = {{IEEE}},\n  year         = {2020},\n  url          = {https://doi.org/10.1109/SBCCI50935.2020.9189905},\n  doi          = {10.1109/SBCCI50935.2020.9189905},\n  timestamp    = {Sun, 02 Oct 2022 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/conf/sbcci/RuaroM20.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Mapping and Migration Strategies for Thermal Management in Many-Core Systems.\n \n \n \n \n\n\n \n da Silva, A. L.; Martins, A. L. D. M.; and Moraes, F. G.\n\n\n \n\n\n\n In 33rd Symposium on Integrated Circuits and Systems Design, SBCCI 2020, Campinas, Brazil, August 24-28, 2020, pages 1–6, 2020. IEEE\n \n\n\n\n
\n\n\n\n \n \n \"MappingPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/sbcci/SilvaMM20,\n  author       = {Alzemiro Lucas da Silva and\n                  Andr{\\'{e}} Lu{\\'{\\i}}s Del Mestre Martins and\n                  Fernando Gehm Moraes},\n  title        = {Mapping and Migration Strategies for Thermal Management in Many-Core\n                  Systems},\n  booktitle    = {33rd Symposium on Integrated Circuits and Systems Design, {SBCCI}\n                  2020, Campinas, Brazil, August 24-28, 2020},\n  pages        = {1--6},\n  publisher    = {{IEEE}},\n  year         = {2020},\n  url          = {https://doi.org/10.1109/SBCCI50935.2020.9189933},\n  doi          = {10.1109/SBCCI50935.2020.9189933},\n  timestamp    = {Sun, 02 Oct 2022 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/conf/sbcci/SilvaMM20.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Reducing NoC Energy Consumption Exploring Asynchronous End-to-end GALS Communication.\n \n \n \n \n\n\n \n Weber, I. I.; de Oliveira, L. L.; Carara, E.; and Moraes, F. G.\n\n\n \n\n\n\n In 33rd Symposium on Integrated Circuits and Systems Design, SBCCI 2020, Campinas, Brazil, August 24-28, 2020, pages 1–6, 2020. IEEE\n \n\n\n\n
\n\n\n\n \n \n \"ReducingPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/sbcci/WeberOCM20,\n  author       = {Ia{\\c{c}}an{\\~{a}} I. Weber and\n                  Leonardo Londero de Oliveira and\n                  Everton Carara and\n                  Fernando Gehm Moraes},\n  title        = {Reducing NoC Energy Consumption Exploring Asynchronous End-to-end\n                  {GALS} Communication},\n  booktitle    = {33rd Symposium on Integrated Circuits and Systems Design, {SBCCI}\n                  2020, Campinas, Brazil, August 24-28, 2020},\n  pages        = {1--6},\n  publisher    = {{IEEE}},\n  year         = {2020},\n  url          = {https://doi.org/10.1109/SBCCI50935.2020.9189896},\n  doi          = {10.1109/SBCCI50935.2020.9189896},\n  timestamp    = {Sun, 02 Oct 2022 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/conf/sbcci/WeberOCM20.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n A Survey of Aging Monitors and Reconfiguration Techniques.\n \n \n \n \n\n\n \n Juracy, L. R.; Moreira, M. T.; de Morais Amory, A.; and Moraes, F. G.\n\n\n \n\n\n\n CoRR, abs/2007.07829. 2020.\n \n\n\n\n
\n\n\n\n \n \n \"APaper\n  \n \n\n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@article{DBLP:journals/corr/abs-2007-07829,\n  author       = {Leonardo Rezende Juracy and\n                  Matheus Trevisan Moreira and\n                  Alexandre de Morais Amory and\n                  Fernando Gehm Moraes},\n  title        = {A Survey of Aging Monitors and Reconfiguration Techniques},\n  journal      = {CoRR},\n  volume       = {abs/2007.07829},\n  year         = {2020},\n  url          = {https://arxiv.org/abs/2007.07829},\n  eprinttype    = {arXiv},\n  eprint       = {2007.07829},\n  timestamp    = {Tue, 21 Jul 2020 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/journals/corr/abs-2007-07829.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n  \n 2019\n \n \n (11)\n \n \n
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\n \n\n \n \n \n \n \n \n Memphis: a framework for heterogeneous many-core SoCs generation and validation.\n \n \n \n \n\n\n \n Ruaro, M.; Caimi, L. L.; Fochi, V.; and Moraes, F. G.\n\n\n \n\n\n\n Des. Autom. Embed. Syst., 23(3-4): 103–122. 2019.\n \n\n\n\n
\n\n\n\n \n \n \"Memphis:Paper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@article{DBLP:journals/dafes/RuaroCFM19,\n  author       = {Marcelo Ruaro and\n                  Luciano L. Caimi and\n                  Vinicius Fochi and\n                  Fernando Gehm Moraes},\n  title        = {Memphis: a framework for heterogeneous many-core SoCs generation and\n                  validation},\n  journal      = {Des. Autom. Embed. Syst.},\n  volume       = {23},\n  number       = {3-4},\n  pages        = {103--122},\n  year         = {2019},\n  url          = {https://doi.org/10.1007/s10617-019-09223-4},\n  doi          = {10.1007/S10617-019-09223-4},\n  timestamp    = {Mon, 26 Oct 2020 00:00:00 +0100},\n  biburl       = {https://dblp.org/rec/journals/dafes/RuaroCFM19.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n The power impact of hardware and software actuators on self-adaptable many-core systems.\n \n \n \n \n\n\n \n Martins, A. L. D. M.; Garibotti, R.; Dutt, N. D.; and Moraes, F. G.\n\n\n \n\n\n\n J. Syst. Archit., 97: 42–53. 2019.\n \n\n\n\n
\n\n\n\n \n \n \"ThePaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@article{DBLP:journals/jsa/MartinsGDM19,\n  author       = {Andr{\\'{e}} Lu{\\'{\\i}}s Del Mestre Martins and\n                  Rafael Garibotti and\n                  Nikil D. Dutt and\n                  Fernando Gehm Moraes},\n  title        = {The power impact of hardware and software actuators on self-adaptable\n                  many-core systems},\n  journal      = {J. Syst. Archit.},\n  volume       = {97},\n  pages        = {42--53},\n  year         = {2019},\n  url          = {https://doi.org/10.1016/j.sysarc.2019.05.006},\n  doi          = {10.1016/J.SYSARC.2019.05.006},\n  timestamp    = {Sun, 02 Oct 2022 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/journals/jsa/MartinsGDM19.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Hierarchical adaptive Multi-objective resource management for many-core systems.\n \n \n \n \n\n\n \n Martins, A. L. D. M.; da Silva, A. H. L.; Rahmani, A. M.; Dutt, N. D.; and Moraes, F. G.\n\n\n \n\n\n\n J. Syst. Archit., 97: 416–427. 2019.\n \n\n\n\n
\n\n\n\n \n \n \"HierarchicalPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@article{DBLP:journals/jsa/MartinsSRDM19,\n  author       = {Andr{\\'{e}} Lu{\\'{\\i}}s Del Mestre Martins and\n                  Alzemiro Henrique Lucas da Silva and\n                  Amir M. Rahmani and\n                  Nikil D. Dutt and\n                  Fernando Gehm Moraes},\n  title        = {Hierarchical adaptive Multi-objective resource management for many-core\n                  systems},\n  journal      = {J. Syst. Archit.},\n  volume       = {97},\n  pages        = {416--427},\n  year         = {2019},\n  url          = {https://doi.org/10.1016/j.sysarc.2019.01.006},\n  doi          = {10.1016/J.SYSARC.2019.01.006},\n  timestamp    = {Sun, 02 Oct 2022 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/journals/jsa/MartinsSRDM19.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Self-Adaptive QoS Management of Computation and Communication Resources in Many-Core SoCs.\n \n \n \n \n\n\n \n Ruaro, M.; Jantsch, A.; and Moraes, F. G.\n\n\n \n\n\n\n ACM Trans. Embed. Comput. Syst., 18(4): 37:1–37:21. 2019.\n \n\n\n\n
\n\n\n\n \n \n \"Self-AdaptivePaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@article{DBLP:journals/tecs/RuaroJM19,\n  author       = {Marcelo Ruaro and\n                  Axel Jantsch and\n                  Fernando Gehm Moraes},\n  title        = {Self-Adaptive QoS Management of Computation and Communication Resources\n                  in Many-Core SoCs},\n  journal      = {{ACM} Trans. Embed. Comput. Syst.},\n  volume       = {18},\n  number       = {4},\n  pages        = {37:1--37:21},\n  year         = {2019},\n  url          = {https://doi.org/10.1145/3328755},\n  doi          = {10.1145/3328755},\n  timestamp    = {Sat, 08 Jan 2022 00:00:00 +0100},\n  biburl       = {https://dblp.org/rec/journals/tecs/RuaroJM19.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Security in Many-Core SoCs Leveraged by Opaque Secure Zones.\n \n \n \n \n\n\n \n Caimi, L. L.; and Moraes, F. G.\n\n\n \n\n\n\n In 2019 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2019, Miami, FL, USA, July 15-17, 2019, pages 471–476, 2019. IEEE\n \n\n\n\n
\n\n\n\n \n \n \"SecurityPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/isvlsi/CaimiM19,\n  author       = {Luciano L. Caimi and\n                  Fernando Gehm Moraes},\n  title        = {Security in Many-Core SoCs Leveraged by Opaque Secure Zones},\n  booktitle    = {2019 {IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2019,\n                  Miami, FL, USA, July 15-17, 2019},\n  pages        = {471--476},\n  publisher    = {{IEEE}},\n  year         = {2019},\n  url          = {https://doi.org/10.1109/ISVLSI.2019.00091},\n  doi          = {10.1109/ISVLSI.2019.00091},\n  timestamp    = {Sun, 02 Oct 2022 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/conf/isvlsi/CaimiM19.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n A Framework for Heterogeneous Many-core SoCs Generation.\n \n \n \n \n\n\n \n Ruaro, M.; Caimi, L. L.; Fochi, V.; and Moraes, F. G.\n\n\n \n\n\n\n In Murphy, R. S., editor(s), 10th IEEE Latin American Symposium on Circuits & Systems, LASCAS 2019, Armenia, Colombia, February 24-27, 2019, pages 89–92, 2019. IEEE\n \n\n\n\n
\n\n\n\n \n \n \"APaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/lascas/RuaroCFM19,\n  author       = {Marcelo Ruaro and\n                  Luciano L. Caimi and\n                  Vinicius Fochi and\n                  Fernando Gehm Moraes},\n  editor       = {Roberto S. Murphy},\n  title        = {A Framework for Heterogeneous Many-core SoCs Generation},\n  booktitle    = {10th {IEEE} Latin American Symposium on Circuits {\\&} Systems, {LASCAS}\n                  2019, Armenia, Colombia, February 24-27, 2019},\n  pages        = {89--92},\n  publisher    = {{IEEE}},\n  year         = {2019},\n  url          = {https://doi.org/10.1109/LASCAS.2019.8667590},\n  doi          = {10.1109/LASCAS.2019.8667590},\n  timestamp    = {Sun, 02 Oct 2022 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/conf/lascas/RuaroCFM19.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Distributed SDN architecture for NoC-based many-core SoCs.\n \n \n \n \n\n\n \n Ruaro, M.; Velloso, N.; Jantsch, A.; and Moraes, F. G.\n\n\n \n\n\n\n In Bogdan, P.; and Silvano, C., editor(s), Proceedings of the 13th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2019, New York, NY, USA, October 17-18, 2019, pages 8:1–8:8, 2019. ACM\n \n\n\n\n
\n\n\n\n \n \n \"DistributedPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/nocs/RuaroVJM19,\n  author       = {Marcelo Ruaro and\n                  Nedison Velloso and\n                  Axel Jantsch and\n                  Fernando Gehm Moraes},\n  editor       = {Paul Bogdan and\n                  Cristina Silvano},\n  title        = {Distributed {SDN} architecture for NoC-based many-core SoCs},\n  booktitle    = {Proceedings of the 13th {IEEE/ACM} International Symposium on Networks-on-Chip,\n                  {NOCS} 2019, New York, NY, USA, October 17-18, 2019},\n  pages        = {8:1--8:8},\n  publisher    = {{ACM}},\n  year         = {2019},\n  url          = {https://doi.org/10.1145/3313231.3352361},\n  doi          = {10.1145/3313231.3352361},\n  timestamp    = {Sun, 02 Oct 2022 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/conf/nocs/RuaroVJM19.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Lightweight security mechanisms for MPSoCs.\n \n \n \n \n\n\n \n Sant'Ana, A. C.; Medina, H. M.; Fiorentin, K. B.; and Moraes, F. G.\n\n\n \n\n\n\n In Martino, J. A.; Lubaszewski, M.; and Reorda, M. S., editor(s), Proceedings of the 32nd Symposium on Integrated Circuits and Systems Design, SBCCI 2019, Sao Paulo, Brazil, August 26-30, 2019, pages 2, 2019. ACM\n \n\n\n\n
\n\n\n\n \n \n \"LightweightPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/sbcci/SantAnaMFM19,\n  author       = {Anderson Camargo Sant'Ana and\n                  Henrique Martins Medina and\n                  Kevin Boucinha Fiorentin and\n                  Fernando Gehm Moraes},\n  editor       = {Jo{\\~{a}}o Antonio Martino and\n                  Marcelo Lubaszewski and\n                  Matteo Sonza Reorda},\n  title        = {Lightweight security mechanisms for MPSoCs},\n  booktitle    = {Proceedings of the 32nd Symposium on Integrated Circuits and Systems\n                  Design, {SBCCI} 2019, Sao Paulo, Brazil, August 26-30, 2019},\n  pages        = {2},\n  publisher    = {{ACM}},\n  year         = {2019},\n  url          = {https://doi.org/10.1145/3338852.3339876},\n  doi          = {10.1145/3338852.3339876},\n  timestamp    = {Sun, 02 Oct 2022 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/conf/sbcci/SantAnaMFM19.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Fine-grain temperature monitoring for many-core systems.\n \n \n \n \n\n\n \n da Silva, A. H. L.; Martins, A. L. D. M.; and Moraes, F. G.\n\n\n \n\n\n\n In Martino, J. A.; Lubaszewski, M.; and Reorda, M. S., editor(s), Proceedings of the 32nd Symposium on Integrated Circuits and Systems Design, SBCCI 2019, Sao Paulo, Brazil, August 26-30, 2019, pages 4, 2019. ACM\n \n\n\n\n
\n\n\n\n \n \n \"Fine-grainPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/sbcci/SilvaMM19,\n  author       = {Alzemiro Henrique Lucas da Silva and\n                  Andr{\\'{e}} Lu{\\'{\\i}}s Del Mestre Martins and\n                  Fernando Gehm Moraes},\n  editor       = {Jo{\\~{a}}o Antonio Martino and\n                  Marcelo Lubaszewski and\n                  Matteo Sonza Reorda},\n  title        = {Fine-grain temperature monitoring for many-core systems},\n  booktitle    = {Proceedings of the 32nd Symposium on Integrated Circuits and Systems\n                  Design, {SBCCI} 2019, Sao Paulo, Brazil, August 26-30, 2019},\n  pages        = {4},\n  publisher    = {{ACM}},\n  year         = {2019},\n  url          = {https://doi.org/10.1145/3338852.3339841},\n  doi          = {10.1145/3338852.3339841},\n  timestamp    = {Sun, 02 Oct 2022 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/conf/sbcci/SilvaMM19.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n A FPGA parameterizable multi-layer architecture for CNNs.\n \n \n \n \n\n\n \n Korol, G.; and Moraes, F. G.\n\n\n \n\n\n\n In Martino, J. A.; Lubaszewski, M.; and Reorda, M. S., editor(s), Proceedings of the 32nd Symposium on Integrated Circuits and Systems Design, SBCCI 2019, Sao Paulo, Brazil, August 26-30, 2019, pages 30, 2019. ACM\n \n\n\n\n
\n\n\n\n \n \n \"APaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/sbcci/KorolM19,\n  author       = {Guilherme Korol and\n                  Fernando Gehm Moraes},\n  editor       = {Jo{\\~{a}}o Antonio Martino and\n                  Marcelo Lubaszewski and\n                  Matteo Sonza Reorda},\n  title        = {A {FPGA} parameterizable multi-layer architecture for CNNs},\n  booktitle    = {Proceedings of the 32nd Symposium on Integrated Circuits and Systems\n                  Design, {SBCCI} 2019, Sao Paulo, Brazil, August 26-30, 2019},\n  pages        = {30},\n  publisher    = {{ACM}},\n  year         = {2019},\n  url          = {https://doi.org/10.1145/3338852.3339840},\n  doi          = {10.1145/3338852.3339840},\n  timestamp    = {Sun, 02 Oct 2022 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/conf/sbcci/KorolM19.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n An IR-UWB pulse generator using PAM modulation with adaptive PSD in 130nm CMOS process.\n \n \n \n \n\n\n \n Moreira, L. C.; Neto, J. F.; Oliveira, W. S.; Ferauche, T.; Heck, G.; Calazans, N. L. V.; and Moraes, F. G.\n\n\n \n\n\n\n In Martino, J. A.; Lubaszewski, M.; and Reorda, M. S., editor(s), Proceedings of the 32nd Symposium on Integrated Circuits and Systems Design, SBCCI 2019, Sao Paulo, Brazil, August 26-30, 2019, pages 34, 2019. ACM\n \n\n\n\n
\n\n\n\n \n \n \"AnPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/sbcci/MoreiraNOFHCM19,\n  author       = {Luiz Carlos Moreira and\n                  Jos{\\'{e}} Fontebasso Neto and\n                  Walter Silva Oliveira and\n                  Thiago Ferauche and\n                  Guilherme Heck and\n                  Ney Laert Vilar Calazans and\n                  Fernando Gehm Moraes},\n  editor       = {Jo{\\~{a}}o Antonio Martino and\n                  Marcelo Lubaszewski and\n                  Matteo Sonza Reorda},\n  title        = {An {IR-UWB} pulse generator using {PAM} modulation with adaptive {PSD}\n                  in 130nm {CMOS} process},\n  booktitle    = {Proceedings of the 32nd Symposium on Integrated Circuits and Systems\n                  Design, {SBCCI} 2019, Sao Paulo, Brazil, August 26-30, 2019},\n  pages        = {34},\n  publisher    = {{ACM}},\n  year         = {2019},\n  url          = {https://doi.org/10.1145/3338852.3339860},\n  doi          = {10.1145/3338852.3339860},\n  timestamp    = {Sun, 02 Oct 2022 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/conf/sbcci/MoreiraNOFHCM19.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n  \n 2018\n \n \n (12)\n \n \n
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\n \n\n \n \n \n \n \n \n A Hierarchical and Distributed Fault Tolerant Proposal for NoC-Based MPSoCs.\n \n \n \n \n\n\n \n Wächter, E.; Fochi, V.; Barreto, F. F. S.; Amory, A. M.; and Moraes, F.\n\n\n \n\n\n\n IEEE Trans. Emerg. Top. Comput., 6(4): 524–537. 2018.\n \n\n\n\n
\n\n\n\n \n \n \"APaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@article{DBLP:journals/tetc/WachterFBAM18,\n  author       = {Eduardo W{\\"{a}}chter and\n                  Vinicius Fochi and\n                  Francisco F. S. Barreto and\n                  Alexandre M. Amory and\n                  Fernando Moraes},\n  title        = {A Hierarchical and Distributed Fault Tolerant Proposal for NoC-Based\n                  MPSoCs},\n  journal      = {{IEEE} Trans. Emerg. Top. Comput.},\n  volume       = {6},\n  number       = {4},\n  pages        = {524--537},\n  year         = {2018},\n  url          = {https://doi.org/10.1109/TETC.2016.2593640},\n  doi          = {10.1109/TETC.2016.2593640},\n  timestamp    = {Fri, 15 May 2020 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/journals/tetc/WachterFBAM18.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Exploring RSA Performance up to 4096-bit for Fast Security Processing on a Flexible Instruction Set Architecture Processor.\n \n \n \n \n\n\n \n Marchesan, G. C.; Weirich, N. R.; Culau, E. C.; Weber, I. I.; Moraes, F. G.; Carara, E.; and de Oliveira, L. L.\n\n\n \n\n\n\n In 25th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2018, Bordeaux, France, December 9-12, 2018, pages 757–760, 2018. IEEE\n \n\n\n\n
\n\n\n\n \n \n \"ExploringPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/icecsys/MarchesanWCWMCO18,\n  author       = {Gr{\\'{e}}gory C. Marchesan and\n                  Nelson R. Weirich and\n                  Eduardo C. Culau and\n                  Iacana Ianiski Weber and\n                  Fernando Gehm Moraes and\n                  Everton Carara and\n                  Leonardo Londero de Oliveira},\n  title        = {Exploring {RSA} Performance up to 4096-bit for Fast Security Processing\n                  on a Flexible Instruction Set Architecture Processor},\n  booktitle    = {25th {IEEE} International Conference on Electronics, Circuits and\n                  Systems, {ICECS} 2018, Bordeaux, France, December 9-12, 2018},\n  pages        = {757--760},\n  publisher    = {{IEEE}},\n  year         = {2018},\n  url          = {https://doi.org/10.1109/ICECS.2018.8617840},\n  doi          = {10.1109/ICECS.2018.8617840},\n  timestamp    = {Sun, 02 Oct 2022 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/conf/icecsys/MarchesanWCWMCO18.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Secure Admission of Applications in Many-cores.\n \n \n \n \n\n\n \n Caimi, L. L.; Fochi, V.; and Moraes, F. G.\n\n\n \n\n\n\n In 25th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2018, Bordeaux, France, December 9-12, 2018, pages 761–764, 2018. IEEE\n \n\n\n\n
\n\n\n\n \n \n \"SecurePaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/icecsys/CaimiFM18,\n  author       = {Luciano L. Caimi and\n                  Vinicius Fochi and\n                  Fernando Gehm Moraes},\n  title        = {Secure Admission of Applications in Many-cores},\n  booktitle    = {25th {IEEE} International Conference on Electronics, Circuits and\n                  Systems, {ICECS} 2018, Bordeaux, France, December 9-12, 2018},\n  pages        = {761--764},\n  publisher    = {{IEEE}},\n  year         = {2018},\n  url          = {https://doi.org/10.1109/ICECS.2018.8618021},\n  doi          = {10.1109/ICECS.2018.8618021},\n  timestamp    = {Sun, 02 Oct 2022 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/conf/icecsys/CaimiFM18.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Evaluating Serialization for a Publish-Subscribe Based Middleware for MPSoCs.\n \n \n \n \n\n\n \n Hamerski, J. C.; Domingues, A. R. P.; Moraes, F. G.; and Amory, A. M.\n\n\n \n\n\n\n In 25th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2018, Bordeaux, France, December 9-12, 2018, pages 773–776, 2018. IEEE\n \n\n\n\n
\n\n\n\n \n \n \"EvaluatingPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/icecsys/HamerskiDMA18,\n  author       = {Jean Carlo Hamerski and\n                  Anderson R. P. Domingues and\n                  Fernando Gehm Moraes and\n                  Alexandre M. Amory},\n  title        = {Evaluating Serialization for a Publish-Subscribe Based Middleware\n                  for MPSoCs},\n  booktitle    = {25th {IEEE} International Conference on Electronics, Circuits and\n                  Systems, {ICECS} 2018, Bordeaux, France, December 9-12, 2018},\n  pages        = {773--776},\n  publisher    = {{IEEE}},\n  year         = {2018},\n  url          = {https://doi.org/10.1109/ICECS.2018.8618003},\n  doi          = {10.1109/ICECS.2018.8618003},\n  timestamp    = {Sun, 02 Oct 2022 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/conf/icecsys/HamerskiDMA18.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Exploring the Impact of Soft Errors on NoC-based Multiprocessor Systems.\n \n \n \n \n\n\n \n Bortolon, F. T.; Abich, G.; Bampi, S.; Reis, R.; Moraes, F.; and Ost, L.\n\n\n \n\n\n\n In IEEE International Symposium on Circuits and Systems, ISCAS 2018, 27-30 May 2018, Florence, Italy, pages 1–5, 2018. IEEE\n \n\n\n\n
\n\n\n\n \n \n \"ExploringPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/iscas/BortolonABRMO18,\n  author       = {Felipe T. Bortolon and\n                  Geancarlo Abich and\n                  Sergio Bampi and\n                  Ricardo Reis and\n                  Fernando Moraes and\n                  Luciano Ost},\n  title        = {Exploring the Impact of Soft Errors on NoC-based Multiprocessor Systems},\n  booktitle    = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2018,\n                  27-30 May 2018, Florence, Italy},\n  pages        = {1--5},\n  publisher    = {{IEEE}},\n  year         = {2018},\n  url          = {https://doi.org/10.1109/ISCAS.2018.8351391},\n  doi          = {10.1109/ISCAS.2018.8351391},\n  timestamp    = {Sat, 30 Sep 2023 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/conf/iscas/BortolonABRMO18.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n An LSSD Compliant Scan Cell for Flip-Flops.\n \n \n \n \n\n\n \n Juracy, L. R.; Moreira, M. T.; Kuentzer, F. A.; Moraes, F. G.; and Amory, A. M.\n\n\n \n\n\n\n In IEEE International Symposium on Circuits and Systems, ISCAS 2018, 27-30 May 2018, Florence, Italy, pages 1–5, 2018. IEEE\n \n\n\n\n
\n\n\n\n \n \n \"AnPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/iscas/JuracyMKMA18,\n  author       = {Leonardo Rezende Juracy and\n                  Matheus T. Moreira and\n                  Felipe A. Kuentzer and\n                  Fernando Gehm Moraes and\n                  Alexandre M. Amory},\n  title        = {An {LSSD} Compliant Scan Cell for Flip-Flops},\n  booktitle    = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2018,\n                  27-30 May 2018, Florence, Italy},\n  pages        = {1--5},\n  publisher    = {{IEEE}},\n  year         = {2018},\n  url          = {https://doi.org/10.1109/ISCAS.2018.8351515},\n  doi          = {10.1109/ISCAS.2018.8351515},\n  timestamp    = {Sun, 02 Oct 2022 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/conf/iscas/JuracyMKMA18.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Software-Defined Networking Architecture for NoC-based Many-Cores.\n \n \n \n \n\n\n \n Ruaro, M.; Medina, H. M.; Amory, A. M.; and Moraes, F. G.\n\n\n \n\n\n\n In IEEE International Symposium on Circuits and Systems, ISCAS 2018, 27-30 May 2018, Florence, Italy, pages 1–5, 2018. IEEE\n \n\n\n\n
\n\n\n\n \n \n \"Software-DefinedPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/iscas/RuaroMAM18,\n  author       = {Marcelo Ruaro and\n                  Henrique Martins Medina and\n                  Alexandre M. Amory and\n                  Fernando Gehm Moraes},\n  title        = {Software-Defined Networking Architecture for NoC-based Many-Cores},\n  booktitle    = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2018,\n                  27-30 May 2018, Florence, Italy},\n  pages        = {1--5},\n  publisher    = {{IEEE}},\n  year         = {2018},\n  url          = {https://doi.org/10.1109/ISCAS.2018.8351830},\n  doi          = {10.1109/ISCAS.2018.8351830},\n  timestamp    = {Sun, 02 Oct 2022 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/conf/iscas/RuaroMAM18.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Runtime creation of continuous secure zones in many-core systems for secure applications.\n \n \n \n \n\n\n \n Caimi, L. L.; Fochi, V.; Wächter, E.; and Moraes, F. G.\n\n\n \n\n\n\n In 9th IEEE Latin American Symposium on Circuits & Systems, LASCAS 2018, Puerto Vallarta, Mexico, February 25-28, 2018, pages 1–4, 2018. IEEE\n \n\n\n\n
\n\n\n\n \n \n \"RuntimePaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/lascas/CaimiFWM18,\n  author       = {Luciano L. Caimi and\n                  Vinicius Fochi and\n                  Eduardo W{\\"{a}}chter and\n                  Fernando Gehm Moraes},\n  title        = {Runtime creation of continuous secure zones in many-core systems for\n                  secure applications},\n  booktitle    = {9th {IEEE} Latin American Symposium on Circuits {\\&} Systems, {LASCAS}\n                  2018, Puerto Vallarta, Mexico, February 25-28, 2018},\n  pages        = {1--4},\n  publisher    = {{IEEE}},\n  year         = {2018},\n  url          = {https://doi.org/10.1109/LASCAS.2018.8399904},\n  doi          = {10.1109/LASCAS.2018.8399904},\n  timestamp    = {Sun, 02 Oct 2022 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/conf/lascas/CaimiFWM18.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Evaluating the cost to cipher the NoC communication.\n \n \n \n \n\n\n \n Oliveira, B. S.; Reusch, R. S.; Medina, H. M.; and Moraes, F.\n\n\n \n\n\n\n In 9th IEEE Latin American Symposium on Circuits & Systems, LASCAS 2018, Puerto Vallarta, Mexico, February 25-28, 2018, pages 1–4, 2018. IEEE\n \n\n\n\n
\n\n\n\n \n \n \"EvaluatingPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/lascas/OliveiraRMM18,\n  author       = {Bruno S. Oliveira and\n                  Rafael Schild Reusch and\n                  Henrique Martins Medina and\n                  Fernando Moraes},\n  title        = {Evaluating the cost to cipher the NoC communication},\n  booktitle    = {9th {IEEE} Latin American Symposium on Circuits {\\&} Systems, {LASCAS}\n                  2018, Puerto Vallarta, Mexico, February 25-28, 2018},\n  pages        = {1--4},\n  publisher    = {{IEEE}},\n  year         = {2018},\n  url          = {https://doi.org/10.1109/LASCAS.2018.8399914},\n  doi          = {10.1109/LASCAS.2018.8399914},\n  timestamp    = {Fri, 09 Dec 2022 00:00:00 +0100},\n  biburl       = {https://dblp.org/rec/conf/lascas/OliveiraRMM18.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Fault-Tolerance at the Management Level in Many-Core Systems.\n \n \n \n \n\n\n \n Fochi, V.; Caimi, L. L.; da Silva, M. H.; and Moraes, F. G.\n\n\n \n\n\n\n In 31st Symposium on Integrated Circuits and Systems Design, SBCCI 2018, Bento Gonçalves, RS, Brazil, August 27-31, 2018, pages 1–6, 2018. IEEE\n \n\n\n\n
\n\n\n\n \n \n \"Fault-TolerancePaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/sbcci/FochiCSM18,\n  author       = {Vinicius Fochi and\n                  Luciano L. Caimi and\n                  Marcelo H. da Silva and\n                  Fernando Gehm Moraes},\n  title        = {Fault-Tolerance at the Management Level in Many-Core Systems},\n  booktitle    = {31st Symposium on Integrated Circuits and Systems Design, {SBCCI}\n                  2018, Bento Gon{\\c{c}}alves, RS, Brazil, August 27-31, 2018},\n  pages        = {1--6},\n  publisher    = {{IEEE}},\n  year         = {2018},\n  url          = {https://doi.org/10.1109/SBCCI.2018.8533249},\n  doi          = {10.1109/SBCCI.2018.8533249},\n  timestamp    = {Sun, 02 Oct 2022 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/conf/sbcci/FochiCSM18.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Secure Environment Architecture for MPSoCs.\n \n \n \n \n\n\n \n Oliveira, B. S.; Medina, H. M.; Sant'Ana, A. C.; and Moraes, F. G.\n\n\n \n\n\n\n In 31st Symposium on Integrated Circuits and Systems Design, SBCCI 2018, Bento Gonçalves, RS, Brazil, August 27-31, 2018, pages 1–6, 2018. IEEE\n \n\n\n\n
\n\n\n\n \n \n \"SecurePaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/sbcci/OliveiraMSM18,\n  author       = {Bruno Scherer Oliveira and\n                  Henrique Martins Medina and\n                  Anderson C. Sant'Ana and\n                  Fernando Gehm Moraes},\n  title        = {Secure Environment Architecture for MPSoCs},\n  booktitle    = {31st Symposium on Integrated Circuits and Systems Design, {SBCCI}\n                  2018, Bento Gon{\\c{c}}alves, RS, Brazil, August 27-31, 2018},\n  pages        = {1--6},\n  publisher    = {{IEEE}},\n  year         = {2018},\n  url          = {https://doi.org/10.1109/SBCCI.2018.8533238},\n  doi          = {10.1109/SBCCI.2018.8533238},\n  timestamp    = {Sun, 02 Oct 2022 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/conf/sbcci/OliveiraMSM18.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Exploring Asynchronous End-to-End Communication Through a Synchronous NoC.\n \n \n \n \n\n\n \n Weber, I. I.; Moraes, F. G.; de Oliveira, L. L.; and Carara, E. A.\n\n\n \n\n\n\n In 31st Symposium on Integrated Circuits and Systems Design, SBCCI 2018, Bento Gonçalves, RS, Brazil, August 27-31, 2018, pages 1–6, 2018. IEEE\n \n\n\n\n
\n\n\n\n \n \n \"ExploringPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/sbcci/WeberMOC18,\n  author       = {Ia{\\c{c}}an{\\~{a}} I. Weber and\n                  Fernando Gehm Moraes and\n                  Leonardo L. de Oliveira and\n                  Everton Alceu Carara},\n  title        = {Exploring Asynchronous End-to-End Communication Through a Synchronous\n                  NoC},\n  booktitle    = {31st Symposium on Integrated Circuits and Systems Design, {SBCCI}\n                  2018, Bento Gon{\\c{c}}alves, RS, Brazil, August 27-31, 2018},\n  pages        = {1--6},\n  publisher    = {{IEEE}},\n  year         = {2018},\n  url          = {https://doi.org/10.1109/SBCCI.2018.8533228},\n  doi          = {10.1109/SBCCI.2018.8533228},\n  timestamp    = {Sun, 02 Oct 2022 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/conf/sbcci/WeberMOC18.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n  \n 2017\n \n \n (12)\n \n \n
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\n \n\n \n \n \n \n \n \n Exploiting performance, dynamic power and energy scaling in full-system simulators.\n \n \n \n \n\n\n \n Duenha, L. D.; Madalozzo, G. A.; Moraes, F. G.; and Azevedo, R.\n\n\n \n\n\n\n Concurr. Comput. Pract. Exp., 29(22). 2017.\n \n\n\n\n
\n\n\n\n \n \n \"ExploitingPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@article{DBLP:journals/concurrency/DuenhaMMA17,\n  author       = {Liana Dessandre Duenha and\n                  Guilherme A. Madalozzo and\n                  Fernando Gehm Moraes and\n                  Rodolfo Azevedo},\n  title        = {Exploiting performance, dynamic power and energy scaling in full-system\n                  simulators},\n  journal      = {Concurr. Comput. Pract. Exp.},\n  volume       = {29},\n  number       = {22},\n  year         = {2017},\n  url          = {https://doi.org/10.1002/cpe.4034},\n  doi          = {10.1002/CPE.4034},\n  timestamp    = {Thu, 27 Jul 2023 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/journals/concurrency/DuenhaMMA17.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Distributed Runtime Energy Management for Many-Core Systems Running Real-Time Applications.\n \n \n \n \n\n\n \n Martins, A. L. M.; Ruaro, M.; Sant'Ana, A. C.; and Moraes, F. G.\n\n\n \n\n\n\n J. Low Power Electron., 13(3): 402–418. 2017.\n \n\n\n\n
\n\n\n\n \n \n \"DistributedPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@article{DBLP:journals/jolpe/MartinsRSM17,\n  author       = {Andre L. M. Martins and\n                  Marcelo Ruaro and\n                  Anderson C. Sant'Ana and\n                  Fernando Gehm Moraes},\n  title        = {Distributed Runtime Energy Management for Many-Core Systems Running\n                  Real-Time Applications},\n  journal      = {J. Low Power Electron.},\n  volume       = {13},\n  number       = {3},\n  pages        = {402--418},\n  year         = {2017},\n  url          = {https://doi.org/10.1166/jolpe.2017.1502},\n  doi          = {10.1166/JOLPE.2017.1502},\n  timestamp    = {Sun, 02 Oct 2022 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/journals/jolpe/MartinsRSM17.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n BrNoC: A broadcast NoC for control messages in many-core systems.\n \n \n \n \n\n\n \n Wächter, E.; Caimi, L. L.; Fochi, V.; Munhoz, D.; and Moraes, F. G.\n\n\n \n\n\n\n Microelectron. J., 68: 69–77. 2017.\n \n\n\n\n
\n\n\n\n \n \n \"BrNoC:Paper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@article{DBLP:journals/mj/WachterCFMM17,\n  author       = {Eduardo W{\\"{a}}chter and\n                  Luciano L. Caimi and\n                  Vinicius Fochi and\n                  Daniel Munhoz and\n                  Fernando Gehm Moraes},\n  title        = {BrNoC: {A} broadcast NoC for control messages in many-core systems},\n  journal      = {Microelectron. J.},\n  volume       = {68},\n  pages        = {69--77},\n  year         = {2017},\n  url          = {https://doi.org/10.1016/j.mejo.2017.08.010},\n  doi          = {10.1016/J.MEJO.2017.08.010},\n  timestamp    = {Sun, 02 Oct 2022 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/journals/mj/WachterCFMM17.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n XGT4: An industrial grade, open source tester for multi-gigabit networks.\n \n \n \n \n\n\n \n Juracy, L. R.; Lazzarotto, F. B.; Pigatto, D. V.; Calazans, N. L. V.; and Moraes, F. G.\n\n\n \n\n\n\n In 24th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2017, Batumi, Georgia, December 5-8, 2017, pages 252–255, 2017. IEEE\n \n\n\n\n
\n\n\n\n \n \n \"XGT4:Paper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/icecsys/JuracyLPCM17,\n  author       = {Leonardo Rezende Juracy and\n                  Felipe B. Lazzarotto and\n                  Daniel V. Pigatto and\n                  Ney Laert Vilar Calazans and\n                  Fernando Gehm Moraes},\n  title        = {{XGT4:} An industrial grade, open source tester for multi-gigabit\n                  networks},\n  booktitle    = {24th {IEEE} International Conference on Electronics, Circuits and\n                  Systems, {ICECS} 2017, Batumi, Georgia, December 5-8, 2017},\n  pages        = {252--255},\n  publisher    = {{IEEE}},\n  year         = {2017},\n  url          = {https://doi.org/10.1109/ICECS.2017.8292042},\n  doi          = {10.1109/ICECS.2017.8292042},\n  timestamp    = {Sun, 02 Oct 2022 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/conf/icecsys/JuracyLPCM17.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Activation of secure zones in many-core systems with dynamic rerouting.\n \n \n \n \n\n\n \n Caimi, L. L.; Fochi, V.; Wächter, E.; Munhoz, D.; and Moraes, F. G.\n\n\n \n\n\n\n In IEEE International Symposium on Circuits and Systems, ISCAS 2017, Baltimore, MD, USA, May 28-31, 2017, pages 1–4, 2017. IEEE\n \n\n\n\n
\n\n\n\n \n \n \"ActivationPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/iscas/CaimiFWMM17,\n  author       = {Luciano L. Caimi and\n                  Vinicius Fochi and\n                  Eduardo W{\\"{a}}chter and\n                  Daniel Munhoz and\n                  Fernando Gehm Moraes},\n  title        = {Activation of secure zones in many-core systems with dynamic rerouting},\n  booktitle    = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2017,\n                  Baltimore, MD, USA, May 28-31, 2017},\n  pages        = {1--4},\n  publisher    = {{IEEE}},\n  year         = {2017},\n  url          = {https://doi.org/10.1109/ISCAS.2017.8050256},\n  doi          = {10.1109/ISCAS.2017.8050256},\n  timestamp    = {Sun, 02 Oct 2022 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/conf/iscas/CaimiFWMM17.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Runtime energy management under real-time constraints in MPSoCs.\n \n \n \n \n\n\n \n Martins, A. L. M.; Ruaro, M.; Sant'Ana, A. C.; and Moraes, F. G.\n\n\n \n\n\n\n In IEEE International Symposium on Circuits and Systems, ISCAS 2017, Baltimore, MD, USA, May 28-31, 2017, pages 1–4, 2017. IEEE\n \n\n\n\n
\n\n\n\n \n \n \"RuntimePaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/iscas/MartinsRSM17,\n  author       = {Andre L. M. Martins and\n                  Marcelo Ruaro and\n                  Anderson C. Sant'Ana and\n                  Fernando Gehm Moraes},\n  title        = {Runtime energy management under real-time constraints in MPSoCs},\n  booktitle    = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2017,\n                  Baltimore, MD, USA, May 28-31, 2017},\n  pages        = {1--4},\n  publisher    = {{IEEE}},\n  year         = {2017},\n  url          = {https://doi.org/10.1109/ISCAS.2017.8050947},\n  doi          = {10.1109/ISCAS.2017.8050947},\n  timestamp    = {Sun, 02 Oct 2022 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/conf/iscas/MartinsRSM17.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Demystifying the cost of task migration in distributed memory many-core systems.\n \n \n \n \n\n\n \n Ruaro, M.; and Moraes, F. G.\n\n\n \n\n\n\n In IEEE International Symposium on Circuits and Systems, ISCAS 2017, Baltimore, MD, USA, May 28-31, 2017, pages 1–4, 2017. IEEE\n \n\n\n\n
\n\n\n\n \n \n \"DemystifyingPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/iscas/RuaroM17,\n  author       = {Marcelo Ruaro and\n                  Fernando Gehm Moraes},\n  title        = {Demystifying the cost of task migration in distributed memory many-core\n                  systems},\n  booktitle    = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2017,\n                  Baltimore, MD, USA, May 28-31, 2017},\n  pages        = {1--4},\n  publisher    = {{IEEE}},\n  year         = {2017},\n  url          = {https://doi.org/10.1109/ISCAS.2017.8050257},\n  doi          = {10.1109/ISCAS.2017.8050257},\n  timestamp    = {Sun, 02 Oct 2022 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/conf/iscas/RuaroM17.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n SDN-Based Circuit-Switching for Many-Cores.\n \n \n \n \n\n\n \n Ruaro, M.; Medina, H. M.; and Moraes, F. G.\n\n\n \n\n\n\n In 2017 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2017, Bochum, Germany, July 3-5, 2017, pages 385–390, 2017. IEEE Computer Society\n \n\n\n\n
\n\n\n\n \n \n \"SDN-BasedPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/isvlsi/RuaroMM17,\n  author       = {Marcelo Ruaro and\n                  Henrique Martins Medina and\n                  Fernando Gehm Moraes},\n  title        = {SDN-Based Circuit-Switching for Many-Cores},\n  booktitle    = {2017 {IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2017,\n                  Bochum, Germany, July 3-5, 2017},\n  pages        = {385--390},\n  publisher    = {{IEEE} Computer Society},\n  year         = {2017},\n  url          = {https://doi.org/10.1109/ISVLSI.2017.74},\n  doi          = {10.1109/ISVLSI.2017.74},\n  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},\n  biburl       = {https://dblp.org/rec/conf/isvlsi/RuaroMM17.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Secure admission and execution of applications in many-core systems.\n \n \n \n \n\n\n \n Caimi, L. L.; Fochi, V.; Wächter, E.; Munhoz, D.; and Moraes, F. G.\n\n\n \n\n\n\n In Silveira, J. A. N., editor(s), Proceedings of the 30th Symposium on Integrated Circuits and Systems Design: Chip on the Sands, SBCCI 2017, Fortaleza, Ceará, Brazil, August 28 - September 01, 2017, pages 65–71, 2017. ACM\n \n\n\n\n
\n\n\n\n \n \n \"SecurePaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/sbcci/CaimiFWMM17,\n  author       = {Luciano L. Caimi and\n                  Vinicius Fochi and\n                  Eduardo W{\\"{a}}chter and\n                  Daniel Munhoz and\n                  Fernando Gehm Moraes},\n  editor       = {Jarbas A. N. Silveira},\n  title        = {Secure admission and execution of applications in many-core systems},\n  booktitle    = {Proceedings of the 30th Symposium on Integrated Circuits and Systems\n                  Design: Chip on the Sands, {SBCCI} 2017, Fortaleza, Cear{\\'{a}}, Brazil,\n                  August 28 - September 01, 2017},\n  pages        = {65--71},\n  publisher    = {{ACM}},\n  year         = {2017},\n  url          = {https://doi.org/10.1145/3109984.3110015},\n  doi          = {10.1145/3109984.3110015},\n  timestamp    = {Sun, 02 Oct 2022 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/conf/sbcci/CaimiFWMM17.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Hardware and software infrastructure to implement many-core systems in modern FPGAs.\n \n \n \n \n\n\n \n Bortolon, F. T.; and Moraes, F. G.\n\n\n \n\n\n\n In Silveira, J. A. N., editor(s), Proceedings of the 30th Symposium on Integrated Circuits and Systems Design: Chip on the Sands, SBCCI 2017, Fortaleza, Ceará, Brazil, August 28 - September 01, 2017, pages 79–83, 2017. ACM\n \n\n\n\n
\n\n\n\n \n \n \"HardwarePaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/sbcci/BortolonM17,\n  author       = {Felipe T. Bortolon and\n                  Fernando Gehm Moraes},\n  editor       = {Jarbas A. N. Silveira},\n  title        = {Hardware and software infrastructure to implement many-core systems\n                  in modern FPGAs},\n  booktitle    = {Proceedings of the 30th Symposium on Integrated Circuits and Systems\n                  Design: Chip on the Sands, {SBCCI} 2017, Fortaleza, Cear{\\'{a}}, Brazil,\n                  August 28 - September 01, 2017},\n  pages        = {79--83},\n  publisher    = {{ACM}},\n  year         = {2017},\n  url          = {https://doi.org/10.1145/3109984.3109997},\n  doi          = {10.1145/3109984.3109997},\n  timestamp    = {Sun, 02 Oct 2022 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/conf/sbcci/BortolonM17.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Estimation methods for static noise margins in CMOS subthreshold logic circuits.\n \n \n \n \n\n\n \n Bortolon, F. T.; Moraes, F. G.; Moreira, M. T.; and Bampi, S.\n\n\n \n\n\n\n In Silveira, J. A. N., editor(s), Proceedings of the 30th Symposium on Integrated Circuits and Systems Design: Chip on the Sands, SBCCI 2017, Fortaleza, Ceará, Brazil, August 28 - September 01, 2017, pages 90–95, 2017. ACM\n \n\n\n\n
\n\n\n\n \n \n \"EstimationPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/sbcci/BortolonMMB17,\n  author       = {Felipe T. Bortolon and\n                  Fernando Gehm Moraes and\n                  Matheus T. Moreira and\n                  Sergio Bampi},\n  editor       = {Jarbas A. N. Silveira},\n  title        = {Estimation methods for static noise margins in {CMOS} subthreshold\n                  logic circuits},\n  booktitle    = {Proceedings of the 30th Symposium on Integrated Circuits and Systems\n                  Design: Chip on the Sands, {SBCCI} 2017, Fortaleza, Cear{\\'{a}}, Brazil,\n                  August 28 - September 01, 2017},\n  pages        = {90--95},\n  publisher    = {{ACM}},\n  year         = {2017},\n  url          = {https://doi.org/10.1145/3109984.3109998},\n  doi          = {10.1145/3109984.3109998},\n  timestamp    = {Sun, 02 Oct 2022 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/conf/sbcci/BortolonMMB17.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n System management recovery protocol for MPSoCs.\n \n \n \n \n\n\n \n Fochi, V.; Caimi, L. L.; Ruaro, M.; Wächter, E.; and Moraes, F. G.\n\n\n \n\n\n\n In Alioto, M.; Li, H. H.; Becker, J.; Schlichtmann, U.; and Sridhar, R., editor(s), 30th IEEE International System-on-Chip Conference, SOCC 2017, Munich, Germany, September 5-8, 2017, pages 367–374, 2017. IEEE\n \n\n\n\n
\n\n\n\n \n \n \"SystemPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/socc/FochiCRWM17,\n  author       = {Vinicius Fochi and\n                  Luciano L. Caimi and\n                  Marcelo Ruaro and\n                  Eduardo W{\\"{a}}chter and\n                  Fernando Gehm Moraes},\n  editor       = {Massimo Alioto and\n                  Hai Helen Li and\n                  J{\\"{u}}rgen Becker and\n                  Ulf Schlichtmann and\n                  Ramalingam Sridhar},\n  title        = {System management recovery protocol for MPSoCs},\n  booktitle    = {30th {IEEE} International System-on-Chip Conference, {SOCC} 2017,\n                  Munich, Germany, September 5-8, 2017},\n  pages        = {367--374},\n  publisher    = {{IEEE}},\n  year         = {2017},\n  url          = {https://doi.org/10.1109/SOCC.2017.8226080},\n  doi          = {10.1109/SOCC.2017.8226080},\n  timestamp    = {Sun, 02 Oct 2022 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/conf/socc/FochiCRWM17.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n  \n 2016\n \n \n (12)\n \n \n
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\n \n\n \n \n \n \n \n \n MPSoCBench: A benchmark for high-level evaluation of multiprocessor system-on-chip tools and methodologies.\n \n \n \n \n\n\n \n Duenha, L. D.; Madalozzo, G. A.; Santiago, T.; Moraes, F.; and Azevedo, R.\n\n\n \n\n\n\n J. Parallel Distributed Comput., 95: 138–157. 2016.\n \n\n\n\n
\n\n\n\n \n \n \"MPSoCBench:Paper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@article{DBLP:journals/jpdc/DuenhaMSMA16,\n  author       = {Liana Dessandre Duenha and\n                  Guilherme A. Madalozzo and\n                  Thiago Santiago and\n                  Fernando Moraes and\n                  Rodolfo Azevedo},\n  title        = {MPSoCBench: {A} benchmark for high-level evaluation of multiprocessor\n                  system-on-chip tools and methodologies},\n  journal      = {J. Parallel Distributed Comput.},\n  volume       = {95},\n  pages        = {138--157},\n  year         = {2016},\n  url          = {https://doi.org/10.1016/j.jpdc.2016.03.009},\n  doi          = {10.1016/J.JPDC.2016.03.009},\n  timestamp    = {Thu, 27 Jul 2023 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/journals/jpdc/DuenhaMSMA16.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Hierarchical energy monitoring for task mapping in many-core systems.\n \n \n \n \n\n\n \n Castilhos, G. M.; Mandelli, M.; Ost, L.; and Moraes, F. G.\n\n\n \n\n\n\n J. Syst. Archit., 63: 80–92. 2016.\n \n\n\n\n
\n\n\n\n \n \n \"HierarchicalPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@article{DBLP:journals/jsa/CastilhosMOM16,\n  author       = {Guilherme M. Castilhos and\n                  Marcelo Mandelli and\n                  Luciano Ost and\n                  Fernando Gehm Moraes},\n  title        = {Hierarchical energy monitoring for task mapping in many-core systems},\n  journal      = {J. Syst. Archit.},\n  volume       = {63},\n  pages        = {80--92},\n  year         = {2016},\n  url          = {https://doi.org/10.1016/j.sysarc.2016.01.005},\n  doi          = {10.1016/J.SYSARC.2016.01.005},\n  timestamp    = {Mon, 03 Jan 2022 00:00:00 +0100},\n  biburl       = {https://dblp.org/rec/journals/jsa/CastilhosMOM16.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Dynamic Real-Time Scheduler for Large-Scale MPSoCs.\n \n \n \n \n\n\n \n Ruaro, M.; and Moraes, F. G.\n\n\n \n\n\n\n In Coskun, A. K.; Margala, M.; Behjat, L.; and Han, J., editor(s), Proceedings of the 26th edition on Great Lakes Symposium on VLSI, GLVLSI 2016, Boston, MA, USA, May 18-20, 2016, pages 341–346, 2016. ACM\n \n\n\n\n
\n\n\n\n \n \n \"DynamicPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/glvlsi/RuaroM16,\n  author       = {Marcelo Ruaro and\n                  Fernando Gehm Moraes},\n  editor       = {Ayse K. Coskun and\n                  Martin Margala and\n                  Laleh Behjat and\n                  Jie Han},\n  title        = {Dynamic Real-Time Scheduler for Large-Scale MPSoCs},\n  booktitle    = {Proceedings of the 26th edition on Great Lakes Symposium on VLSI,\n                  {GLVLSI} 2016, Boston, MA, USA, May 18-20, 2016},\n  pages        = {341--346},\n  publisher    = {{ACM}},\n  year         = {2016},\n  url          = {https://doi.org/10.1145/2902961.2903027},\n  doi          = {10.1145/2902961.2903027},\n  timestamp    = {Wed, 10 Mar 2021 14:55:38 +0100},\n  biburl       = {https://dblp.org/rec/conf/glvlsi/RuaroM16.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Runtime energy management for many-core systems.\n \n \n \n \n\n\n \n Martins, A. L. M.; Sant'Ana, A. C.; and Moraes, F. G.\n\n\n \n\n\n\n In 2016 IEEE International Conference on Electronics, Circuits and Systems, ICECS 2016, Monte Carlo, Monaco, December 11-14, 2016, pages 380–383, 2016. IEEE\n \n\n\n\n
\n\n\n\n \n \n \"RuntimePaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/icecsys/MartinsSM16,\n  author       = {Andre L. M. Martins and\n                  Anderson C. Sant'Ana and\n                  Fernando Gehm Moraes},\n  title        = {Runtime energy management for many-core systems},\n  booktitle    = {2016 {IEEE} International Conference on Electronics, Circuits and\n                  Systems, {ICECS} 2016, Monte Carlo, Monaco, December 11-14, 2016},\n  pages        = {380--383},\n  publisher    = {{IEEE}},\n  year         = {2016},\n  url          = {https://doi.org/10.1109/ICECS.2016.7841212},\n  doi          = {10.1109/ICECS.2016.7841212},\n  timestamp    = {Wed, 16 Oct 2019 14:14:55 +0200},\n  biburl       = {https://dblp.org/rec/conf/icecsys/MartinsSM16.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Scalability evaluation in many-core systems due to the memory organization.\n \n \n \n \n\n\n \n Madalozzo, G. A.; Duenha, L. D.; Azevedo, R.; and Moraes, F. G.\n\n\n \n\n\n\n In 2016 IEEE International Conference on Electronics, Circuits and Systems, ICECS 2016, Monte Carlo, Monaco, December 11-14, 2016, pages 396–399, 2016. IEEE\n \n\n\n\n
\n\n\n\n \n \n \"ScalabilityPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/icecsys/MadalozzoDAM16,\n  author       = {Guilherme A. Madalozzo and\n                  Liana Dessandre Duenha and\n                  Rodolfo Azevedo and\n                  Fernando Gehm Moraes},\n  title        = {Scalability evaluation in many-core systems due to the memory organization},\n  booktitle    = {2016 {IEEE} International Conference on Electronics, Circuits and\n                  Systems, {ICECS} 2016, Monte Carlo, Monaco, December 11-14, 2016},\n  pages        = {396--399},\n  publisher    = {{IEEE}},\n  year         = {2016},\n  url          = {https://doi.org/10.1109/ICECS.2016.7841216},\n  doi          = {10.1109/ICECS.2016.7841216},\n  timestamp    = {Thu, 27 Jul 2023 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/conf/icecsys/MadalozzoDAM16.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n A data extraction and debugging framework for large-scale MPSoCs.\n \n \n \n \n\n\n \n Ruaro, M.; Chamorra, H.; Rubin, F.; Amory, A. M.; and Moraes, F. G.\n\n\n \n\n\n\n In 2016 IEEE International Conference on Electronics, Circuits and Systems, ICECS 2016, Monte Carlo, Monaco, December 11-14, 2016, pages 616–619, 2016. IEEE\n \n\n\n\n
\n\n\n\n \n \n \"APaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/icecsys/RuaroCRAM16,\n  author       = {Marcelo Ruaro and\n                  Henrique Chamorra and\n                  Felipe Rubin and\n                  Alexandre M. Amory and\n                  Fernando Gehm Moraes},\n  title        = {A data extraction and debugging framework for large-scale MPSoCs},\n  booktitle    = {2016 {IEEE} International Conference on Electronics, Circuits and\n                  Systems, {ICECS} 2016, Monte Carlo, Monaco, December 11-14, 2016},\n  pages        = {616--619},\n  publisher    = {{IEEE}},\n  year         = {2016},\n  url          = {https://doi.org/10.1109/ICECS.2016.7841277},\n  doi          = {10.1109/ICECS.2016.7841277},\n  timestamp    = {Sun, 25 Oct 2020 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/conf/icecsys/RuaroCRAM16.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Mapping of real-time applications on a packet switching NoC-based MPSoC.\n \n \n \n \n\n\n \n Madalozzo, G. A.; Indrusiak, L. S.; and Moraes, F. G.\n\n\n \n\n\n\n In 2016 IEEE International Conference on Electronics, Circuits and Systems, ICECS 2016, Monte Carlo, Monaco, December 11-14, 2016, pages 640–643, 2016. IEEE\n \n\n\n\n
\n\n\n\n \n \n \"MappingPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/icecsys/MadalozzoIM16,\n  author       = {Guilherme A. Madalozzo and\n                  Leandro Soares Indrusiak and\n                  Fernando Gehm Moraes},\n  title        = {Mapping of real-time applications on a packet switching NoC-based\n                  MPSoC},\n  booktitle    = {2016 {IEEE} International Conference on Electronics, Circuits and\n                  Systems, {ICECS} 2016, Monte Carlo, Monaco, December 11-14, 2016},\n  pages        = {640--643},\n  publisher    = {{IEEE}},\n  year         = {2016},\n  url          = {https://doi.org/10.1109/ICECS.2016.7841283},\n  doi          = {10.1109/ICECS.2016.7841283},\n  timestamp    = {Sun, 02 Jun 2019 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/conf/icecsys/MadalozzoIM16.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Extending FreeRTOS to support dynamic and distributed mapping in multiprocessor systems.\n \n \n \n \n\n\n \n Abich, G.; Mandelli, M. G.; Rosa, F. R.; Moraes, F. G.; Ost, L.; and Reis, R.\n\n\n \n\n\n\n In 2016 IEEE International Conference on Electronics, Circuits and Systems, ICECS 2016, Monte Carlo, Monaco, December 11-14, 2016, pages 712–715, 2016. IEEE\n \n\n\n\n
\n\n\n\n \n \n \"ExtendingPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/icecsys/AbichMRMOR16,\n  author       = {Geancarlo Abich and\n                  Marcelo G. Mandelli and\n                  Felipe R. Rosa and\n                  Fernando Gehm Moraes and\n                  Luciano Ost and\n                  Ricardo Reis},\n  title        = {Extending FreeRTOS to support dynamic and distributed mapping in multiprocessor\n                  systems},\n  booktitle    = {2016 {IEEE} International Conference on Electronics, Circuits and\n                  Systems, {ICECS} 2016, Monte Carlo, Monaco, December 11-14, 2016},\n  pages        = {712--715},\n  publisher    = {{IEEE}},\n  year         = {2016},\n  url          = {https://doi.org/10.1109/ICECS.2016.7841301},\n  doi          = {10.1109/ICECS.2016.7841301},\n  timestamp    = {Sat, 30 Sep 2023 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/conf/icecsys/AbichMRMOR16.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n DMNI: A specialized network interface for NoC-based MPSoCs.\n \n \n \n \n\n\n \n Ruaro, M.; Lazzarotto, F. B.; Marcon, C. A. M.; and Moraes, F. G.\n\n\n \n\n\n\n In IEEE International Symposium on Circuits and Systems, ISCAS 2016, Montréal, QC, Canada, May 22-25, 2016, pages 1202–1205, 2016. IEEE\n \n\n\n\n
\n\n\n\n \n \n \"DMNI:Paper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/iscas/RuaroLMM16,\n  author       = {Marcelo Ruaro and\n                  Felipe B. Lazzarotto and\n                  C{\\'{e}}sar A. M. Marcon and\n                  Fernando Gehm Moraes},\n  title        = {{DMNI:} {A} specialized network interface for NoC-based MPSoCs},\n  booktitle    = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2016,\n                  Montr{\\'{e}}al, QC, Canada, May 22-25, 2016},\n  pages        = {1202--1205},\n  publisher    = {{IEEE}},\n  year         = {2016},\n  url          = {https://doi.org/10.1109/ISCAS.2016.7527462},\n  doi          = {10.1109/ISCAS.2016.7527462},\n  timestamp    = {Thu, 14 Oct 2021 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/conf/iscas/RuaroLMM16.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Efficient traffic balancing for NoC routing latency minimization.\n \n \n \n \n\n\n \n Ferreira, J. M.; Silveira, J.; Silveira, J.; Cataldo, R.; Webber, T.; Moraes, F. G.; and Marcon, C. A. M.\n\n\n \n\n\n\n In IEEE International Symposium on Circuits and Systems, ISCAS 2016, Montréal, QC, Canada, May 22-25, 2016, pages 2599–2602, 2016. IEEE\n \n\n\n\n
\n\n\n\n \n \n \"EfficientPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/iscas/FerreiraSSCWMM16,\n  author       = {Joao Marcelo Ferreira and\n                  Jarbas Silveira and\n                  Jardel Silveira and\n                  Rodrigo Cataldo and\n                  Thais Webber and\n                  Fernando Gehm Moraes and\n                  C{\\'{e}}sar A. M. Marcon},\n  title        = {Efficient traffic balancing for NoC routing latency minimization},\n  booktitle    = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2016,\n                  Montr{\\'{e}}al, QC, Canada, May 22-25, 2016},\n  pages        = {2599--2602},\n  publisher    = {{IEEE}},\n  year         = {2016},\n  url          = {https://doi.org/10.1109/ISCAS.2016.7539125},\n  doi          = {10.1109/ISCAS.2016.7539125},\n  timestamp    = {Sat, 09 Apr 2022 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/conf/iscas/FerreiraSSCWMM16.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n A layered approach for fault tolerant NoC-based MPSoCs - Special session: Dependable MPSoCs.\n \n \n \n \n\n\n \n Wächter, E.; Barreto, F. F. S.; Fochi, V.; Amory, A. M.; and Moraes, F. G.\n\n\n \n\n\n\n In 17th Latin-American Test Symposium, LATS 2016, Foz do Iguacu, Brazil, April 6-8, 2016, pages 189–194, 2016. IEEE\n \n\n\n\n
\n\n\n\n \n \n \"APaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/latw/WachterBFAM16,\n  author       = {Eduardo W{\\"{a}}chter and\n                  Francisco F. S. Barreto and\n                  Vinicius Fochi and\n                  Alexandre M. Amory and\n                  Fernando Gehm Moraes},\n  title        = {A layered approach for fault tolerant NoC-based MPSoCs - Special session:\n                  Dependable MPSoCs},\n  booktitle    = {17th Latin-American Test Symposium, {LATS} 2016, Foz do Iguacu, Brazil,\n                  April 6-8, 2016},\n  pages        = {189--194},\n  publisher    = {{IEEE}},\n  year         = {2016},\n  url          = {https://doi.org/10.1109/LATW.2016.7483367},\n  doi          = {10.1109/LATW.2016.7483367},\n  timestamp    = {Wed, 16 Oct 2019 14:14:55 +0200},\n  biburl       = {https://dblp.org/rec/conf/latw/WachterBFAM16.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n A lightweight software-based runtime temperature monitoring model for multiprocessor embedded systems.\n \n \n \n \n\n\n \n Castilhos, G. M.; Moraes, F. G.; and Ost, L.\n\n\n \n\n\n\n In 29th Symposium on Integrated Circuits and Systems Design, SBCCI 2016, Belo Horizonte, Brazil, August 29 - September 3, 2016, pages 1–6, 2016. IEEE\n \n\n\n\n
\n\n\n\n \n \n \"APaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/sbcci/CastilhosMO16,\n  author       = {Guilherme M. Castilhos and\n                  Fernando Gehm Moraes and\n                  Luciano Ost},\n  title        = {A lightweight software-based runtime temperature monitoring model\n                  for multiprocessor embedded systems},\n  booktitle    = {29th Symposium on Integrated Circuits and Systems Design, {SBCCI}\n                  2016, Belo Horizonte, Brazil, August 29 - September 3, 2016},\n  pages        = {1--6},\n  publisher    = {{IEEE}},\n  year         = {2016},\n  url          = {https://doi.org/10.1109/SBCCI.2016.7724040},\n  doi          = {10.1109/SBCCI.2016.7724040},\n  timestamp    = {Mon, 03 Jan 2022 00:00:00 +0100},\n  biburl       = {https://dblp.org/rec/conf/sbcci/CastilhosMO16.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n  \n 2015\n \n \n (15)\n \n \n
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\n \n\n \n \n \n \n \n \n Static Differential NCL Gates: Toward Low Power.\n \n \n \n \n\n\n \n Moreira, M. T.; Arendt, M. E.; Moraes, F. G.; and Calazans, N. L. V.\n\n\n \n\n\n\n IEEE Trans. Circuits Syst. II Express Briefs, 62-II(6): 563–567. 2015.\n \n\n\n\n
\n\n\n\n \n \n \"StaticPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@article{DBLP:journals/tcas/MoreiraAMC15,\n  author       = {Matheus Trevisan Moreira and\n                  Michel Evandro Arendt and\n                  Fernando Gehm Moraes and\n                  Ney Laert Vilar Calazans},\n  title        = {Static Differential {NCL} Gates: Toward Low Power},\n  journal      = {{IEEE} Trans. Circuits Syst. {II} Express Briefs},\n  volume       = {62-II},\n  number       = {6},\n  pages        = {563--567},\n  year         = {2015},\n  url          = {https://doi.org/10.1109/TCSII.2015.2407198},\n  doi          = {10.1109/TCSII.2015.2407198},\n  timestamp    = {Sun, 02 Oct 2022 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/journals/tcas/MoreiraAMC15.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Runtime Adaptive Circuit Switching and Flow Priority in NoC-Based MPSoCs.\n \n \n \n \n\n\n \n Ruaro, M.; Carara, E. A.; and Moraes, F. G.\n\n\n \n\n\n\n IEEE Trans. Very Large Scale Integr. Syst., 23(6): 1077–1088. 2015.\n \n\n\n\n
\n\n\n\n \n \n \"RuntimePaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@article{DBLP:journals/tvlsi/RuaroCM15,\n  author       = {Marcelo Ruaro and\n                  Everton Alceu Carara and\n                  Fernando Gehm Moraes},\n  title        = {Runtime Adaptive Circuit Switching and Flow Priority in NoC-Based\n                  MPSoCs},\n  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},\n  volume       = {23},\n  number       = {6},\n  pages        = {1077--1088},\n  year         = {2015},\n  url          = {https://doi.org/10.1109/TVLSI.2014.2331135},\n  doi          = {10.1109/TVLSI.2014.2331135},\n  timestamp    = {Mon, 26 Oct 2020 00:00:00 +0100},\n  biburl       = {https://dblp.org/rec/journals/tvlsi/RuaroCM15.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n A hierarchical LST-based task scheduler for NoC-based MPSoCs with slack-time monitoring support.\n \n \n \n \n\n\n \n Ruaro, M.; Madalozzo, G. A.; and Moraes, F. G.\n\n\n \n\n\n\n In 2015 IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2015, Cairo, Egypt, December 6-9, 2015, pages 308–311, 2015. IEEE\n \n\n\n\n
\n\n\n\n \n \n \"APaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/icecsys/RuaroMM15,\n  author       = {Marcelo Ruaro and\n                  Guilherme A. Madalozzo and\n                  Fernando Gehm Moraes},\n  title        = {A hierarchical LST-based task scheduler for NoC-based MPSoCs with\n                  slack-time monitoring support},\n  booktitle    = {2015 {IEEE} International Conference on Electronics, Circuits, and\n                  Systems, {ICECS} 2015, Cairo, Egypt, December 6-9, 2015},\n  pages        = {308--311},\n  publisher    = {{IEEE}},\n  year         = {2015},\n  url          = {https://doi.org/10.1109/ICECS.2015.7440310},\n  doi          = {10.1109/ICECS.2015.7440310},\n  timestamp    = {Sun, 25 Oct 2020 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/conf/icecsys/RuaroMM15.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Differentiation of MPSoCs message classes using multiple NoCs.\n \n \n \n \n\n\n \n Silva, D. R. G.; and Moraes, F. G.\n\n\n \n\n\n\n In 2015 IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2015, Cairo, Egypt, December 6-9, 2015, pages 312–315, 2015. IEEE\n \n\n\n\n
\n\n\n\n \n \n \"DifferentiationPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/icecsys/SilvaM15,\n  author       = {Douglas R. G. Silva and\n                  Fernando Gehm Moraes},\n  title        = {Differentiation of MPSoCs message classes using multiple NoCs},\n  booktitle    = {2015 {IEEE} International Conference on Electronics, Circuits, and\n                  Systems, {ICECS} 2015, Cairo, Egypt, December 6-9, 2015},\n  pages        = {312--315},\n  publisher    = {{IEEE}},\n  year         = {2015},\n  url          = {https://doi.org/10.1109/ICECS.2015.7440311},\n  doi          = {10.1109/ICECS.2015.7440311},\n  timestamp    = {Sun, 02 Jun 2019 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/conf/icecsys/SilvaM15.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n A non-intrusive and reconfigurable access control to secure NoCs.\n \n \n \n \n\n\n \n Fernandes, R.; Oliveira, B. S.; Sepúlveda, J.; Marcon, C. A. M.; and Moraes, F. G.\n\n\n \n\n\n\n In 2015 IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2015, Cairo, Egypt, December 6-9, 2015, pages 316–319, 2015. IEEE\n \n\n\n\n
\n\n\n\n \n \n \"APaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/icecsys/FernandesOSMM15,\n  author       = {Ramon Fernandes and\n                  Bruno S. Oliveira and\n                  Johanna Sep{\\'{u}}lveda and\n                  C{\\'{e}}sar A. M. Marcon and\n                  Fernando Gehm Moraes},\n  title        = {A non-intrusive and reconfigurable access control to secure NoCs},\n  booktitle    = {2015 {IEEE} International Conference on Electronics, Circuits, and\n                  Systems, {ICECS} 2015, Cairo, Egypt, December 6-9, 2015},\n  pages        = {316--319},\n  publisher    = {{IEEE}},\n  year         = {2015},\n  url          = {https://doi.org/10.1109/ICECS.2015.7440312},\n  doi          = {10.1109/ICECS.2015.7440312},\n  timestamp    = {Thu, 14 Oct 2021 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/conf/icecsys/FernandesOSMM15.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n A platform-based design framework to boost many-core software development.\n \n \n \n \n\n\n \n Madalozzo, G. A.; Mandelli, M.; Ost, L.; and Moraes, F. G.\n\n\n \n\n\n\n In 2015 IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2015, Cairo, Egypt, December 6-9, 2015, pages 320–323, 2015. IEEE\n \n\n\n\n
\n\n\n\n \n \n \"APaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/icecsys/MadalozzoMOM15,\n  author       = {Guilherme A. Madalozzo and\n                  Marcelo Mandelli and\n                  Luciano Ost and\n                  Fernando Gehm Moraes},\n  title        = {A platform-based design framework to boost many-core software development},\n  booktitle    = {2015 {IEEE} International Conference on Electronics, Circuits, and\n                  Systems, {ICECS} 2015, Cairo, Egypt, December 6-9, 2015},\n  pages        = {320--323},\n  publisher    = {{IEEE}},\n  year         = {2015},\n  url          = {https://doi.org/10.1109/ICECS.2015.7440313},\n  doi          = {10.1109/ICECS.2015.7440313},\n  timestamp    = {Mon, 03 Jan 2022 00:00:00 +0100},\n  biburl       = {https://dblp.org/rec/conf/icecsys/MadalozzoMOM15.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Hierarchical energy monitoring for many-core systems.\n \n \n \n \n\n\n \n Martins, A. L. M.; Ruaro, M.; and Moraes, F. G.\n\n\n \n\n\n\n In 2015 IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2015, Cairo, Egypt, December 6-9, 2015, pages 657–660, 2015. IEEE\n \n\n\n\n
\n\n\n\n \n \n \"HierarchicalPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/icecsys/MartinsRM15,\n  author       = {Andre L. M. Martins and\n                  Marcelo Ruaro and\n                  Fernando Gehm Moraes},\n  title        = {Hierarchical energy monitoring for many-core systems},\n  booktitle    = {2015 {IEEE} International Conference on Electronics, Circuits, and\n                  Systems, {ICECS} 2015, Cairo, Egypt, December 6-9, 2015},\n  pages        = {657--660},\n  publisher    = {{IEEE}},\n  year         = {2015},\n  url          = {https://doi.org/10.1109/ICECS.2015.7440402},\n  doi          = {10.1109/ICECS.2015.7440402},\n  timestamp    = {Sun, 25 Oct 2020 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/conf/icecsys/MartinsRM15.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Fault recovery protocol for distributed memory MPSoCs.\n \n \n \n \n\n\n \n Barreto, F. F. S.; Amory, A. M.; and Moraes, F. G.\n\n\n \n\n\n\n In 2015 IEEE International Symposium on Circuits and Systems, ISCAS 2015, Lisbon, Portugal, May 24-27, 2015, pages 421–424, 2015. IEEE\n \n\n\n\n
\n\n\n\n \n \n \"FaultPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/iscas/BarretoAM15,\n  author       = {Francisco F. S. Barreto and\n                  Alexandre M. Amory and\n                  Fernando Gehm Moraes},\n  title        = {Fault recovery protocol for distributed memory MPSoCs},\n  booktitle    = {2015 {IEEE} International Symposium on Circuits and Systems, {ISCAS}\n                  2015, Lisbon, Portugal, May 24-27, 2015},\n  pages        = {421--424},\n  publisher    = {{IEEE}},\n  year         = {2015},\n  url          = {https://doi.org/10.1109/ISCAS.2015.7168660},\n  doi          = {10.1109/ISCAS.2015.7168660},\n  timestamp    = {Wed, 16 Oct 2019 14:14:49 +0200},\n  biburl       = {https://dblp.org/rec/conf/iscas/BarretoAM15.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n An integrated method for implementing online fault detection in NoC-based MPSoCs.\n \n \n \n \n\n\n \n Fochi, V.; Wächter, E.; Erichsen, A.; Amory, A. M.; and Moraes, F. G.\n\n\n \n\n\n\n In 2015 IEEE International Symposium on Circuits and Systems, ISCAS 2015, Lisbon, Portugal, May 24-27, 2015, pages 1562–1565, 2015. IEEE\n \n\n\n\n
\n\n\n\n \n \n \"AnPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/iscas/FochiWEAM15,\n  author       = {Vinicius Fochi and\n                  Eduardo W{\\"{a}}chter and\n                  Augusto Erichsen and\n                  Alexandre M. Amory and\n                  Fernando Gehm Moraes},\n  title        = {An integrated method for implementing online fault detection in NoC-based\n                  MPSoCs},\n  booktitle    = {2015 {IEEE} International Symposium on Circuits and Systems, {ISCAS}\n                  2015, Lisbon, Portugal, May 24-27, 2015},\n  pages        = {1562--1565},\n  publisher    = {{IEEE}},\n  year         = {2015},\n  url          = {https://doi.org/10.1109/ISCAS.2015.7168945},\n  doi          = {10.1109/ISCAS.2015.7168945},\n  timestamp    = {Wed, 25 Sep 2019 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/conf/iscas/FochiWEAM15.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n A context saving fault tolerant approach for a shared memory many-core architecture.\n \n \n \n \n\n\n \n Wächter, E.; Ventroux, N.; and Moraes, F. G.\n\n\n \n\n\n\n In 2015 IEEE International Symposium on Circuits and Systems, ISCAS 2015, Lisbon, Portugal, May 24-27, 2015, pages 1570–1573, 2015. IEEE\n \n\n\n\n
\n\n\n\n \n \n \"APaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/iscas/WachterVM15,\n  author       = {Eduardo W{\\"{a}}chter and\n                  Nicolas Ventroux and\n                  Fernando Gehm Moraes},\n  title        = {A context saving fault tolerant approach for a shared memory many-core\n                  architecture},\n  booktitle    = {2015 {IEEE} International Symposium on Circuits and Systems, {ISCAS}\n                  2015, Lisbon, Portugal, May 24-27, 2015},\n  pages        = {1570--1573},\n  publisher    = {{IEEE}},\n  year         = {2015},\n  url          = {https://doi.org/10.1109/ISCAS.2015.7168947},\n  doi          = {10.1109/ISCAS.2015.7168947},\n  timestamp    = {Sun, 02 Jun 2019 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/conf/iscas/WachterVM15.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Trading-off system load and communication in mapping heuristics for improving NoC-based MPSoCs reliability.\n \n \n \n \n\n\n \n Mandelli, M.; Ost, L.; Sassatelli, G.; and Moraes, F. G.\n\n\n \n\n\n\n In Sixteenth International Symposium on Quality Electronic Design, ISQED 2015, Santa Clara, CA, USA, March 2-4, 2015, pages 392–396, 2015. IEEE\n \n\n\n\n
\n\n\n\n \n \n \"Trading-offPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/isqed/MandelliOSM15,\n  author       = {Marcelo Mandelli and\n                  Luciano Ost and\n                  Gilles Sassatelli and\n                  Fernando Gehm Moraes},\n  title        = {Trading-off system load and communication in mapping heuristics for\n                  improving NoC-based MPSoCs reliability},\n  booktitle    = {Sixteenth International Symposium on Quality Electronic Design, {ISQED}\n                  2015, Santa Clara, CA, USA, March 2-4, 2015},\n  pages        = {392--396},\n  publisher    = {{IEEE}},\n  year         = {2015},\n  url          = {https://doi.org/10.1109/ISQED.2015.7085457},\n  doi          = {10.1109/ISQED.2015.7085457},\n  timestamp    = {Mon, 03 Jan 2022 00:00:00 +0100},\n  biburl       = {https://dblp.org/rec/conf/isqed/MandelliOSM15.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n BAT-Hermes: A transition-signaling bundled-data NoC router.\n \n \n \n \n\n\n \n Gibiluka, M.; Moreira, M. T.; Moraes, F. G.; and Calazans, N. L. V.\n\n\n \n\n\n\n In IEEE 6th Latin American Symposium on Circuits & Systems, LASCAS 2015, Montevideo, Uruguay, February 24-27, 2015, pages 1–4, 2015. IEEE\n \n\n\n\n
\n\n\n\n \n \n \"BAT-Hermes:Paper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/lascas/GibilukaMMC15,\n  author       = {Matheus Gibiluka and\n                  Matheus Trevisan Moreira and\n                  Fernando Gehm Moraes and\n                  Ney Laert Vilar Calazans},\n  title        = {BAT-Hermes: {A} transition-signaling bundled-data NoC router},\n  booktitle    = {{IEEE} 6th Latin American Symposium on Circuits {\\&} Systems, {LASCAS}\n                  2015, Montevideo, Uruguay, February 24-27, 2015},\n  pages        = {1--4},\n  publisher    = {{IEEE}},\n  year         = {2015},\n  url          = {https://doi.org/10.1109/LASCAS.2015.7250461},\n  doi          = {10.1109/LASCAS.2015.7250461},\n  timestamp    = {Sun, 02 Oct 2022 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/conf/lascas/GibilukaMMC15.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n A digitally controlled oscillator for fine-grained local clock generators in MPSoCs.\n \n \n \n \n\n\n \n Heck, G.; Heck, L. S.; Moreira, M. T.; Moraes, F. G.; and Calazans, N. L. V.\n\n\n \n\n\n\n In IEEE 6th Latin American Symposium on Circuits & Systems, LASCAS 2015, Montevideo, Uruguay, February 24-27, 2015, pages 1–4, 2015. IEEE\n \n\n\n\n
\n\n\n\n \n \n \"APaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/lascas/HeckHMMC15,\n  author       = {Guilherme Heck and\n                  Leandro S. Heck and\n                  Matheus T. Moreira and\n                  Fernando Gehm Moraes and\n                  Ney Laert Vilar Calazans},\n  title        = {A digitally controlled oscillator for fine-grained local clock generators\n                  in MPSoCs},\n  booktitle    = {{IEEE} 6th Latin American Symposium on Circuits {\\&} Systems, {LASCAS}\n                  2015, Montevideo, Uruguay, February 24-27, 2015},\n  pages        = {1--4},\n  publisher    = {{IEEE}},\n  year         = {2015},\n  url          = {https://doi.org/10.1109/LASCAS.2015.7250444},\n  doi          = {10.1109/LASCAS.2015.7250444},\n  timestamp    = {Sun, 02 Oct 2022 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/conf/lascas/HeckHMMC15.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n SDDS-NCL Design: Analysis of Supply Voltage Scaling.\n \n \n \n \n\n\n \n Guazzelli, R. A.; Moraes, F. G.; Calazans, N. L. V.; and Moreira, M. T.\n\n\n \n\n\n\n In de Lima, R. N.; Cunha, A. I. A.; Plett, C.; and de Oliveira, W. L. A., editor(s), Proceedings of the 28th Symposium on Integrated Circuits and Systems Design, SBCCI 2015, Salvador, Brazil, August 31 - September 4, 2015, pages 2:1–2:7, 2015. ACM\n \n\n\n\n
\n\n\n\n \n \n \"SDDS-NCLPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/sbcci/GuazzelliMCM15,\n  author       = {Ricardo A. Guazzelli and\n                  Fernando Gehm Moraes and\n                  Ney Laert Vilar Calazans and\n                  Matheus T. Moreira},\n  editor       = {Robson Nunes de Lima and\n                  Ana Isabela Ara{\\'{u}}jo Cunha and\n                  Calvin Plett and\n                  Wagner Luiz Alves de Oliveira},\n  title        = {{SDDS-NCL} Design: Analysis of Supply Voltage Scaling},\n  booktitle    = {Proceedings of the 28th Symposium on Integrated Circuits and Systems\n                  Design, {SBCCI} 2015, Salvador, Brazil, August 31 - September 4, 2015},\n  pages        = {2:1--2:7},\n  publisher    = {{ACM}},\n  year         = {2015},\n  url          = {https://doi.org/10.1145/2800986.2800999},\n  doi          = {10.1145/2800986.2800999},\n  timestamp    = {Sun, 02 Oct 2022 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/conf/sbcci/GuazzelliMCM15.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n A Distributed Energy-aware Task Mapping to Achieve Thermal Balancing and Improve Reliability of Many-core Systems.\n \n \n \n \n\n\n \n Mandelli, M.; Castilhos, G. M.; Sassatelli, G.; Ost, L.; and Moraes, F. G.\n\n\n \n\n\n\n In de Lima, R. N.; Cunha, A. I. A.; Plett, C.; and de Oliveira, W. L. A., editor(s), Proceedings of the 28th Symposium on Integrated Circuits and Systems Design, SBCCI 2015, Salvador, Brazil, August 31 - September 4, 2015, pages 13:1–13:7, 2015. ACM\n \n\n\n\n
\n\n\n\n \n \n \"APaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/sbcci/MandelliCSOM15,\n  author       = {Marcelo Mandelli and\n                  Guilherme M. Castilhos and\n                  Gilles Sassatelli and\n                  Luciano Ost and\n                  Fernando Gehm Moraes},\n  editor       = {Robson Nunes de Lima and\n                  Ana Isabela Ara{\\'{u}}jo Cunha and\n                  Calvin Plett and\n                  Wagner Luiz Alves de Oliveira},\n  title        = {A Distributed Energy-aware Task Mapping to Achieve Thermal Balancing\n                  and Improve Reliability of Many-core Systems},\n  booktitle    = {Proceedings of the 28th Symposium on Integrated Circuits and Systems\n                  Design, {SBCCI} 2015, Salvador, Brazil, August 31 - September 4, 2015},\n  pages        = {13:1--13:7},\n  publisher    = {{ACM}},\n  year         = {2015},\n  url          = {https://doi.org/10.1145/2800986.2800992},\n  doi          = {10.1145/2800986.2800992},\n  timestamp    = {Mon, 03 Jan 2022 00:00:00 +0100},\n  biburl       = {https://dblp.org/rec/conf/sbcci/MandelliCSOM15.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n  \n 2014\n \n \n (13)\n \n \n
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\n \n\n \n \n \n \n \n \n Spatially Distributed Dual-Spacer Null Convention Logic Design.\n \n \n \n \n\n\n \n Moreira, M. T.; Trojan, G.; Moraes, F. G.; and Calazans, N. L. V.\n\n\n \n\n\n\n J. Low Power Electron., 10(3): 313–320. 2014.\n \n\n\n\n
\n\n\n\n \n \n \"SpatiallyPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@article{DBLP:journals/jolpe/MoreiraTMC14,\n  author       = {Matheus Trevisan Moreira and\n                  Guilherme Trojan and\n                  Fernando Gehm Moraes and\n                  Ney Laert Vilar Calazans},\n  title        = {Spatially Distributed Dual-Spacer Null Convention Logic Design},\n  journal      = {J. Low Power Electron.},\n  volume       = {10},\n  number       = {3},\n  pages        = {313--320},\n  year         = {2014},\n  url          = {https://doi.org/10.1166/jolpe.2014.1332},\n  doi          = {10.1166/JOLPE.2014.1332},\n  timestamp    = {Sun, 02 Oct 2022 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/journals/jolpe/MoreiraTMC14.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n MoNoC: A monitored network on chip with path adaptation mechanism.\n \n \n \n \n\n\n \n Moreno, E. I.; Webber, T.; Marcon, C. A. M.; Moraes, F. G.; and Calazans, N. L. V.\n\n\n \n\n\n\n J. Syst. Archit., 60(10): 783–795. 2014.\n \n\n\n\n
\n\n\n\n \n \n \"MoNoC:Paper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@article{DBLP:journals/jsa/MorenoWMMC14,\n  author       = {Edson I. Moreno and\n                  Thais Webber and\n                  C{\\'{e}}sar A. M. Marcon and\n                  Fernando Gehm Moraes and\n                  Ney Laert Vilar Calazans},\n  title        = {MoNoC: {A} monitored network on chip with path adaptation mechanism},\n  journal      = {J. Syst. Archit.},\n  volume       = {60},\n  number       = {10},\n  pages        = {783--795},\n  year         = {2014},\n  url          = {https://doi.org/10.1016/j.sysarc.2014.10.002},\n  doi          = {10.1016/J.SYSARC.2014.10.002},\n  timestamp    = {Thu, 14 Oct 2021 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/journals/jsa/MorenoWMMC14.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Differentiated Communication Services for NoC-Based MPSoCs.\n \n \n \n \n\n\n \n Carara, E. A.; Calazans, N. L. V.; and Moraes, F. G.\n\n\n \n\n\n\n IEEE Trans. Computers, 63(3): 595–608. 2014.\n \n\n\n\n
\n\n\n\n \n \n \"DifferentiatedPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@article{DBLP:journals/tc/CararaCM14,\n  author       = {Everton Alceu Carara and\n                  Ney Laert Vilar Calazans and\n                  Fernando Gehm Moraes},\n  title        = {Differentiated Communication Services for NoC-Based MPSoCs},\n  journal      = {{IEEE} Trans. Computers},\n  volume       = {63},\n  number       = {3},\n  pages        = {595--608},\n  year         = {2014},\n  url          = {https://doi.org/10.1109/TC.2012.123},\n  doi          = {10.1109/TC.2012.123},\n  timestamp    = {Sun, 02 Oct 2022 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/journals/tc/CararaCM14.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Beware the Dynamic C-Element.\n \n \n \n \n\n\n \n Moreira, M. T.; Moraes, F. G.; and Calazans, N. L. V.\n\n\n \n\n\n\n IEEE Trans. Very Large Scale Integr. Syst., 22(7): 1644–1647. 2014.\n \n\n\n\n
\n\n\n\n \n \n \"BewarePaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@article{DBLP:journals/tvlsi/MoreiraMC14,\n  author       = {Matheus Trevisan Moreira and\n                  Fernando Gehm Moraes and\n                  Ney Laert Vilar Calazans},\n  title        = {Beware the Dynamic C-Element},\n  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},\n  volume       = {22},\n  number       = {7},\n  pages        = {1644--1647},\n  year         = {2014},\n  url          = {https://doi.org/10.1109/TVLSI.2013.2276538},\n  doi          = {10.1109/TVLSI.2013.2276538},\n  timestamp    = {Sun, 02 Oct 2022 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/journals/tvlsi/MoreiraMC14.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n A method for NoC-based MPSoC energy consumption estimation.\n \n \n \n \n\n\n \n Martins, A. L. M.; Silva, D. R. G.; Castilhos, G. M.; Monteiro, T.; and Moraes, F. G.\n\n\n \n\n\n\n In 21st IEEE International Conference on Electronics, Circuits and Systems, ICECS 2014, Marseille, France, December 7-10, 2014, pages 427–430, 2014. IEEE\n \n\n\n\n
\n\n\n\n \n \n \"APaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/icecsys/MartinsSCMM14,\n  author       = {Andre L. M. Martins and\n                  Douglas R. G. Silva and\n                  Guilherme M. Castilhos and\n                  Thiago Monteiro and\n                  Fernando Gehm Moraes},\n  title        = {A method for NoC-based MPSoC energy consumption estimation},\n  booktitle    = {21st {IEEE} International Conference on Electronics, Circuits and\n                  Systems, {ICECS} 2014, Marseille, France, December 7-10, 2014},\n  pages        = {427--430},\n  publisher    = {{IEEE}},\n  year         = {2014},\n  url          = {https://doi.org/10.1109/ICECS.2014.7050013},\n  doi          = {10.1109/ICECS.2014.7050013},\n  timestamp    = {Wed, 16 Oct 2019 14:14:55 +0200},\n  biburl       = {https://dblp.org/rec/conf/icecsys/MartinsSCMM14.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Effects of the NoC architecture in the performance of NoC-based MPSoCs.\n \n \n \n \n\n\n \n Silva, D. R. G.; Oliveira, B. S.; and Moraes, F. G.\n\n\n \n\n\n\n In 21st IEEE International Conference on Electronics, Circuits and Systems, ICECS 2014, Marseille, France, December 7-10, 2014, pages 431–434, 2014. IEEE\n \n\n\n\n
\n\n\n\n \n \n \"EffectsPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/icecsys/SilvaOM14,\n  author       = {Douglas R. G. Silva and\n                  Bruno S. Oliveira and\n                  Fernando Gehm Moraes},\n  title        = {Effects of the NoC architecture in the performance of NoC-based MPSoCs},\n  booktitle    = {21st {IEEE} International Conference on Electronics, Circuits and\n                  Systems, {ICECS} 2014, Marseille, France, December 7-10, 2014},\n  pages        = {431--434},\n  publisher    = {{IEEE}},\n  year         = {2014},\n  url          = {https://doi.org/10.1109/ICECS.2014.7050014},\n  doi          = {10.1109/ICECS.2014.7050014},\n  timestamp    = {Sun, 02 Jun 2019 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/conf/icecsys/SilvaOM14.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n A monitored NoC with runtime path adaptation.\n \n \n \n \n\n\n \n Moreno, E. I.; Webber, T.; Marcon, C. A. M.; Moraes, F.; and Calazans, N.\n\n\n \n\n\n\n In IEEE International Symposium on Circuits and Systemss, ISCAS 2014, Melbourne, Victoria, Australia, June 1-5, 2014, pages 1965–1968, 2014. IEEE\n \n\n\n\n
\n\n\n\n \n \n \"APaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/iscas/MorenoWMMC14,\n  author       = {Edson I. Moreno and\n                  Thais Webber and\n                  C{\\'{e}}sar A. M. Marcon and\n                  Fernando Moraes and\n                  Ney Calazans},\n  title        = {A monitored NoC with runtime path adaptation},\n  booktitle    = {{IEEE} International Symposium on Circuits and Systemss, {ISCAS} 2014,\n                  Melbourne, Victoria, Australia, June 1-5, 2014},\n  pages        = {1965--1968},\n  publisher    = {{IEEE}},\n  year         = {2014},\n  url          = {https://doi.org/10.1109/ISCAS.2014.6865547},\n  doi          = {10.1109/ISCAS.2014.6865547},\n  timestamp    = {Sun, 02 Oct 2022 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/conf/iscas/MorenoWMMC14.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Tool-set for NoC-based MPSoC debugging - A protocol view perspective.\n \n \n \n \n\n\n \n Ruaro, M.; Carara, E. A.; and Moraes, F. G.\n\n\n \n\n\n\n In IEEE International Symposium on Circuits and Systemss, ISCAS 2014, Melbourne, Victoria, Australia, June 1-5, 2014, pages 2531–2534, 2014. IEEE\n \n\n\n\n
\n\n\n\n \n \n \"Tool-setPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/iscas/RuaroCM14,\n  author       = {Marcelo Ruaro and\n                  Everton Alceu Carara and\n                  Fernando Gehm Moraes},\n  title        = {Tool-set for NoC-based MPSoC debugging - {A} protocol view perspective},\n  booktitle    = {{IEEE} International Symposium on Circuits and Systemss, {ISCAS} 2014,\n                  Melbourne, Victoria, Australia, June 1-5, 2014},\n  pages        = {2531--2534},\n  publisher    = {{IEEE}},\n  year         = {2014},\n  url          = {https://doi.org/10.1109/ISCAS.2014.6865688},\n  doi          = {10.1109/ISCAS.2014.6865688},\n  timestamp    = {Sun, 25 Oct 2020 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/conf/iscas/RuaroCM14.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Runtime fault recovery protocol for NoC-based MPSoCs.\n \n \n \n \n\n\n \n Wächter, E.; Erichsen, A.; Juracy, L.; Amory, A. M.; and Moraes, F.\n\n\n \n\n\n\n In Fifteenth International Symposium on Quality Electronic Design, ISQED 2014, Santa Clara, CA, USA, March 3-5, 2014, pages 132–139, 2014. IEEE\n \n\n\n\n
\n\n\n\n \n \n \"RuntimePaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/isqed/WachterEJAM14,\n  author       = {Eduardo W{\\"{a}}chter and\n                  Augusto Erichsen and\n                  Leonardo Juracy and\n                  Alexandre M. Amory and\n                  Fernando Moraes},\n  title        = {Runtime fault recovery protocol for NoC-based MPSoCs},\n  booktitle    = {Fifteenth International Symposium on Quality Electronic Design, {ISQED}\n                  2014, Santa Clara, CA, USA, March 3-5, 2014},\n  pages        = {132--139},\n  publisher    = {{IEEE}},\n  year         = {2014},\n  url          = {https://doi.org/10.1109/ISQED.2014.6783316},\n  doi          = {10.1109/ISQED.2014.6783316},\n  timestamp    = {Tue, 10 Mar 2020 00:00:00 +0100},\n  biburl       = {https://dblp.org/rec/conf/isqed/WachterEJAM14.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n A framework for MPSoC generation and distributed applications evaluation.\n \n \n \n \n\n\n \n Castilhos, G. M.; Wächter, E.; Madalozzo, G. A.; Erichsen, A.; Monteiro, T.; and Moraes, F.\n\n\n \n\n\n\n In Fifteenth International Symposium on Quality Electronic Design, ISQED 2014, Santa Clara, CA, USA, March 3-5, 2014, pages 408–411, 2014. IEEE\n \n\n\n\n
\n\n\n\n \n \n \"APaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/isqed/CastilhosWMEMM14,\n  author       = {Guilherme M. Castilhos and\n                  Eduardo W{\\"{a}}chter and\n                  Guilherme A. Madalozzo and\n                  Augusto Erichsen and\n                  Thiago Monteiro and\n                  Fernando Moraes},\n  title        = {A framework for MPSoC generation and distributed applications evaluation},\n  booktitle    = {Fifteenth International Symposium on Quality Electronic Design, {ISQED}\n                  2014, Santa Clara, CA, USA, March 3-5, 2014},\n  pages        = {408--411},\n  publisher    = {{IEEE}},\n  year         = {2014},\n  url          = {https://doi.org/10.1109/ISQED.2014.6783353},\n  doi          = {10.1109/ISQED.2014.6783353},\n  timestamp    = {Tue, 10 Mar 2020 00:00:00 +0100},\n  biburl       = {https://dblp.org/rec/conf/isqed/CastilhosWMEMM14.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Fast energy evaluation of embedded applications for many-core systems.\n \n \n \n \n\n\n \n Rosa, F.; Ost, L.; da Rosa, T. R.; Moraes, F. G.; and Reis, R.\n\n\n \n\n\n\n In 24th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS), Palma de Mallorca, Spain, September 29 - Oct. 1, 2014, pages 1–6, 2014. IEEE\n \n\n\n\n
\n\n\n\n \n \n \"FastPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/patmos/RosaORMR14,\n  author       = {Felipe Rosa and\n                  Luciano Ost and\n                  Thiago Raupp da Rosa and\n                  Fernando Gehm Moraes and\n                  Ricardo Reis},\n  title        = {Fast energy evaluation of embedded applications for many-core systems},\n  booktitle    = {24th International Workshop on Power and Timing Modeling, Optimization\n                  and Simulation, PATMOS), Palma de Mallorca, Spain, September 29 -\n                  Oct. 1, 2014},\n  pages        = {1--6},\n  publisher    = {{IEEE}},\n  year         = {2014},\n  url          = {https://doi.org/10.1109/PATMOS.2014.6951893},\n  doi          = {10.1109/PATMOS.2014.6951893},\n  timestamp    = {Thu, 13 Oct 2022 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/conf/patmos/RosaORMR14.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n A Fast Runtime Fault Recovery Approach for NoC-Based MPSoCS for Performance Constrained Applications.\n \n \n \n \n\n\n \n Wächter, E.; Erichsen, A.; Juracy, L.; Amory, A. M.; and Moraes, F. G.\n\n\n \n\n\n\n In Ordonez, E. D. M.; de Azevedo, R. J.; and Kinget, P. R., editor(s), Proceedings of the 27th Symposium on Integrated Circuits and Systems Design, Aracaju, Brazil, September 1-5, 2014, pages 18:1–18:7, 2014. ACM\n \n\n\n\n
\n\n\n\n \n \n \"APaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/sbcci/WachterEJAM14,\n  author       = {Eduardo W{\\"{a}}chter and\n                  Augusto Erichsen and\n                  Leonardo Juracy and\n                  Alexandre M. Amory and\n                  Fernando Gehm Moraes},\n  editor       = {Edward David Moreno Ordonez and\n                  Rodolfo Jardim de Azevedo and\n                  Peter R. Kinget},\n  title        = {A Fast Runtime Fault Recovery Approach for NoC-Based MPSoCS for Performance\n                  Constrained Applications},\n  booktitle    = {Proceedings of the 27th Symposium on Integrated Circuits and Systems\n                  Design, Aracaju, Brazil, September 1-5, 2014},\n  pages        = {18:1--18:7},\n  publisher    = {{ACM}},\n  year         = {2014},\n  url          = {https://doi.org/10.1145/2660540.2660986},\n  doi          = {10.1145/2660540.2660986},\n  timestamp    = {Wed, 25 Sep 2019 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/conf/sbcci/WachterEJAM14.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Runtime QoS Support for MPSoC: a Processor Centric Approach.\n \n \n \n \n\n\n \n Ruaro, M.; Carara, E. A.; and Moraes, F. G.\n\n\n \n\n\n\n In Ordonez, E. D. M.; de Azevedo, R. J.; and Kinget, P. R., editor(s), Proceedings of the 27th Symposium on Integrated Circuits and Systems Design, Aracaju, Brazil, September 1-5, 2014, pages 43:1–43:7, 2014. ACM\n \n\n\n\n
\n\n\n\n \n \n \"RuntimePaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/sbcci/RuaroCM14,\n  author       = {Marcelo Ruaro and\n                  Everton Alceu Carara and\n                  Fernando Gehm Moraes},\n  editor       = {Edward David Moreno Ordonez and\n                  Rodolfo Jardim de Azevedo and\n                  Peter R. Kinget},\n  title        = {Runtime QoS Support for MPSoC: a Processor Centric Approach},\n  booktitle    = {Proceedings of the 27th Symposium on Integrated Circuits and Systems\n                  Design, Aracaju, Brazil, September 1-5, 2014},\n  pages        = {43:1--43:7},\n  publisher    = {{ACM}},\n  year         = {2014},\n  url          = {https://doi.org/10.1145/2660540.2661011},\n  doi          = {10.1145/2660540.2661011},\n  timestamp    = {Sun, 25 Oct 2020 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/conf/sbcci/RuaroCM14.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n  \n 2013\n \n \n (10)\n \n \n
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\n \n\n \n \n \n \n \n \n Power-aware dynamic mapping heuristics for NoC-based MPSoCs using a unified model-based approach.\n \n \n \n \n\n\n \n Ost, L.; Mandelli, M.; Almeida, G. M.; Möller, L.; Indrusiak, L. S.; Sassatelli, G.; Benoit, P.; Glesner, M.; Robert, M.; and Moraes, F.\n\n\n \n\n\n\n ACM Trans. Embed. Comput. Syst., 12(3): 75:1–75:22. 2013.\n \n\n\n\n
\n\n\n\n \n \n \"Power-awarePaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@article{DBLP:journals/tecs/OstMAMISBGRM13,\n  author       = {Luciano Ost and\n                  Marcelo Mandelli and\n                  Gabriel Marchesan Almeida and\n                  Leandro M{\\"{o}}ller and\n                  Leandro Soares Indrusiak and\n                  Gilles Sassatelli and\n                  Pascal Benoit and\n                  Manfred Glesner and\n                  Michel Robert and\n                  Fernando Moraes},\n  title        = {Power-aware dynamic mapping heuristics for NoC-based MPSoCs using\n                  a unified model-based approach},\n  journal      = {{ACM} Trans. Embed. Comput. Syst.},\n  volume       = {12},\n  number       = {3},\n  pages        = {75:1--75:22},\n  year         = {2013},\n  url          = {https://doi.org/10.1145/2442116.2442125},\n  doi          = {10.1145/2442116.2442125},\n  timestamp    = {Sun, 02 Oct 2022 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/journals/tecs/OstMAMISBGRM13.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Topology-agnostic fault-tolerant NoC routing method.\n \n \n \n \n\n\n \n Wächter, E.; Erichsen, A.; Amory, A. M.; and Moraes, F.\n\n\n \n\n\n\n In Macii, E., editor(s), Design, Automation and Test in Europe, DATE 13, Grenoble, France, March 18-22, 2013, pages 1595–1600, 2013. EDA Consortium San Jose, CA, USA / ACM DL\n \n\n\n\n
\n\n\n\n \n \n \"Topology-agnosticPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/date/WachterEAM13,\n  author       = {Eduardo W{\\"{a}}chter and\n                  Augusto Erichsen and\n                  Alexandre M. Amory and\n                  Fernando Moraes},\n  editor       = {Enrico Macii},\n  title        = {Topology-agnostic fault-tolerant NoC routing method},\n  booktitle    = {Design, Automation and Test in Europe, {DATE} 13, Grenoble, France,\n                  March 18-22, 2013},\n  pages        = {1595--1600},\n  publisher    = {{EDA} Consortium San Jose, CA, {USA} / {ACM} {DL}},\n  year         = {2013},\n  url          = {https://doi.org/10.7873/DATE.2013.324},\n  doi          = {10.7873/DATE.2013.324},\n  timestamp    = {Tue, 10 Mar 2020 00:00:00 +0100},\n  biburl       = {https://dblp.org/rec/conf/date/WachterEAM13.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Charge sharing aware NCL gates design.\n \n \n \n \n\n\n \n Moreira, M. T.; Oliveira, B. S.; Moraes, F. G.; and Calazans, N. L. V.\n\n\n \n\n\n\n In 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFTS 2013, New York City, NY, USA, October 2-4, 2013, pages 212–217, 2013. IEEE Computer Society\n \n\n\n\n
\n\n\n\n \n \n \"ChargePaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/dft/MoreiraOMC13,\n  author       = {Matheus T. Moreira and\n                  Bruno S. Oliveira and\n                  Fernando Gehm Moraes and\n                  Ney Laert Vilar Calazans},\n  title        = {Charge sharing aware {NCL} gates design},\n  booktitle    = {2013 {IEEE} International Symposium on Defect and Fault Tolerance\n                  in {VLSI} and Nanotechnology Systems, {DFTS} 2013, New York City,\n                  NY, USA, October 2-4, 2013},\n  pages        = {212--217},\n  publisher    = {{IEEE} Computer Society},\n  year         = {2013},\n  url          = {https://doi.org/10.1109/DFT.2013.6653608},\n  doi          = {10.1109/DFT.2013.6653608},\n  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},\n  biburl       = {https://dblp.org/rec/conf/dft/MoreiraOMC13.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Multi-level MPSoC modeling for reducing software development cycle.\n \n \n \n \n\n\n \n Mandelli, M.; Rosa, F.; Ost, L.; Sassatelli, G.; and Moraes, F. G.\n\n\n \n\n\n\n In 20th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2013, Abu Dhabi, UAE, December 8-11, 2013, pages 489–492, 2013. IEEE\n \n\n\n\n
\n\n\n\n \n \n \"Multi-levelPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/icecsys/MandelliROSM13,\n  author       = {Marcelo Mandelli and\n                  Felipe Rosa and\n                  Luciano Ost and\n                  Gilles Sassatelli and\n                  Fernando Gehm Moraes},\n  title        = {Multi-level MPSoC modeling for reducing software development cycle},\n  booktitle    = {20th {IEEE} International Conference on Electronics, Circuits, and\n                  Systems, {ICECS} 2013, Abu Dhabi, UAE, December 8-11, 2013},\n  pages        = {489--492},\n  publisher    = {{IEEE}},\n  year         = {2013},\n  url          = {https://doi.org/10.1109/ICECS.2013.6815460},\n  doi          = {10.1109/ICECS.2013.6815460},\n  timestamp    = {Thu, 13 Oct 2022 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/conf/icecsys/MandelliROSM13.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Evaluating the scalability of test buses.\n \n \n \n \n\n\n \n Amory, A. M.; Moreira, M. T.; Calazans, N. L. V.; Moraes, F. G.; Lazzari, C.; and Lubaszewski, M. S.\n\n\n \n\n\n\n In Nurmi, J.; Ellervee, P.; Indrusiak, L. S.; Vainio, O.; Thombre, S.; and Raasakka, J., editor(s), 2013 International Symposium on System on Chip, ISSoC 2013, Tampere, Finland, October 23-24, 2013, pages 1–6, 2013. IEEE\n \n\n\n\n
\n\n\n\n \n \n \"EvaluatingPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/issoc/AmoryMCMLL13,\n  author       = {Alexandre M. Amory and\n                  Matheus T. Moreira and\n                  Ney Laert Vilar Calazans and\n                  Fernando Gehm Moraes and\n                  Cristiano Lazzari and\n                  Marcelo Soares Lubaszewski},\n  editor       = {Jari Nurmi and\n                  Peeter Ellervee and\n                  Leandro Soares Indrusiak and\n                  Olli Vainio and\n                  Sarang Thombre and\n                  Jussi Raasakka},\n  title        = {Evaluating the scalability of test buses},\n  booktitle    = {2013 International Symposium on System on Chip, ISSoC 2013, Tampere,\n                  Finland, October 23-24, 2013},\n  pages        = {1--6},\n  publisher    = {{IEEE}},\n  year         = {2013},\n  url          = {https://doi.org/10.1109/ISSoC.2013.6675278},\n  doi          = {10.1109/ISSOC.2013.6675278},\n  timestamp    = {Sat, 19 Oct 2019 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/conf/issoc/AmoryMCMLL13.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Achieving QoS in NoC-based MPSoCs through Dynamic Frequency Scaling.\n \n \n \n \n\n\n \n Guindani, G. M.; and Moraes, F. G.\n\n\n \n\n\n\n In Nurmi, J.; Ellervee, P.; Indrusiak, L. S.; Vainio, O.; Thombre, S.; and Raasakka, J., editor(s), 2013 International Symposium on System on Chip, ISSoC 2013, Tampere, Finland, October 23-24, 2013, pages 1–6, 2013. IEEE\n \n\n\n\n
\n\n\n\n \n \n \"AchievingPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/issoc/GuindaniM13,\n  author       = {Guilherme Montez Guindani and\n                  Fernando Gehm Moraes},\n  editor       = {Jari Nurmi and\n                  Peeter Ellervee and\n                  Leandro Soares Indrusiak and\n                  Olli Vainio and\n                  Sarang Thombre and\n                  Jussi Raasakka},\n  title        = {Achieving QoS in NoC-based MPSoCs through Dynamic Frequency Scaling},\n  booktitle    = {2013 International Symposium on System on Chip, ISSoC 2013, Tampere,\n                  Finland, October 23-24, 2013},\n  pages        = {1--6},\n  publisher    = {{IEEE}},\n  year         = {2013},\n  url          = {https://doi.org/10.1109/ISSoC.2013.6675275},\n  doi          = {10.1109/ISSOC.2013.6675275},\n  timestamp    = {Sun, 02 Jun 2019 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/conf/issoc/GuindaniM13.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Adaptive QoS techniques for NoC-based MPSoCs.\n \n \n \n \n\n\n \n Ruaro, M.; Carara, E. A.; and Moraes, F. G.\n\n\n \n\n\n\n In Nurmi, J.; Ellervee, P.; Indrusiak, L. S.; Vainio, O.; Thombre, S.; and Raasakka, J., editor(s), 2013 International Symposium on System on Chip, ISSoC 2013, Tampere, Finland, October 23-24, 2013, pages 1–6, 2013. IEEE\n \n\n\n\n
\n\n\n\n \n \n \"AdaptivePaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/issoc/RuaroCM13,\n  author       = {Marcelo Ruaro and\n                  Everton Alceu Carara and\n                  Fernando Gehm Moraes},\n  editor       = {Jari Nurmi and\n                  Peeter Ellervee and\n                  Leandro Soares Indrusiak and\n                  Olli Vainio and\n                  Sarang Thombre and\n                  Jussi Raasakka},\n  title        = {Adaptive QoS techniques for NoC-based MPSoCs},\n  booktitle    = {2013 International Symposium on System on Chip, ISSoC 2013, Tampere,\n                  Finland, October 23-24, 2013},\n  pages        = {1--6},\n  publisher    = {{IEEE}},\n  year         = {2013},\n  url          = {https://doi.org/10.1109/ISSoC.2013.6675274},\n  doi          = {10.1109/ISSOC.2013.6675274},\n  timestamp    = {Sun, 02 Jun 2019 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/conf/issoc/RuaroCM13.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Determining the test sources/sinks for NoC TAMs.\n \n \n \n \n\n\n \n Amory, A. M.; Moreno, E. I.; Moraes, F.; and Lubaszewski, M.\n\n\n \n\n\n\n In IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2013, Natal, Brazil, August 5-7, 2013, pages 8–13, 2013. IEEE Computer Socity\n \n\n\n\n
\n\n\n\n \n \n \"DeterminingPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/isvlsi/AmoryMML13,\n  author       = {Alexandre M. Amory and\n                  Edson I. Moreno and\n                  Fernando Moraes and\n                  Marcelo Lubaszewski},\n  title        = {Determining the test sources/sinks for NoC TAMs},\n  booktitle    = {{IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2013, Natal,\n                  Brazil, August 5-7, 2013},\n  pages        = {8--13},\n  publisher    = {{IEEE} Computer Socity},\n  year         = {2013},\n  url          = {https://doi.org/10.1109/ISVLSI.2013.6654615},\n  doi          = {10.1109/ISVLSI.2013.6654615},\n  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},\n  biburl       = {https://dblp.org/rec/conf/isvlsi/AmoryMML13.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Distributed resource management in NoC-based MPSoCs with dynamic cluster sizes.\n \n \n \n \n\n\n \n Castilhos, G. M.; Mandelli, M.; Madalozzo, G. A.; and Moraes, F.\n\n\n \n\n\n\n In IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2013, Natal, Brazil, August 5-7, 2013, pages 153–158, 2013. IEEE Computer Socity\n \n\n\n\n
\n\n\n\n \n \n \"DistributedPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/isvlsi/CastilhosMMM13,\n  author       = {Guilherme M. Castilhos and\n                  Marcelo Mandelli and\n                  Guilherme A. Madalozzo and\n                  Fernando Moraes},\n  title        = {Distributed resource management in NoC-based MPSoCs with dynamic cluster\n                  sizes},\n  booktitle    = {{IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2013, Natal,\n                  Brazil, August 5-7, 2013},\n  pages        = {153--158},\n  publisher    = {{IEEE} Computer Socity},\n  year         = {2013},\n  url          = {https://doi.org/10.1109/ISVLSI.2013.6654651},\n  doi          = {10.1109/ISVLSI.2013.6654651},\n  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},\n  biburl       = {https://dblp.org/rec/conf/isvlsi/CastilhosMMM13.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Fault recovery communication protocol for NoC-based MPSoCs.\n \n \n \n \n\n\n \n Wächter, E. W.; Amory, A. M.; and Moraes, F. G.\n\n\n \n\n\n\n In IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2013, Natal, Brazil, August 5-7, 2013, pages 219–220, 2013. IEEE Computer Socity\n \n\n\n\n
\n\n\n\n \n \n \"FaultPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/isvlsi/WachterAM13,\n  author       = {Eduardo Weber W{\\"{a}}chter and\n                  Alexandre M. Amory and\n                  Fernando Gehm Moraes},\n  title        = {Fault recovery communication protocol for NoC-based MPSoCs},\n  booktitle    = {{IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2013, Natal,\n                  Brazil, August 5-7, 2013},\n  pages        = {219--220},\n  publisher    = {{IEEE} Computer Socity},\n  year         = {2013},\n  url          = {https://doi.org/10.1109/ISVLSI.2013.6654648},\n  doi          = {10.1109/ISVLSI.2013.6654648},\n  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},\n  biburl       = {https://dblp.org/rec/conf/isvlsi/WachterAM13.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n  \n 2012\n \n \n (10)\n \n \n
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\n \n\n \n \n \n \n \n \n Enabling Adaptive Techniques in Heterogeneous MPSoCs Based on Virtualization.\n \n \n \n \n\n\n \n Ost, L.; Varyani, S.; Indrusiak, L. S.; Mandelli, M.; Almeida, G. M.; Wächter, E.; Moraes, F.; and Sassatelli, G.\n\n\n \n\n\n\n ACM Trans. Reconfigurable Technol. Syst., 5(3): 17:1–17:11. 2012.\n \n\n\n\n
\n\n\n\n \n \n \"EnablingPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@article{DBLP:journals/trets/OstVIMAWMS12,\n  author       = {Luciano Ost and\n                  Sameer Varyani and\n                  Leandro Soares Indrusiak and\n                  Marcelo Mandelli and\n                  Gabriel Marchesan Almeida and\n                  Eduardo W{\\"{a}}chter and\n                  Fernando Moraes and\n                  Gilles Sassatelli},\n  title        = {Enabling Adaptive Techniques in Heterogeneous MPSoCs Based on Virtualization},\n  journal      = {{ACM} Trans. Reconfigurable Technol. Syst.},\n  volume       = {5},\n  number       = {3},\n  pages        = {17:1--17:11},\n  year         = {2012},\n  url          = {https://doi.org/10.1145/2362374.2362381},\n  doi          = {10.1145/2362374.2362381},\n  timestamp    = {Mon, 03 Jan 2022 00:00:00 +0100},\n  biburl       = {https://dblp.org/rec/journals/trets/OstVIMAWMS12.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n A generic FPGA emulation framework.\n \n \n \n \n\n\n \n Moraes, F. G.; Moreira, M. T.; Lucas, C.; Correa, D.; de O. Cardoso, D.; Magnaguagno, M.; Castilhos, G. M.; and Calazans, N. L. V.\n\n\n \n\n\n\n In 19th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2012, Seville, Spain, December 9-12, 2012, pages 233–236, 2012. IEEE\n \n\n\n\n
\n\n\n\n \n \n \"APaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/icecsys/MoraesMLCCMCC12,\n  author       = {Fernando Gehm Moraes and\n                  Matheus T. Moreira and\n                  Carlos Lucas and\n                  D. Correa and\n                  Douglas de O. Cardoso and\n                  M. Magnaguagno and\n                  Guilherme M. Castilhos and\n                  Ney Laert Vilar Calazans},\n  title        = {A generic {FPGA} emulation framework},\n  booktitle    = {19th {IEEE} International Conference on Electronics, Circuits and\n                  Systems, {ICECS} 2012, Seville, Spain, December 9-12, 2012},\n  pages        = {233--236},\n  publisher    = {{IEEE}},\n  year         = {2012},\n  url          = {https://doi.org/10.1109/ICECS.2012.6463758},\n  doi          = {10.1109/ICECS.2012.6463758},\n  timestamp    = {Sun, 02 Oct 2022 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/conf/icecsys/MoraesMLCCMCC12.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Enhancing performance of MPSoCs through distributed resource management.\n \n \n \n \n\n\n \n Mandelli, M.; Castilhos, G. M.; and Moraes, F. G.\n\n\n \n\n\n\n In 19th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2012, Seville, Spain, December 9-12, 2012, pages 544–547, 2012. IEEE\n \n\n\n\n
\n\n\n\n \n \n \"EnhancingPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/icecsys/MandelliCM12,\n  author       = {Marcelo Mandelli and\n                  Guilherme M. Castilhos and\n                  Fernando Gehm Moraes},\n  title        = {Enhancing performance of MPSoCs through distributed resource management},\n  booktitle    = {19th {IEEE} International Conference on Electronics, Circuits and\n                  Systems, {ICECS} 2012, Seville, Spain, December 9-12, 2012},\n  pages        = {544--547},\n  publisher    = {{IEEE}},\n  year         = {2012},\n  url          = {https://doi.org/10.1109/ICECS.2012.6463689},\n  doi          = {10.1109/ICECS.2012.6463689},\n  timestamp    = {Sun, 02 Jun 2019 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/conf/icecsys/MandelliCM12.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Evaluation of adaptive management techniques in NoC-Based MPSoCs.\n \n \n \n \n\n\n \n Moraes, F. G.; Carara, E. A.; Ruaro, M.; and Madalozzo, G. A.\n\n\n \n\n\n\n In 19th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2012, Seville, Spain, December 9-12, 2012, pages 548–551, 2012. IEEE\n \n\n\n\n
\n\n\n\n \n \n \"EvaluationPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/icecsys/MoraesCRM12,\n  author       = {Fernando Gehm Moraes and\n                  Everton Alceu Carara and\n                  Marcelo Ruaro and\n                  Guilherme A. Madalozzo},\n  title        = {Evaluation of adaptive management techniques in NoC-Based MPSoCs},\n  booktitle    = {19th {IEEE} International Conference on Electronics, Circuits and\n                  Systems, {ICECS} 2012, Seville, Spain, December 9-12, 2012},\n  pages        = {548--551},\n  publisher    = {{IEEE}},\n  year         = {2012},\n  url          = {https://doi.org/10.1109/ICECS.2012.6463688},\n  doi          = {10.1109/ICECS.2012.6463688},\n  timestamp    = {Sun, 25 Oct 2020 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/conf/icecsys/MoraesCRM12.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Proposal and evaluation of a task migration protocol for NoC-based MPSoCs.\n \n \n \n \n\n\n \n Moraes, F. G.; Madalozzo, G. A.; Castilhos, G. M.; and Carara, E. A.\n\n\n \n\n\n\n In 2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012, Seoul, Korea (South), May 20-23, 2012, pages 644–647, 2012. IEEE\n \n\n\n\n
\n\n\n\n \n \n \"ProposalPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/iscas/MoraesMCC12,\n  author       = {Fernando Gehm Moraes and\n                  Guilherme A. Madalozzo and\n                  Guilherme M. Castilhos and\n                  Everton Alceu Carara},\n  title        = {Proposal and evaluation of a task migration protocol for NoC-based\n                  MPSoCs},\n  booktitle    = {2012 {IEEE} International Symposium on Circuits and Systems, {ISCAS}\n                  2012, Seoul, Korea (South), May 20-23, 2012},\n  pages        = {644--647},\n  publisher    = {{IEEE}},\n  year         = {2012},\n  url          = {https://doi.org/10.1109/ISCAS.2012.6272114},\n  doi          = {10.1109/ISCAS.2012.6272114},\n  timestamp    = {Wed, 16 Oct 2019 14:14:49 +0200},\n  biburl       = {https://dblp.org/rec/conf/iscas/MoraesMCC12.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Impact of C-elements in asynchronous circuits.\n \n \n \n \n\n\n \n Moreira, M. T.; de Oliveira, B. C.; Moraes, F.; and Calazans, N.\n\n\n \n\n\n\n In Bowman, K. A.; Gadepally, K. V.; Chatterjee, P.; Budnik, M. M.; and Immaneni, L., editor(s), Thirteenth International Symposium on Quality Electronic Design, ISQED 2012, Santa Clara, CA, USA, March 19-21, 2012, pages 437–343, 2012. IEEE\n \n\n\n\n
\n\n\n\n \n \n \"ImpactPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/isqed/MoreiraOMC12,\n  author       = {Matheus T. Moreira and\n                  Bruno Cruz de Oliveira and\n                  Fernando Moraes and\n                  Ney Calazans},\n  editor       = {Keith A. Bowman and\n                  Kamesh V. Gadepally and\n                  Pallab Chatterjee and\n                  Mark M. Budnik and\n                  Lalitha Immaneni},\n  title        = {Impact of C-elements in asynchronous circuits},\n  booktitle    = {Thirteenth International Symposium on Quality Electronic Design, {ISQED}\n                  2012, Santa Clara, CA, USA, March 19-21, 2012},\n  pages        = {437--343},\n  publisher    = {{IEEE}},\n  year         = {2012},\n  url          = {https://doi.org/10.1109/ISQED.2012.6187530},\n  doi          = {10.1109/ISQED.2012.6187530},\n  timestamp    = {Sun, 02 Oct 2022 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/conf/isqed/MoreiraOMC12.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Comparative analysis of dynamic task mapping heuristics in heterogeneous NoC-based MPSoCs.\n \n \n \n \n\n\n \n Möller, L.; Indrusiak, L. S.; Ost, L.; Moraes, F. G.; and Glesner, M.\n\n\n \n\n\n\n In 2012 International Symposium on System on Chip, ISSoC 2012, Tampere, Finland, October 10-12, 2012, pages 1–4, 2012. IEEE\n \n\n\n\n
\n\n\n\n \n \n \"ComparativePaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
\n
@inproceedings{DBLP:conf/issoc/MollerIOMG12,\n  author       = {Leandro M{\\"{o}}ller and\n                  Leandro Soares Indrusiak and\n                  Luciano Ost and\n                  Fernando Gehm Moraes and\n                  Manfred Glesner},\n  title        = {Comparative analysis of dynamic task mapping heuristics in heterogeneous\n                  NoC-based MPSoCs},\n  booktitle    = {2012 International Symposium on System on Chip, ISSoC 2012, Tampere,\n                  Finland, October 10-12, 2012},\n  pages        = {1--4},\n  publisher    = {{IEEE}},\n  year         = {2012},\n  url          = {https://doi.org/10.1109/ISSoC.2012.6376357},\n  doi          = {10.1109/ISSOC.2012.6376357},\n  timestamp    = {Mon, 03 Jan 2022 00:00:00 +0100},\n  biburl       = {https://dblp.org/rec/conf/issoc/MollerIOMG12.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n A spectrum of MPSoC models for design space exploration and its use.\n \n \n \n \n\n\n \n Petry, C. A.; Wächter, E.; Castilhos, G. M.; Moraes, F. G.; and Calazans, N. L. V.\n\n\n \n\n\n\n In Proceedings of the 23rd IEEE International Symposium on Rapid System Prototyping, RSP 2012, Tampere, Finland, October 11-12, 2012, pages 30–35, 2012. IEEE\n \n\n\n\n
\n\n\n\n \n \n \"APaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/rsp/PetryWCMC12,\n  author       = {Carlos A. Petry and\n                  Eduardo W{\\"{a}}chter and\n                  Guilherme M. Castilhos and\n                  Fernando Gehm Moraes and\n                  Ney Laert Vilar Calazans},\n  title        = {A spectrum of MPSoC models for design space exploration and its use},\n  booktitle    = {Proceedings of the 23rd {IEEE} International Symposium on Rapid System\n                  Prototyping, {RSP} 2012, Tampere, Finland, October 11-12, 2012},\n  pages        = {30--35},\n  publisher    = {{IEEE}},\n  year         = {2012},\n  url          = {https://doi.org/10.1109/RSP.2012.6380687},\n  doi          = {10.1109/RSP.2012.6380687},\n  timestamp    = {Sun, 02 Oct 2022 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/conf/rsp/PetryWCMC12.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Power consumption reduction in MPSoCs through DFS.\n \n \n \n \n\n\n \n da Rosa, T. R.; Larrea, V.; Calazans, N.; and Moraes, F. G.\n\n\n \n\n\n\n In 25th Symposium on Integrated Circuits and Systems Design, SBCCI 2012, Brasilia, Brazil, August 30 - September 2, 2012, pages 1–6, 2012. IEEE\n \n\n\n\n
\n\n\n\n \n \n \"PowerPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/sbcci/RosaLCM12,\n  author       = {Thiago R. da Rosa and\n                  Vivian Larrea and\n                  Ney Calazans and\n                  Fernando Gehm Moraes},\n  title        = {Power consumption reduction in MPSoCs through {DFS}},\n  booktitle    = {25th Symposium on Integrated Circuits and Systems Design, {SBCCI}\n                  2012, Brasilia, Brazil, August 30 - September 2, 2012},\n  pages        = {1--6},\n  publisher    = {{IEEE}},\n  year         = {2012},\n  url          = {https://doi.org/10.1109/SBCCI.2012.6344429},\n  doi          = {10.1109/SBCCI.2012.6344429},\n  timestamp    = {Wed, 16 Oct 2019 14:14:55 +0200},\n  biburl       = {https://dblp.org/rec/conf/sbcci/RosaLCM12.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n MAZENOC: Novel approach for fault-tolerant NOC routing.\n \n \n \n \n\n\n \n Wächter, E. W.; and Moraes, F. G.\n\n\n \n\n\n\n In Sridhar, R.; Schuhmann, N.; and Shi, K., editor(s), IEEE 25th International SOC Conference, SOCC 2012, Niagara Falls, NY, USA, September 12-14, 2012, pages 364–369, 2012. IEEE\n \n\n\n\n
\n\n\n\n \n \n \"MAZENOC:Paper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/socc/WachterM12,\n  author       = {Eduardo Weber W{\\"{a}}chter and\n                  Fernando Gehm Moraes},\n  editor       = {Ramalingam Sridhar and\n                  Norbert Schuhmann and\n                  Kaijian Shi},\n  title        = {{MAZENOC:} Novel approach for fault-tolerant {NOC} routing},\n  booktitle    = {{IEEE} 25th International {SOC} Conference, {SOCC} 2012, Niagara Falls,\n                  NY, USA, September 12-14, 2012},\n  pages        = {364--369},\n  publisher    = {{IEEE}},\n  year         = {2012},\n  url          = {https://doi.org/10.1109/SOCC.2012.6398333},\n  doi          = {10.1109/SOCC.2012.6398333},\n  timestamp    = {Wed, 16 Oct 2019 14:14:53 +0200},\n  biburl       = {https://dblp.org/rec/conf/socc/WachterM12.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n  \n 2011\n \n \n (20)\n \n \n
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\n \n\n \n \n \n \n \n \n Exploring NoC-Based MPSoC Design Space with Power Estimation Models.\n \n \n \n \n\n\n \n Ost, L.; Guindani, G. M.; Moraes, F. G.; Indrusiak, L. S.; and Määttä, S.\n\n\n \n\n\n\n IEEE Des. Test Comput., 28(2): 16–29. 2011.\n \n\n\n\n
\n\n\n\n \n \n \"ExploringPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@article{DBLP:journals/dt/OstGMIM11,\n  author       = {Luciano Ost and\n                  Guilherme Montez Guindani and\n                  Fernando Gehm Moraes and\n                  Leandro Soares Indrusiak and\n                  Sanna M{\\"{a}}{\\"{a}}tt{\\"{a}}},\n  title        = {Exploring NoC-Based MPSoC Design Space with Power Estimation Models},\n  journal      = {{IEEE} Des. Test Comput.},\n  volume       = {28},\n  number       = {2},\n  pages        = {16--29},\n  year         = {2011},\n  url          = {https://doi.org/10.1109/MDT.2010.116},\n  doi          = {10.1109/MDT.2010.116},\n  timestamp    = {Mon, 03 Jan 2022 00:00:00 +0100},\n  biburl       = {https://dblp.org/rec/journals/dt/OstGMIM11.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n A Robust Architectural Approach for Cryptographic Algorithms Using GALS Pipelines.\n \n \n \n \n\n\n \n Soares, R. I.; Calazans, N. L. V.; Moraes, F. G.; Maurine, P.; and Torres, L.\n\n\n \n\n\n\n IEEE Des. Test Comput., 28(5): 62–71. 2011.\n \n\n\n\n
\n\n\n\n \n \n \"APaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@article{DBLP:journals/dt/SoaresCMMT11,\n  author       = {Rafael Iankowski Soares and\n                  Ney Laert Vilar Calazans and\n                  Fernando Gehm Moraes and\n                  Philippe Maurine and\n                  Lionel Torres},\n  title        = {A Robust Architectural Approach for Cryptographic Algorithms Using\n                  {GALS} Pipelines},\n  journal      = {{IEEE} Des. Test Comput.},\n  volume       = {28},\n  number       = {5},\n  pages        = {62--71},\n  year         = {2011},\n  url          = {https://doi.org/10.1109/MDT.2011.69},\n  doi          = {10.1109/MDT.2011.69},\n  timestamp    = {Sun, 02 Oct 2022 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/journals/dt/SoaresCMMT11.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n A new test scheduling algorithm based on Networks-on-Chip as Test Access Mechanisms.\n \n \n \n \n\n\n \n Amory, A. M.; Lazzari, C.; Lubaszewski, M.; and Moraes, F. G.\n\n\n \n\n\n\n J. Parallel Distributed Comput., 71(5): 675–686. 2011.\n \n\n\n\n
\n\n\n\n \n \n \"APaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@article{DBLP:journals/jpdc/AmoryLLM11,\n  author       = {Alexandre M. Amory and\n                  Cristiano Lazzari and\n                  Marcelo Lubaszewski and\n                  Fernando Gehm Moraes},\n  title        = {A new test scheduling algorithm based on Networks-on-Chip as Test\n                  Access Mechanisms},\n  journal      = {J. Parallel Distributed Comput.},\n  volume       = {71},\n  number       = {5},\n  pages        = {675--686},\n  year         = {2011},\n  url          = {https://doi.org/10.1016/j.jpdc.2010.09.008},\n  doi          = {10.1016/J.JPDC.2010.09.008},\n  timestamp    = {Sat, 22 Feb 2020 00:00:00 +0100},\n  biburl       = {https://dblp.org/rec/journals/jpdc/AmoryLLM11.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n CAFES: A framework for intrachip application modeling and communication architecture design.\n \n \n \n \n\n\n \n Marcon, C. A. M.; Calazans, N.; Moreno, E. I.; Moraes, F.; Hessel, F.; and Susin, A. A.\n\n\n \n\n\n\n J. Parallel Distributed Comput., 71(5): 714–728. 2011.\n \n\n\n\n
\n\n\n\n \n \n \"CAFES:Paper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@article{DBLP:journals/jpdc/MarconCMMHS11,\n  author       = {C{\\'{e}}sar A. M. Marcon and\n                  Ney Calazans and\n                  Edson I. Moreno and\n                  Fernando Moraes and\n                  Fabiano Hessel and\n                  Altamiro Amadeu Susin},\n  title        = {{CAFES:} {A} framework for intrachip application modeling and communication\n                  architecture design},\n  journal      = {J. Parallel Distributed Comput.},\n  volume       = {71},\n  number       = {5},\n  pages        = {714--728},\n  year         = {2011},\n  url          = {https://doi.org/10.1016/j.jpdc.2010.10.002},\n  doi          = {10.1016/J.JPDC.2010.10.002},\n  timestamp    = {Sun, 02 Oct 2022 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/journals/jpdc/MarconCMMHS11.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Achieving composability in NoC-based MPSoCs through QoS management at software level.\n \n \n \n \n\n\n \n Carara, E.; Almeida, G. M.; Sassatelli, G.; and Moraes, F. G.\n\n\n \n\n\n\n In Design, Automation and Test in Europe, DATE 2011, Grenoble, France, March 14-18, 2011, pages 407–412, 2011. IEEE\n \n\n\n\n
\n\n\n\n \n \n \"AchievingPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/date/CararaASM11,\n  author       = {Everton Carara and\n                  Gabriel Marchesan Almeida and\n                  Gilles Sassatelli and\n                  Fernando Gehm Moraes},\n  title        = {Achieving composability in NoC-based MPSoCs through QoS management\n                  at software level},\n  booktitle    = {Design, Automation and Test in Europe, {DATE} 2011, Grenoble, France,\n                  March 14-18, 2011},\n  pages        = {407--412},\n  publisher    = {{IEEE}},\n  year         = {2011},\n  url          = {https://doi.org/10.1109/DATE.2011.5763071},\n  doi          = {10.1109/DATE.2011.5763071},\n  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},\n  biburl       = {https://dblp.org/rec/conf/date/CararaASM11.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Evaluating energy consumption of homogeneous MPSoCs using spare tiles.\n \n \n \n \n\n\n \n Amory, A. M.; Ost, L.; Marcon, C. A. M.; Moraes, F. G.; and Lubaszewski, M.\n\n\n \n\n\n\n In Design, Automation and Test in Europe, DATE 2011, Grenoble, France, March 14-18, 2011, pages 1164–1167, 2011. IEEE\n \n\n\n\n
\n\n\n\n \n \n \"EvaluatingPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/date/AmoryOMML11,\n  author       = {Alexandre M. Amory and\n                  Luciano Ost and\n                  C{\\'{e}}sar A. M. Marcon and\n                  Fernando Gehm Moraes and\n                  Marcelo Lubaszewski},\n  title        = {Evaluating energy consumption of homogeneous MPSoCs using spare tiles},\n  booktitle    = {Design, Automation and Test in Europe, {DATE} 2011, Grenoble, France,\n                  March 14-18, 2011},\n  pages        = {1164--1167},\n  publisher    = {{IEEE}},\n  year         = {2011},\n  url          = {https://doi.org/10.1109/DATE.2011.5763304},\n  doi          = {10.1109/DATE.2011.5763304},\n  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},\n  biburl       = {https://dblp.org/rec/conf/date/AmoryOMML11.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Dynamic Flow Reconfiguration Strategy to Avoid Communication Hot-Spots.\n \n \n \n \n\n\n \n Prolonge, R.; Clermidy, F.; Tedesco, L.; and Moraes, F.\n\n\n \n\n\n\n In 14th Euromicro Conference on Digital System Design, Architectures, Methods and Tools, DSD 2011, August 31 - September 2, 2011, Oulu, Finland, pages 519–524, 2011. IEEE Computer Society\n \n\n\n\n
\n\n\n\n \n \n \"DynamicPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/dsd/ProlongeCTM11,\n  author       = {Romain Prolonge and\n                  Fabien Clermidy and\n                  Leonel Tedesco and\n                  Fernando Moraes},\n  title        = {Dynamic Flow Reconfiguration Strategy to Avoid Communication Hot-Spots},\n  booktitle    = {14th Euromicro Conference on Digital System Design, Architectures,\n                  Methods and Tools, {DSD} 2011, August 31 - September 2, 2011, Oulu,\n                  Finland},\n  pages        = {519--524},\n  publisher    = {{IEEE} Computer Society},\n  year         = {2011},\n  url          = {https://doi.org/10.1109/DSD.2011.72},\n  doi          = {10.1109/DSD.2011.72},\n  timestamp    = {Thu, 23 Mar 2023 00:00:00 +0100},\n  biburl       = {https://dblp.org/rec/conf/dsd/ProlongeCTM11.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Adapting a C-element design flow for low power.\n \n \n \n \n\n\n \n Moreira, M. T.; de Oliveira, B. C.; Pontes, J. J. H.; Moraes, F.; and Calazans, N.\n\n\n \n\n\n\n In 18th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2011, Beirut, Lebanon, December 11-14, 2011, pages 45–48, 2011. IEEE\n \n\n\n\n
\n\n\n\n \n \n \"AdaptingPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/icecsys/MoreiraOPMC11,\n  author       = {Matheus T. Moreira and\n                  Bruno Cruz de Oliveira and\n                  Julian J. H. Pontes and\n                  Fernando Moraes and\n                  Ney Calazans},\n  title        = {Adapting a C-element design flow for low power},\n  booktitle    = {18th {IEEE} International Conference on Electronics, Circuits and\n                  Systems, {ICECS} 2011, Beirut, Lebanon, December 11-14, 2011},\n  pages        = {45--48},\n  publisher    = {{IEEE}},\n  year         = {2011},\n  url          = {https://doi.org/10.1109/ICECS.2011.6122210},\n  doi          = {10.1109/ICECS.2011.6122210},\n  timestamp    = {Sun, 02 Oct 2022 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/conf/icecsys/MoreiraOPMC11.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Predictive Dynamic Frequency Scaling for Multi-Processor Systems-on-Chip.\n \n \n \n \n\n\n \n Almeida, G. M.; Busseuil, R.; Carara, E. A.; Hebert, N.; Varyani, S.; Sassatelli, G.; Benoit, P.; Torres, L.; and Moraes, F. G.\n\n\n \n\n\n\n In International Symposium on Circuits and Systems (ISCAS 2011), May 15-19 2011, Rio de Janeiro, Brazil, pages 1500–1503, 2011. IEEE\n \n\n\n\n
\n\n\n\n \n \n \"PredictivePaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/iscas/AlmeidaBCHVSBTM11,\n  author       = {Gabriel Marchesan Almeida and\n                  R{\\'{e}}mi Busseuil and\n                  Everton Alceu Carara and\n                  Nicolas Hebert and\n                  Sameer Varyani and\n                  Gilles Sassatelli and\n                  Pascal Benoit and\n                  Lionel Torres and\n                  Fernando Gehm Moraes},\n  title        = {Predictive Dynamic Frequency Scaling for Multi-Processor Systems-on-Chip},\n  booktitle    = {International Symposium on Circuits and Systems {(ISCAS} 2011), May\n                  15-19 2011, Rio de Janeiro, Brazil},\n  pages        = {1500--1503},\n  publisher    = {{IEEE}},\n  year         = {2011},\n  url          = {https://doi.org/10.1109/ISCAS.2011.5937859},\n  doi          = {10.1109/ISCAS.2011.5937859},\n  timestamp    = {Wed, 16 Oct 2019 14:14:49 +0200},\n  biburl       = {https://dblp.org/rec/conf/iscas/AlmeidaBCHVSBTM11.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Energy-aware dynamic task mapping for NoC-based MPSoCs.\n \n \n \n \n\n\n \n Mandelli, M.; Ost, L.; Carara, E.; Guindani, G. M.; Gouvea, T.; Medeiros, G.; and Moraes, F. G.\n\n\n \n\n\n\n In International Symposium on Circuits and Systems (ISCAS 2011), May 15-19 2011, Rio de Janeiro, Brazil, pages 1676–1679, 2011. IEEE\n \n\n\n\n
\n\n\n\n \n \n \"Energy-awarePaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/iscas/MandelliOCGGMM11,\n  author       = {Marcelo Mandelli and\n                  Luciano Ost and\n                  Everton Carara and\n                  Guilherme Montez Guindani and\n                  Thiago Gouvea and\n                  Guilherme Medeiros and\n                  Fernando Gehm Moraes},\n  title        = {Energy-aware dynamic task mapping for NoC-based MPSoCs},\n  booktitle    = {International Symposium on Circuits and Systems {(ISCAS} 2011), May\n                  15-19 2011, Rio de Janeiro, Brazil},\n  pages        = {1676--1679},\n  publisher    = {{IEEE}},\n  year         = {2011},\n  url          = {https://doi.org/10.1109/ISCAS.2011.5937903},\n  doi          = {10.1109/ISCAS.2011.5937903},\n  timestamp    = {Mon, 03 Jan 2022 00:00:00 +0100},\n  biburl       = {https://dblp.org/rec/conf/iscas/MandelliOCGGMM11.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Exploiting multicast messages in cache-coherence protocols for NoC-based MPSoCs.\n \n \n \n \n\n\n \n Chaves, T. M.; Carara, E. A.; and Moraes, F. G.\n\n\n \n\n\n\n In Proceedings of the 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip, ReCoSoC 2011, Montpellier, France, 20-22 June, 2011, pages 1–6, 2011. IEEE\n \n\n\n\n
\n\n\n\n \n \n \"ExploitingPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/recosoc/ChavesCM11,\n  author       = {Tales Marchesan Chaves and\n                  Everton Alceu Carara and\n                  Fernando Gehm Moraes},\n  title        = {Exploiting multicast messages in cache-coherence protocols for NoC-based\n                  MPSoCs},\n  booktitle    = {Proceedings of the 6th International Workshop on Reconfigurable Communication-centric\n                  Systems-on-Chip, ReCoSoC 2011, Montpellier, France, 20-22 June, 2011},\n  pages        = {1--6},\n  publisher    = {{IEEE}},\n  year         = {2011},\n  url          = {https://doi.org/10.1109/ReCoSoC.2011.5981492},\n  doi          = {10.1109/RECOSOC.2011.5981492},\n  timestamp    = {Wed, 16 Oct 2019 14:14:56 +0200},\n  biburl       = {https://dblp.org/rec/conf/recosoc/ChavesCM11.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Exploring heterogeneous NoC-based MPSoCs: From FPGA to high-level modeling.\n \n \n \n \n\n\n \n Ost, L.; Almeida, G. M.; Mandelli, M.; Wächter, E.; Varyani, S.; Sassatelli, G.; Indrusiak, L. S.; Robert, M.; and Moraes, F.\n\n\n \n\n\n\n In Proceedings of the 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip, ReCoSoC 2011, Montpellier, France, 20-22 June, 2011, pages 1–8, 2011. IEEE\n \n\n\n\n
\n\n\n\n \n \n \"ExploringPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/recosoc/OstAMWVSIRM11,\n  author       = {Luciano Ost and\n                  Gabriel Marchesan Almeida and\n                  Marcelo Mandelli and\n                  Eduardo W{\\"{a}}chter and\n                  Sameer Varyani and\n                  Gilles Sassatelli and\n                  Leandro Soares Indrusiak and\n                  Michel Robert and\n                  Fernando Moraes},\n  title        = {Exploring heterogeneous NoC-based MPSoCs: From {FPGA} to high-level\n                  modeling},\n  booktitle    = {Proceedings of the 6th International Workshop on Reconfigurable Communication-centric\n                  Systems-on-Chip, ReCoSoC 2011, Montpellier, France, 20-22 June, 2011},\n  pages        = {1--8},\n  publisher    = {{IEEE}},\n  year         = {2011},\n  url          = {https://doi.org/10.1109/ReCoSoC.2011.5981517},\n  doi          = {10.1109/RECOSOC.2011.5981517},\n  timestamp    = {Mon, 03 Jan 2022 00:00:00 +0100},\n  biburl       = {https://dblp.org/rec/conf/recosoc/OstAMWVSIRM11.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n HeMPS-S: A homogeneous NoC-based MPSoCs framework prototyped in FPGAs.\n \n \n \n \n\n\n \n Wächter, E.; Biazi, A.; and Moraes, F. G.\n\n\n \n\n\n\n In Proceedings of the 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip, ReCoSoC 2011, Montpellier, France, 20-22 June, 2011, pages 1–8, 2011. IEEE\n \n\n\n\n
\n\n\n\n \n \n \"HeMPS-S:Paper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/recosoc/WachterBM11,\n  author       = {Eduardo W{\\"{a}}chter and\n                  Adelcio Biazi and\n                  Fernando Gehm Moraes},\n  title        = {HeMPS-S: {A} homogeneous NoC-based MPSoCs framework prototyped in\n                  FPGAs},\n  booktitle    = {Proceedings of the 6th International Workshop on Reconfigurable Communication-centric\n                  Systems-on-Chip, ReCoSoC 2011, Montpellier, France, 20-22 June, 2011},\n  pages        = {1--8},\n  publisher    = {{IEEE}},\n  year         = {2011},\n  url          = {https://doi.org/10.1109/ReCoSoC.2011.5981498},\n  doi          = {10.1109/RECOSOC.2011.5981498},\n  timestamp    = {Sun, 02 Jun 2019 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/conf/recosoc/WachterBM11.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Task mapping on NoC-based MPSoCs with faulty tiles: Evaluating the energy consumption and the application execution time.\n \n \n \n \n\n\n \n Amory, A. M.; Marcon, C. A. M.; Moraes, F. G.; and Lubaszewski, M.\n\n\n \n\n\n\n In Proceedings of the 22nd IEEE International Symposium on Rapid System Prototyping, RSP 2011, Karlsruhe, Germany, 24-27 May, 2011, pages 164–170, 2011. IEEE\n \n\n\n\n
\n\n\n\n \n \n \"TaskPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/rsp/AmoryMML11,\n  author       = {Alexandre M. Amory and\n                  C{\\'{e}}sar A. M. Marcon and\n                  Fernando Gehm Moraes and\n                  Marcelo Lubaszewski},\n  title        = {Task mapping on NoC-based MPSoCs with faulty tiles: Evaluating the\n                  energy consumption and the application execution time},\n  booktitle    = {Proceedings of the 22nd {IEEE} International Symposium on Rapid System\n                  Prototyping, {RSP} 2011, Karlsruhe, Germany, 24-27 May, 2011},\n  pages        = {164--170},\n  publisher    = {{IEEE}},\n  year         = {2011},\n  url          = {https://doi.org/10.1109/RSP.2011.5929991},\n  doi          = {10.1109/RSP.2011.5929991},\n  timestamp    = {Thu, 14 Oct 2021 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/conf/rsp/AmoryMML11.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Arbitration and routing impact on NoC design.\n \n \n \n \n\n\n \n Moreno, E. I.; Marcon, C. A. M.; Calazans, N. L. V.; and Moraes, F. G.\n\n\n \n\n\n\n In Proceedings of the 22nd IEEE International Symposium on Rapid System Prototyping, RSP 2011, Karlsruhe, Germany, 24-27 May, 2011, pages 193–198, 2011. IEEE\n \n\n\n\n
\n\n\n\n \n \n \"ArbitrationPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/rsp/MorenoMCM11,\n  author       = {Edson I. Moreno and\n                  C{\\'{e}}sar A. M. Marcon and\n                  Ney Laert Vilar Calazans and\n                  Fernando Gehm Moraes},\n  title        = {Arbitration and routing impact on NoC design},\n  booktitle    = {Proceedings of the 22nd {IEEE} International Symposium on Rapid System\n                  Prototyping, {RSP} 2011, Karlsruhe, Germany, 24-27 May, 2011},\n  pages        = {193--198},\n  publisher    = {{IEEE}},\n  year         = {2011},\n  url          = {https://doi.org/10.1109/RSP.2011.5929995},\n  doi          = {10.1109/RSP.2011.5929995},\n  timestamp    = {Sun, 02 Oct 2022 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/conf/rsp/MorenoMCM11.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Early estimation of wire length for dedicated test access mechanisms in networks-on-chip based SoCs.\n \n \n \n \n\n\n \n Amory, A. M.; Lazzari, C.; Lubaszewski, M.; and Moraes, F. G.\n\n\n \n\n\n\n In Cavalcanti, A. C.; Melcher, E. U. K.; and Becker, J., editor(s), 24th Symposium on Integrated Circuits and Systems Design, SBCCI '11, João Pessoa, Brazil, August 30 - September 2, 2011, pages 73–78, 2011. ACM\n \n\n\n\n
\n\n\n\n \n \n \"EarlyPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/sbcci/AmoryLLM11,\n  author       = {Alexandre M. Amory and\n                  Cristiano Lazzari and\n                  Marcelo Lubaszewski and\n                  Fernando Gehm Moraes},\n  editor       = {Antonio Carlos Cavalcanti and\n                  Elmar U. K. Melcher and\n                  J{\\"{u}}rgen Becker},\n  title        = {Early estimation of wire length for dedicated test access mechanisms\n                  in networks-on-chip based SoCs},\n  booktitle    = {24th Symposium on Integrated Circuits and Systems Design, {SBCCI}\n                  '11, Jo{\\~{a}}o Pessoa, Brazil, August 30 - September 2, 2011},\n  pages        = {73--78},\n  publisher    = {{ACM}},\n  year         = {2011},\n  url          = {https://doi.org/10.1145/2020876.2020894},\n  doi          = {10.1145/2020876.2020894},\n  timestamp    = {Wed, 25 Sep 2019 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/conf/sbcci/AmoryLLM11.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Exploring dynamic mapping impact on NoC-based MPSoCs performance using a model-based framework.\n \n \n \n \n\n\n \n Ost, L.; Mandelli, M.; Almeida, G. M.; Indrusiak, L. S.; Möller, L.; Glesner, M.; Sassatelli, G.; Robert, M.; and Moraes, F.\n\n\n \n\n\n\n In Cavalcanti, A. C.; Melcher, E. U. K.; and Becker, J., editor(s), 24th Symposium on Integrated Circuits and Systems Design, SBCCI '11, João Pessoa, Brazil, August 30 - September 2, 2011, pages 185–190, 2011. ACM\n \n\n\n\n
\n\n\n\n \n \n \"ExploringPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
\n
@inproceedings{DBLP:conf/sbcci/OstMAIMGSRM11,\n  author       = {Luciano Ost and\n                  Marcelo Mandelli and\n                  Gabriel Marchesan Almeida and\n                  Leandro Soares Indrusiak and\n                  Leandro M{\\"{o}}ller and\n                  Manfred Glesner and\n                  Gilles Sassatelli and\n                  Michel Robert and\n                  Fernando Moraes},\n  editor       = {Antonio Carlos Cavalcanti and\n                  Elmar U. K. Melcher and\n                  J{\\"{u}}rgen Becker},\n  title        = {Exploring dynamic mapping impact on NoC-based MPSoCs performance using\n                  a model-based framework},\n  booktitle    = {24th Symposium on Integrated Circuits and Systems Design, {SBCCI}\n                  '11, Jo{\\~{a}}o Pessoa, Brazil, August 30 - September 2, 2011},\n  pages        = {185--190},\n  publisher    = {{ACM}},\n  year         = {2011},\n  url          = {https://doi.org/10.1145/2020876.2020919},\n  doi          = {10.1145/2020876.2020919},\n  timestamp    = {Sun, 02 Oct 2022 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/conf/sbcci/OstMAIMGSRM11.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Multi-task dynamic mapping onto NoC-based MPSoCs.\n \n \n \n \n\n\n \n Mandelli, M.; Amory, A. M.; Ost, L.; and Moraes, F. G.\n\n\n \n\n\n\n In Cavalcanti, A. C.; Melcher, E. U. K.; and Becker, J., editor(s), 24th Symposium on Integrated Circuits and Systems Design, SBCCI '11, João Pessoa, Brazil, August 30 - September 2, 2011, pages 191–196, 2011. ACM\n \n\n\n\n
\n\n\n\n \n \n \"Multi-taskPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/sbcci/MandelliAOM11,\n  author       = {Marcelo Mandelli and\n                  Alexandre M. Amory and\n                  Luciano Ost and\n                  Fernando Gehm Moraes},\n  editor       = {Antonio Carlos Cavalcanti and\n                  Elmar U. K. Melcher and\n                  J{\\"{u}}rgen Becker},\n  title        = {Multi-task dynamic mapping onto NoC-based MPSoCs},\n  booktitle    = {24th Symposium on Integrated Circuits and Systems Design, {SBCCI}\n                  '11, Jo{\\~{a}}o Pessoa, Brazil, August 30 - September 2, 2011},\n  pages        = {191--196},\n  publisher    = {{ACM}},\n  year         = {2011},\n  url          = {https://doi.org/10.1145/2020876.2020920},\n  doi          = {10.1145/2020876.2020920},\n  timestamp    = {Sun, 02 Oct 2022 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/conf/sbcci/MandelliAOM11.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n A self-adaptable distributed DFS scheme for NoC-based MPSoCs.\n \n \n \n \n\n\n \n da Rosa, T. R.; Guindani, G. M.; de O. Cardoso, D.; Calazans, N. L. V.; and Moraes, F. G.\n\n\n \n\n\n\n In Cavalcanti, A. C.; Melcher, E. U. K.; and Becker, J., editor(s), 24th Symposium on Integrated Circuits and Systems Design, SBCCI '11, João Pessoa, Brazil, August 30 - September 2, 2011, pages 203–208, 2011. ACM\n \n\n\n\n
\n\n\n\n \n \n \"APaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/sbcci/RosaGCCM11,\n  author       = {Thiago R. da Rosa and\n                  Guilherme Montez Guindani and\n                  Douglas de O. Cardoso and\n                  Ney Laert Vilar Calazans and\n                  Fernando Gehm Moraes},\n  editor       = {Antonio Carlos Cavalcanti and\n                  Elmar U. K. Melcher and\n                  J{\\"{u}}rgen Becker},\n  title        = {A self-adaptable distributed {DFS} scheme for NoC-based MPSoCs},\n  booktitle    = {24th Symposium on Integrated Circuits and Systems Design, {SBCCI}\n                  '11, Jo{\\~{a}}o Pessoa, Brazil, August 30 - September 2, 2011},\n  pages        = {203--208},\n  publisher    = {{ACM}},\n  year         = {2011},\n  url          = {https://doi.org/10.1145/2020876.2020923},\n  doi          = {10.1145/2020876.2020923},\n  timestamp    = {Sun, 02 Oct 2022 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/conf/sbcci/RosaGCCM11.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Energy-efficient cache coherence protocol for NoC-based MPSoCs.\n \n \n \n \n\n\n \n Chaves, T. M.; Carara, E. A.; and Moraes, F. G.\n\n\n \n\n\n\n In Cavalcanti, A. C.; Melcher, E. U. K.; and Becker, J., editor(s), 24th Symposium on Integrated Circuits and Systems Design, SBCCI '11, João Pessoa, Brazil, August 30 - September 2, 2011, pages 215–220, 2011. ACM\n \n\n\n\n
\n\n\n\n \n \n \"Energy-efficientPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/sbcci/ChavesCM11,\n  author       = {Tales Marchesan Chaves and\n                  Everton Alceu Carara and\n                  Fernando Gehm Moraes},\n  editor       = {Antonio Carlos Cavalcanti and\n                  Elmar U. K. Melcher and\n                  J{\\"{u}}rgen Becker},\n  title        = {Energy-efficient cache coherence protocol for NoC-based MPSoCs},\n  booktitle    = {24th Symposium on Integrated Circuits and Systems Design, {SBCCI}\n                  '11, Jo{\\~{a}}o Pessoa, Brazil, August 30 - September 2, 2011},\n  pages        = {215--220},\n  publisher    = {{ACM}},\n  year         = {2011},\n  url          = {https://doi.org/10.1145/2020876.2020925},\n  doi          = {10.1145/2020876.2020925},\n  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},\n  biburl       = {https://dblp.org/rec/conf/sbcci/ChavesCM11.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n  \n 2010\n \n \n (12)\n \n \n
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\n \n\n \n \n \n \n \n \n Dynamic Task Mapping for MPSoCs.\n \n \n \n \n\n\n \n de Souza Carvalho, E. L.; Calazans, N. L. V.; and Moraes, F. G.\n\n\n \n\n\n\n IEEE Des. Test Comput., 27(5): 26–35. 2010.\n \n\n\n\n
\n\n\n\n \n \n \"DynamicPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@article{DBLP:journals/dt/CarvalhoCM10,\n  author       = {Ewerson Luiz de Souza Carvalho and\n                  Ney Laert Vilar Calazans and\n                  Fernando Gehm Moraes},\n  title        = {Dynamic Task Mapping for MPSoCs},\n  journal      = {{IEEE} Des. Test Comput.},\n  volume       = {27},\n  number       = {5},\n  pages        = {26--35},\n  year         = {2010},\n  url          = {https://doi.org/10.1109/MDT.2010.106},\n  doi          = {10.1109/MDT.2010.106},\n  timestamp    = {Sun, 02 Oct 2022 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/journals/dt/CarvalhoCM10.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Joint Validation of Application Models and Multi-Abstraction Network-on-Chip Platforms.\n \n \n \n \n\n\n \n Määttä, S.; Möller, L.; Indrusiak, L. S.; Ost, L.; Glesner, M.; Nurmi, J.; and Moraes, F.\n\n\n \n\n\n\n Int. J. Embed. Real Time Commun. Syst., 1(1): 86–101. 2010.\n \n\n\n\n
\n\n\n\n \n \n \"JointPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@article{DBLP:journals/ijertcs/MaattaMIOGNM10,\n  author       = {Sanna M{\\"{a}}{\\"{a}}tt{\\"{a}} and\n                  Leandro M{\\"{o}}ller and\n                  Leandro Soares Indrusiak and\n                  Luciano Ost and\n                  Manfred Glesner and\n                  Jari Nurmi and\n                  Fernando Moraes},\n  title        = {Joint Validation of Application Models and Multi-Abstraction Network-on-Chip\n                  Platforms},\n  journal      = {Int. J. Embed. Real Time Commun. Syst.},\n  volume       = {1},\n  number       = {1},\n  pages        = {86--101},\n  year         = {2010},\n  url          = {https://doi.org/10.4018/jertcs.2010103005},\n  doi          = {10.4018/JERTCS.2010103005},\n  timestamp    = {Sun, 02 Oct 2022 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/journals/ijertcs/MaattaMIOGNM10.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Improving QoS of Multi-layer Networks-on-Chip with Partial and Dynamic Reconfiguration of Routers.\n \n \n \n \n\n\n \n Möller, L.; Fischer, P.; Moraes, F.; Indrusiak, L. S.; and Glesner, M.\n\n\n \n\n\n\n In International Conference on Field Programmable Logic and Applications, FPL 2010, August 31 2010 - September 2, 2010, Milano, Italy, pages 229–233, 2010. IEEE Computer Society\n \n\n\n\n
\n\n\n\n \n \n \"ImprovingPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/fpl/MollerFMIG10,\n  author       = {Leandro M{\\"{o}}ller and\n                  Peter Fischer and\n                  Fernando Moraes and\n                  Leandro Soares Indrusiak and\n                  Manfred Glesner},\n  title        = {Improving QoS of Multi-layer Networks-on-Chip with Partial and Dynamic\n                  Reconfiguration of Routers},\n  booktitle    = {International Conference on Field Programmable Logic and Applications,\n                  {FPL} 2010, August 31 2010 - September 2, 2010, Milano, Italy},\n  pages        = {229--233},\n  publisher    = {{IEEE} Computer Society},\n  year         = {2010},\n  url          = {https://doi.org/10.1109/FPL.2010.53},\n  doi          = {10.1109/FPL.2010.53},\n  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},\n  biburl       = {https://dblp.org/rec/conf/fpl/MollerFMIG10.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Model-based design flow for NoC-based MPSoCs.\n \n \n \n \n\n\n \n Ost, L.; Indrusiak, L. S.; Määttä, S.; Mandelli, M.; Nurmi, J.; and Moraes, F.\n\n\n \n\n\n\n In 17th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2010, Athens, Greece, 12-15 December, 2010, pages 750–753, 2010. IEEE\n \n\n\n\n
\n\n\n\n \n \n \"Model-basedPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/icecsys/OstIMMNM10,\n  author       = {Luciano Ost and\n                  Leandro Soares Indrusiak and\n                  Sanna M{\\"{a}}{\\"{a}}tt{\\"{a}} and\n                  Marcelo Mandelli and\n                  Jari Nurmi and\n                  Fernando Moraes},\n  title        = {Model-based design flow for NoC-based MPSoCs},\n  booktitle    = {17th {IEEE} International Conference on Electronics, Circuits, and\n                  Systems, {ICECS} 2010, Athens, Greece, 12-15 December, 2010},\n  pages        = {750--753},\n  publisher    = {{IEEE}},\n  year         = {2010},\n  url          = {https://doi.org/10.1109/ICECS.2010.5724621},\n  doi          = {10.1109/ICECS.2010.5724621},\n  timestamp    = {Mon, 03 Jan 2022 00:00:00 +0100},\n  biburl       = {https://dblp.org/rec/conf/icecsys/OstIMMNM10.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n A case study of hierarchically heterogeneous application modelling using UML and Ptolemy II.\n \n \n \n \n\n\n \n Määttä, S.; Indrusiak, L. S.; Ost, L.; Möller, L.; Glesner, M.; Moraes, F. G.; and Nurmi, J.\n\n\n \n\n\n\n In 2010 International Symposium on System on Chip, SoC 2010, Tampere, September 29-30, 2010, pages 68–71, 2010. IEEE\n \n\n\n\n
\n\n\n\n \n \n \"APaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/issoc/MaattaIOMGMN10,\n  author       = {Sanna M{\\"{a}}{\\"{a}}tt{\\"{a}} and\n                  Leandro Soares Indrusiak and\n                  Luciano Ost and\n                  Leandro M{\\"{o}}ller and\n                  Manfred Glesner and\n                  Fernando Gehm Moraes and\n                  Jari Nurmi},\n  title        = {A case study of hierarchically heterogeneous application modelling\n                  using {UML} and Ptolemy {II}},\n  booktitle    = {2010 International Symposium on System on Chip, SoC 2010, Tampere,\n                  September 29-30, 2010},\n  pages        = {68--71},\n  publisher    = {{IEEE}},\n  year         = {2010},\n  url          = {https://doi.org/10.1109/ISSOC.2010.5625554},\n  doi          = {10.1109/ISSOC.2010.5625554},\n  timestamp    = {Mon, 03 Jan 2022 00:00:00 +0100},\n  biburl       = {https://dblp.org/rec/conf/issoc/MaattaIOMGMN10.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n A message-level monitoring protocol for QoS flows in NoCs.\n \n \n \n \n\n\n \n Tedesco, L.; da Rosa, T. R.; and Moraes, F. G.\n\n\n \n\n\n\n In 2010 International Symposium on System on Chip, SoC 2010, Tampere, September 29-30, 2010, pages 84–88, 2010. IEEE\n \n\n\n\n
\n\n\n\n \n \n \"APaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/issoc/TedescoRM10,\n  author       = {Leonel Tedesco and\n                  Thiago R. da Rosa and\n                  Fernando Gehm Moraes},\n  title        = {A message-level monitoring protocol for QoS flows in NoCs},\n  booktitle    = {2010 International Symposium on System on Chip, SoC 2010, Tampere,\n                  September 29-30, 2010},\n  pages        = {84--88},\n  publisher    = {{IEEE}},\n  year         = {2010},\n  url          = {https://doi.org/10.1109/ISSOC.2010.5625541},\n  doi          = {10.1109/ISSOC.2010.5625541},\n  timestamp    = {Mon, 15 Jun 2020 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/conf/issoc/TedescoRM10.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Hermes-A - An Asynchronous NoC Router with Distributed Routing.\n \n \n \n \n\n\n \n Pontes, J. J. H.; Moreira, M. T.; Moraes, F.; and Calazans, N.\n\n\n \n\n\n\n In van Leuken, R.; and Sicard, G., editor(s), Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation - 20th International Workshop, PATMOS 2010, Grenoble, France, September 7-10, 2010, Revised Selected Papers, volume 6448, of Lecture Notes in Computer Science, pages 150–159, 2010. Springer\n \n\n\n\n
\n\n\n\n \n \n \"Hermes-APaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/patmos/PontesMMC10,\n  author       = {Julian J. H. Pontes and\n                  Matheus T. Moreira and\n                  Fernando Moraes and\n                  Ney Calazans},\n  editor       = {Ren{\\'{e}} van Leuken and\n                  Gilles Sicard},\n  title        = {Hermes-A - An Asynchronous NoC Router with Distributed Routing},\n  booktitle    = {Integrated Circuit and System Design. Power and Timing Modeling, Optimization,\n                  and Simulation - 20th International Workshop, {PATMOS} 2010, Grenoble,\n                  France, September 7-10, 2010, Revised Selected Papers},\n  series       = {Lecture Notes in Computer Science},\n  volume       = {6448},\n  pages        = {150--159},\n  publisher    = {Springer},\n  year         = {2010},\n  url          = {https://doi.org/10.1007/978-3-642-17752-1\\_15},\n  doi          = {10.1007/978-3-642-17752-1\\_15},\n  timestamp    = {Tue, 13 Sep 2022 21:45:42 +0200},\n  biburl       = {https://dblp.org/rec/conf/patmos/PontesMMC10.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n Instruction Set Simulator for MPSoCs based on NoCs and MIPS Processors.\n \n \n \n\n\n \n Möller, L.; Rodrigues, A.; Moraes, F.; Indrusiak, L. S.; and Glesner, M.\n\n\n \n\n\n\n In Hübner, M.; Lagadec, L.; Sander, O.; and Becker, J., editor(s), Proceedings of the 5th International Workshop on Reconfigurable Communication-centric Systems on Chip, ReCoSoC 2010, Karlsruhe, Germany, May 17-19, 2010, volume 7551, of KIT Scientific Reports, pages 7–11, 2010. KIT Scientific Publishing\n \n\n\n\n
\n\n\n\n \n\n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/recosoc/MollerRMIG10,\n  author       = {Leandro M{\\"{o}}ller and\n                  Andr{\\'{e}} Rodrigues and\n                  Fernando Moraes and\n                  Leandro Soares Indrusiak and\n                  Manfred Glesner},\n  editor       = {Michael H{\\"{u}}bner and\n                  Lo{\\"{\\i}}c Lagadec and\n                  Oliver Sander and\n                  J{\\"{u}}rgen Becker},\n  title        = {Instruction Set Simulator for MPSoCs based on NoCs and {MIPS} Processors},\n  booktitle    = {Proceedings of the 5th International Workshop on Reconfigurable Communication-centric\n                  Systems on Chip, ReCoSoC 2010, Karlsruhe, Germany, May 17-19, 2010},\n  series       = {{KIT} Scientific Reports},\n  volume       = {7551},\n  pages        = {7--11},\n  publisher    = {{KIT} Scientific Publishing},\n  year         = {2010},\n  timestamp    = {Thu, 29 Apr 2021 08:19:40 +0200},\n  biburl       = {https://dblp.org/rec/conf/recosoc/MollerRMIG10.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Evaluating the impact of task migration in multi-processor systems-on-chip.\n \n \n \n \n\n\n \n Almeida, G. M.; Varyani, S.; Busseuil, R.; Sassatelli, G.; Benoit, P.; Torres, L.; Carara, E.; and Moraes, F. G.\n\n\n \n\n\n\n In Martino, J. A.; Araujo, G.; Orailoglu, A.; and Klein, F., editor(s), Proceedings of the 23rd Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2010, São Paulo, Brazil, September 6-9, 2010, pages 73–78, 2010. ACM\n \n\n\n\n
\n\n\n\n \n \n \"EvaluatingPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/sbcci/AlmeidaVBSBTCM10,\n  author       = {Gabriel Marchesan Almeida and\n                  Sameer Varyani and\n                  R{\\'{e}}mi Busseuil and\n                  Gilles Sassatelli and\n                  Pascal Benoit and\n                  Lionel Torres and\n                  Everton Carara and\n                  Fernando Gehm Moraes},\n  editor       = {Jo{\\~{a}}o Antonio Martino and\n                  Guido Araujo and\n                  Alex Orailoglu and\n                  Felipe Klein},\n  title        = {Evaluating the impact of task migration in multi-processor systems-on-chip},\n  booktitle    = {Proceedings of the 23rd Annual Symposium on Integrated Circuits and\n                  Systems Design, {SBCCI} 2010, S{\\~{a}}o Paulo, Brazil, September 6-9,\n                  2010},\n  pages        = {73--78},\n  publisher    = {{ACM}},\n  year         = {2010},\n  url          = {https://doi.org/10.1145/1854153.1854174},\n  doi          = {10.1145/1854153.1854174},\n  timestamp    = {Sun, 02 Oct 2022 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/conf/sbcci/AlmeidaVBSBTCM10.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Implementation and evaluation of a congestion aware routing algorithm for networks-on-chip.\n \n \n \n \n\n\n \n Tedesco, L.; da Rosa, T. R.; Clermidy, F.; Calazans, N.; and Moraes, F. G.\n\n\n \n\n\n\n In Martino, J. A.; Araujo, G.; Orailoglu, A.; and Klein, F., editor(s), Proceedings of the 23rd Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2010, São Paulo, Brazil, September 6-9, 2010, pages 91–96, 2010. ACM\n \n\n\n\n
\n\n\n\n \n \n \"ImplementationPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/sbcci/TedescoRCCM10,\n  author       = {Leonel Tedesco and\n                  Thiago R. da Rosa and\n                  Fabien Clermidy and\n                  Ney Calazans and\n                  Fernando Gehm Moraes},\n  editor       = {Jo{\\~{a}}o Antonio Martino and\n                  Guido Araujo and\n                  Alex Orailoglu and\n                  Felipe Klein},\n  title        = {Implementation and evaluation of a congestion aware routing algorithm\n                  for networks-on-chip},\n  booktitle    = {Proceedings of the 23rd Annual Symposium on Integrated Circuits and\n                  Systems Design, {SBCCI} 2010, S{\\~{a}}o Paulo, Brazil, September 6-9,\n                  2010},\n  pages        = {91--96},\n  publisher    = {{ACM}},\n  year         = {2010},\n  url          = {https://doi.org/10.1145/1854153.1854178},\n  doi          = {10.1145/1854153.1854178},\n  timestamp    = {Sun, 02 Oct 2022 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/conf/sbcci/TedescoRCCM10.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Flow oriented routing for NOCS.\n \n \n \n \n\n\n \n Carara, E.; and Moraes, F.\n\n\n \n\n\n\n In Büchner, T.; Sridhar, R.; Marshall, A.; and Schuhmann, N., editor(s), Annual IEEE International SoC Conference, SoCC 2010, September 27-29, 2010, Las Vegas, NV, USA, Proceedings, pages 367–370, 2010. IEEE\n \n\n\n\n
\n\n\n\n \n \n \"FlowPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/socc/CararaM10,\n  author       = {Everton Carara and\n                  Fernando Moraes},\n  editor       = {Thomas B{\\"{u}}chner and\n                  Ramalingam Sridhar and\n                  Andrew Marshall and\n                  Norbert Schuhmann},\n  title        = {Flow oriented routing for {NOCS}},\n  booktitle    = {Annual {IEEE} International SoC Conference, SoCC 2010, September 27-29,\n                  2010, Las Vegas, NV, USA, Proceedings},\n  pages        = {367--370},\n  publisher    = {{IEEE}},\n  year         = {2010},\n  url          = {https://doi.org/10.1109/SOCC.2010.5784697},\n  doi          = {10.1109/SOCC.2010.5784697},\n  timestamp    = {Tue, 10 Mar 2020 00:00:00 +0100},\n  biburl       = {https://dblp.org/rec/conf/socc/CararaM10.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Hermes-AA: A 65nm asynchronous NoC router with adaptive routing.\n \n \n \n \n\n\n \n Pontes, J. J. H.; Moreira, M. T.; Moraes, F.; and Calazans, N.\n\n\n \n\n\n\n In Büchner, T.; Sridhar, R.; Marshall, A.; and Schuhmann, N., editor(s), Annual IEEE International SoC Conference, SoCC 2010, September 27-29, 2010, Las Vegas, NV, USA, Proceedings, pages 493–498, 2010. IEEE\n \n\n\n\n
\n\n\n\n \n \n \"Hermes-AA:Paper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/socc/PontesMMC10,\n  author       = {Julian J. H. Pontes and\n                  Matheus T. Moreira and\n                  Fernando Moraes and\n                  Ney Calazans},\n  editor       = {Thomas B{\\"{u}}chner and\n                  Ramalingam Sridhar and\n                  Andrew Marshall and\n                  Norbert Schuhmann},\n  title        = {Hermes-AA: {A} 65nm asynchronous NoC router with adaptive routing},\n  booktitle    = {Annual {IEEE} International SoC Conference, SoCC 2010, September 27-29,\n                  2010, Las Vegas, NV, USA, Proceedings},\n  pages        = {493--498},\n  publisher    = {{IEEE}},\n  year         = {2010},\n  url          = {https://doi.org/10.1109/SOCC.2010.5784676},\n  doi          = {10.1109/SOCC.2010.5784676},\n  timestamp    = {Sun, 02 Oct 2022 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/conf/socc/PontesMMC10.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n  \n 2009\n \n \n (10)\n \n \n
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\n \n\n \n \n \n \n \n \n A monitoring and adaptive routing mechanism for QoS traffic on mesh NoC architectures.\n \n \n \n \n\n\n \n Tedesco, L.; Clermidy, F.; and Moraes, F.\n\n\n \n\n\n\n In Rosenstiel, W.; and Wakabayashi, K., editor(s), Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2009, Grenoble, France, October 11-16, 2009, pages 109–118, 2009. ACM\n \n\n\n\n
\n\n\n\n \n \n \"APaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/codes/TedescoCM09,\n  author       = {Leonel Tedesco and\n                  Fabien Clermidy and\n                  Fernando Moraes},\n  editor       = {Wolfgang Rosenstiel and\n                  Kazutoshi Wakabayashi},\n  title        = {A monitoring and adaptive routing mechanism for QoS traffic on mesh\n                  NoC architectures},\n  booktitle    = {Proceedings of the 7th International Conference on Hardware/Software\n                  Codesign and System Synthesis, {CODES+ISSS} 2009, Grenoble, France,\n                  October 11-16, 2009},\n  pages        = {109--118},\n  publisher    = {{ACM}},\n  year         = {2009},\n  url          = {https://doi.org/10.1145/1629435.1629451},\n  doi          = {10.1145/1629435.1629451},\n  timestamp    = {Sun, 02 Oct 2022 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/conf/codes/TedescoCM09.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n HeMPS - a Framework for NoC-based MPSoC Generation.\n \n \n \n \n\n\n \n Carara, E.; de Oliveira, R. P.; Calazans, N. L. V.; and Moraes, F. G.\n\n\n \n\n\n\n In International Symposium on Circuits and Systems (ISCAS 2009), 24-17 May 2009, Taipei, Taiwan, pages 1345–1348, 2009. IEEE\n \n\n\n\n
\n\n\n\n \n \n \"HeMPSPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/iscas/CararaOCM09,\n  author       = {Everton Carara and\n                  Roberto P. de Oliveira and\n                  Ney Laert Vilar Calazans and\n                  Fernando Gehm Moraes},\n  title        = {HeMPS - a Framework for NoC-based MPSoC Generation},\n  booktitle    = {International Symposium on Circuits and Systems {(ISCAS} 2009), 24-17\n                  May 2009, Taipei, Taiwan},\n  pages        = {1345--1348},\n  publisher    = {{IEEE}},\n  year         = {2009},\n  url          = {https://doi.org/10.1109/ISCAS.2009.5118013},\n  doi          = {10.1109/ISCAS.2009.5118013},\n  timestamp    = {Sun, 02 Oct 2022 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/conf/iscas/CararaOCM09.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Evaluation of static and dynamic task mapping algorithms in NoC-based MPSoCs.\n \n \n \n \n\n\n \n Carvalho, E.; Marcon, C. A. M.; Calazans, N.; and Moraes, F.\n\n\n \n\n\n\n In 2008 IEEE International Symposium on System-on-Chip, SOC 2009, Tampere, Finland, October 6-7, 2008, pages 87–90, 2009. IEEE\n \n\n\n\n
\n\n\n\n \n \n \"EvaluationPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/issoc/CarvalhoMCM09,\n  author       = {Ewerson Carvalho and\n                  C{\\'{e}}sar A. M. Marcon and\n                  Ney Calazans and\n                  Fernando Moraes},\n  title        = {Evaluation of static and dynamic task mapping algorithms in NoC-based\n                  MPSoCs},\n  booktitle    = {2008 {IEEE} International Symposium on System-on-Chip, {SOC} 2009,\n                  Tampere, Finland, October 6-7, 2008},\n  pages        = {87--90},\n  publisher    = {{IEEE}},\n  year         = {2009},\n  url          = {https://doi.org/10.1109/SOCC.2009.5335672},\n  doi          = {10.1109/SOCC.2009.5335672},\n  timestamp    = {Sun, 02 Oct 2022 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/conf/issoc/CarvalhoMCM09.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Characterising embedded applications using a UML profile.\n \n \n \n \n\n\n \n Määttä, S.; Indrusiak, L. S.; Ost, L.; Möller, L.; Glesner, M.; Moraes, F. G.; and Nurmi, J.\n\n\n \n\n\n\n In 2008 IEEE International Symposium on System-on-Chip, SOC 2009, Tampere, Finland, October 6-7, 2008, pages 172–175, 2009. IEEE\n \n\n\n\n
\n\n\n\n \n \n \"CharacterisingPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/issoc/MaattaIOMGMN09,\n  author       = {Sanna M{\\"{a}}{\\"{a}}tt{\\"{a}} and\n                  Leandro Soares Indrusiak and\n                  Luciano Ost and\n                  Leandro M{\\"{o}}ller and\n                  Manfred Glesner and\n                  Fernando Gehm Moraes and\n                  Jari Nurmi},\n  title        = {Characterising embedded applications using a {UML} profile},\n  booktitle    = {2008 {IEEE} International Symposium on System-on-Chip, {SOC} 2009,\n                  Tampere, Finland, October 6-7, 2008},\n  pages        = {172--175},\n  publisher    = {{IEEE}},\n  year         = {2009},\n  url          = {https://doi.org/10.1109/SOCC.2009.5335654},\n  doi          = {10.1109/SOCC.2009.5335654},\n  timestamp    = {Mon, 03 Jan 2022 00:00:00 +0100},\n  biburl       = {https://dblp.org/rec/conf/issoc/MaattaIOMGMN09.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Increasing NoC power estimation accuracy through a rate-based model.\n \n \n \n \n\n\n \n Guindani, G. M.; Reinbrecht, C.; da Rosa, T. R.; and Moraes, F.\n\n\n \n\n\n\n In Third International Symposium on Networks-on-Chips, NOCS 2009, May 10-13 2009, La Jolla, CA, USA. Proceedings, pages 89, 2009. IEEE Computer Society\n \n\n\n\n
\n\n\n\n \n \n \"IncreasingPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
\n
@inproceedings{DBLP:conf/nocs/GuindaniRRM09,\n  author       = {Guilherme Montez Guindani and\n                  Cezar Reinbrecht and\n                  Thiago R. da Rosa and\n                  Fernando Moraes},\n  title        = {Increasing NoC power estimation accuracy through a rate-based model},\n  booktitle    = {Third International Symposium on Networks-on-Chips, {NOCS} 2009, May\n                  10-13 2009, La Jolla, CA, {USA.} Proceedings},\n  pages        = {89},\n  publisher    = {{IEEE} Computer Society},\n  year         = {2009},\n  url          = {https://doi.org/10.1109/NOCS.2009.5071452},\n  doi          = {10.1109/NOCS.2009.5071452},\n  timestamp    = {Thu, 23 Mar 2023 00:00:00 +0100},\n  biburl       = {https://dblp.org/rec/conf/nocs/GuindaniRRM09.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Floating Point Hardware for Embedded Processors in FPGAs: Design Space Exploration for Performance and Area.\n \n \n \n \n\n\n \n Rodolfo, T. A.; Calazans, N. L. V.; and Moraes, F. G.\n\n\n \n\n\n\n In Prasanna, V. K.; Torres, L.; and Cumplido, R., editor(s), ReConFig'09: 2009 International Conference on Reconfigurable Computing and FPGAs, Cancun, Quintana Roo, Mexico, 9-11 December 2009, Proceedings, pages 24–29, 2009. IEEE Computer Society\n \n\n\n\n
\n\n\n\n \n \n \"FloatingPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
\n
@inproceedings{DBLP:conf/reconfig/RodolfoCM09,\n  author       = {Taciano A. Rodolfo and\n                  Ney Laert Vilar Calazans and\n                  Fernando Gehm Moraes},\n  editor       = {Viktor K. Prasanna and\n                  Lionel Torres and\n                  Ren{\\'{e}} Cumplido},\n  title        = {Floating Point Hardware for Embedded Processors in FPGAs: Design Space\n                  Exploration for Performance and Area},\n  booktitle    = {ReConFig'09: 2009 International Conference on Reconfigurable Computing\n                  and FPGAs, Cancun, Quintana Roo, Mexico, 9-11 December 2009, Proceedings},\n  pages        = {24--29},\n  publisher    = {{IEEE} Computer Society},\n  year         = {2009},\n  url          = {https://doi.org/10.1109/ReConFig.2009.26},\n  doi          = {10.1109/RECONFIG.2009.26},\n  timestamp    = {Thu, 23 Mar 2023 00:00:00 +0100},\n  biburl       = {https://dblp.org/rec/conf/reconfig/RodolfoCM09.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n A 10 Gbps OTN Framer Implementation Targeting FPGA Devices.\n \n \n \n \n\n\n \n Guindani, G. M.; Ferlini, F.; Oliveira, J.; Calazans, N. L. V.; Pigatto, D. V.; and Moraes, F. G.\n\n\n \n\n\n\n In Prasanna, V. K.; Torres, L.; and Cumplido, R., editor(s), ReConFig'09: 2009 International Conference on Reconfigurable Computing and FPGAs, Cancun, Quintana Roo, Mexico, 9-11 December 2009, Proceedings, pages 30–35, 2009. IEEE Computer Society\n \n\n\n\n
\n\n\n\n \n \n \"APaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/reconfig/GuindaniFOCPM09,\n  author       = {Guilherme Montez Guindani and\n                  Frederico Ferlini and\n                  Jeferson Oliveira and\n                  Ney Laert Vilar Calazans and\n                  Daniel V. Pigatto and\n                  Fernando Gehm Moraes},\n  editor       = {Viktor K. Prasanna and\n                  Lionel Torres and\n                  Ren{\\'{e}} Cumplido},\n  title        = {A 10 Gbps {OTN} Framer Implementation Targeting {FPGA} Devices},\n  booktitle    = {ReConFig'09: 2009 International Conference on Reconfigurable Computing\n                  and FPGAs, Cancun, Quintana Roo, Mexico, 9-11 December 2009, Proceedings},\n  pages        = {30--35},\n  publisher    = {{IEEE} Computer Society},\n  year         = {2009},\n  url          = {https://doi.org/10.1109/ReConFig.2009.27},\n  doi          = {10.1109/RECONFIG.2009.27},\n  timestamp    = {Thu, 23 Mar 2023 00:00:00 +0100},\n  biburl       = {https://dblp.org/rec/conf/reconfig/GuindaniFOCPM09.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n A high abstraction, high accuracy power estimation model for networks-on-chip.\n \n \n \n \n\n\n \n Ost, L.; Guindani, G. M.; Indrusiak, L. S.; Reinbrecht, C.; da Rosa, T. R.; and Moraes, F.\n\n\n \n\n\n\n In Silva, I. S.; Ribas, R. P.; and Plett, C., editor(s), Proceedings of the 22st Annual Symposium on Integrated Circuits and Systems Design: Chip on the Dunes, SBCCI 2009, Natal, Brazil, August 31 - September 3, 2009, 2009. ACM\n \n\n\n\n
\n\n\n\n \n \n \"APaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/sbcci/OstGIRRM09,\n  author       = {Luciano Ost and\n                  Guilherme Montez Guindani and\n                  Leandro Soares Indrusiak and\n                  Cezar Reinbrecht and\n                  Thiago Raupp da Rosa and\n                  Fernando Moraes},\n  editor       = {Ivan Saraiva Silva and\n                  Renato P. Ribas and\n                  Calvin Plett},\n  title        = {A high abstraction, high accuracy power estimation model for networks-on-chip},\n  booktitle    = {Proceedings of the 22st Annual Symposium on Integrated Circuits and\n                  Systems Design: Chip on the Dunes, {SBCCI} 2009, Natal, Brazil, August\n                  31 - September 3, 2009},\n  publisher    = {{ACM}},\n  year         = {2009},\n  url          = {https://doi.org/10.1145/1601896.1601936},\n  doi          = {10.1145/1601896.1601936},\n  timestamp    = {Sun, 02 Oct 2022 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/conf/sbcci/OstGIRRM09.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n A path-load based adaptive routing algorithm for networks-on-chip.\n \n \n \n \n\n\n \n Tedesco, L.; Clermidy, F.; and Moraes, F.\n\n\n \n\n\n\n In Silva, I. S.; Ribas, R. P.; and Plett, C., editor(s), Proceedings of the 22st Annual Symposium on Integrated Circuits and Systems Design: Chip on the Dunes, SBCCI 2009, Natal, Brazil, August 31 - September 3, 2009, 2009. ACM\n \n\n\n\n
\n\n\n\n \n \n \"APaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/sbcci/TedescoCM09,\n  author       = {Leonel Tedesco and\n                  Fabien Clermidy and\n                  Fernando Moraes},\n  editor       = {Ivan Saraiva Silva and\n                  Renato P. Ribas and\n                  Calvin Plett},\n  title        = {A path-load based adaptive routing algorithm for networks-on-chip},\n  booktitle    = {Proceedings of the 22st Annual Symposium on Integrated Circuits and\n                  Systems Design: Chip on the Dunes, {SBCCI} 2009, Natal, Brazil, August\n                  31 - September 3, 2009},\n  publisher    = {{ACM}},\n  year         = {2009},\n  url          = {https://doi.org/10.1145/1601896.1601926},\n  doi          = {10.1145/1601896.1601926},\n  timestamp    = {Sun, 02 Oct 2022 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/conf/sbcci/TedescoCM09.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Crosstalk Fault Tolerant NoC: Design and Evaluation.\n \n \n \n \n\n\n \n da Silva, A. H. L.; Amory, A. M.; and Moraes, F. G.\n\n\n \n\n\n\n In Becker, J.; Johann, M. O.; and Reis, R., editor(s), VLSI-SoC: Technologies for Systems Integration - 17th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2009, Florianópolis, Brazil, October 12-14, 2009, Revised Selected Papers, volume 360, of IFIP Advances in Information and Communication Technology, pages 81–93, 2009. Springer\n \n\n\n\n
\n\n\n\n \n \n \"CrosstalkPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/vlsi/LucasAM09,\n  author       = {Alzemiro Henrique Lucas da Silva and\n                  Alexandre M. Amory and\n                  Fernando Gehm Moraes},\n  editor       = {J{\\"{u}}rgen Becker and\n                  Marcelo O. Johann and\n                  Ricardo Reis},\n  title        = {Crosstalk Fault Tolerant NoC: Design and Evaluation},\n  booktitle    = {VLSI-SoC: Technologies for Systems Integration - 17th {IFIP} {WG}\n                  10.5/IEEE International Conference on Very Large Scale Integration,\n                  VLSI-SoC 2009, Florian{\\'{o}}polis, Brazil, October 12-14, 2009, Revised\n                  Selected Papers},\n  series       = {{IFIP} Advances in Information and Communication Technology},\n  volume       = {360},\n  pages        = {81--93},\n  publisher    = {Springer},\n  year         = {2009},\n  url          = {https://doi.org/10.1007/978-3-642-23120-9\\_5},\n  doi          = {10.1007/978-3-642-23120-9\\_5},\n  timestamp    = {Tue, 22 Oct 2019 15:21:19 +0200},\n  biburl       = {https://dblp.org/rec/conf/vlsi/LucasAM09.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n  \n 2008\n \n \n (8)\n \n \n
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\n \n\n \n \n \n \n \n \n Comparison of network-on-chip mapping algorithms targeting low energy consumption.\n \n \n \n \n\n\n \n Marcon, C. A. M.; Moreno, E. I.; Calazans, N. L. V.; and Moraes, F. G.\n\n\n \n\n\n\n IET Comput. Digit. Tech., 2(6): 471–482. 2008.\n \n\n\n\n
\n\n\n\n \n \n \"ComparisonPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@article{DBLP:journals/iet-cdt/MarconMCM08,\n  author       = {C{\\'{e}}sar Augusto Missio Marcon and\n                  Edson Ifarraguirre Moreno and\n                  Ney Laert Vilar Calazans and\n                  Fernando Gehm Moraes},\n  title        = {Comparison of network-on-chip mapping algorithms targeting low energy\n                  consumption},\n  journal      = {{IET} Comput. Digit. Tech.},\n  volume       = {2},\n  number       = {6},\n  pages        = {471--482},\n  year         = {2008},\n  url          = {https://doi.org/10.1049/iet-cdt:20070111},\n  doi          = {10.1049/IET-CDT:20070111},\n  timestamp    = {Sun, 02 Oct 2022 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/journals/iet-cdt/MarconMCM08.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Congestion-aware task mapping in heterogeneous MPSoCs.\n \n \n \n \n\n\n \n Carvalho, E.; and Moraes, F.\n\n\n \n\n\n\n In 2008 IEEE International Symposium on System-on-Chip, SOC 2008, Tampere, Finland, November 5-6, 2008, pages 1–4, 2008. IEEE\n \n\n\n\n
\n\n\n\n \n \n \"Congestion-awarePaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/issoc/CarvalhoM08,\n  author       = {Ewerson Carvalho and\n                  Fernando Moraes},\n  title        = {Congestion-aware task mapping in heterogeneous MPSoCs},\n  booktitle    = {2008 {IEEE} International Symposium on System-on-Chip, {SOC} 2008,\n                  Tampere, Finland, November 5-6, 2008},\n  pages        = {1--4},\n  publisher    = {{IEEE}},\n  year         = {2008},\n  url          = {https://doi.org/10.1109/ISSOC.2008.4694878},\n  doi          = {10.1109/ISSOC.2008.4694878},\n  timestamp    = {Mon, 09 Aug 2021 14:54:02 +0200},\n  biburl       = {https://dblp.org/rec/conf/issoc/CarvalhoM08.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Deadlock-Free Multicast Routing Algorithm for Wormhole-Switched Mesh Networks-on-Chip.\n \n \n \n \n\n\n \n Carara, E.; and Moraes, F. G.\n\n\n \n\n\n\n In IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2008, 7-9 April 2008, Montpellier, France, pages 341–346, 2008. IEEE Computer Society\n \n\n\n\n
\n\n\n\n \n \n \"Deadlock-FreePaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/isvlsi/CararaM08,\n  author       = {Everton Carara and\n                  Fernando Gehm Moraes},\n  title        = {Deadlock-Free Multicast Routing Algorithm for Wormhole-Switched Mesh\n                  Networks-on-Chip},\n  booktitle    = {{IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2008, 7-9\n                  April 2008, Montpellier, France},\n  pages        = {341--346},\n  publisher    = {{IEEE} Computer Society},\n  year         = {2008},\n  url          = {https://doi.org/10.1109/ISVLSI.2008.18},\n  doi          = {10.1109/ISVLSI.2008.18},\n  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},\n  biburl       = {https://dblp.org/rec/conf/isvlsi/CararaM08.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n NoC Power Estimation at the RTL Abstraction Level.\n \n \n \n \n\n\n \n Guindani, G. M.; Reinbrecht, C.; da Rosa, T. R.; Calazans, N.; and Moraes, F. G.\n\n\n \n\n\n\n In IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2008, 7-9 April 2008, Montpellier, France, pages 475–478, 2008. IEEE Computer Society\n \n\n\n\n
\n\n\n\n \n \n \"NoCPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/isvlsi/GuindaniRRCM08,\n  author       = {Guilherme Montez Guindani and\n                  Cezar Reinbrecht and\n                  Thiago Raupp da Rosa and\n                  Ney Calazans and\n                  Fernando Gehm Moraes},\n  title        = {NoC Power Estimation at the {RTL} Abstraction Level},\n  booktitle    = {{IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2008, 7-9\n                  April 2008, Montpellier, France},\n  pages        = {475--478},\n  publisher    = {{IEEE} Computer Society},\n  year         = {2008},\n  url          = {https://doi.org/10.1109/ISVLSI.2008.17},\n  doi          = {10.1109/ISVLSI.2008.17},\n  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},\n  biburl       = {https://dblp.org/rec/conf/isvlsi/GuindaniRRCM08.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Applying UML Interactions and Actor-Oriented Simulation to the Design Space Exploration of Network-on-Chip Interconnects.\n \n \n \n \n\n\n \n Indrusiak, L. S.; Ost, L.; Möller, L.; Moraes, F.; and Glesner, M.\n\n\n \n\n\n\n In IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2008, 7-9 April 2008, Montpellier, France, pages 491–494, 2008. IEEE Computer Society\n \n\n\n\n
\n\n\n\n \n \n \"ApplyingPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/isvlsi/IndrusiakOMMG08,\n  author       = {Leandro Soares Indrusiak and\n                  Luciano Ost and\n                  Leandro M{\\"{o}}ller and\n                  Fernando Moraes and\n                  Manfred Glesner},\n  title        = {Applying {UML} Interactions and Actor-Oriented Simulation to the Design\n                  Space Exploration of Network-on-Chip Interconnects},\n  booktitle    = {{IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2008, 7-9\n                  April 2008, Montpellier, France},\n  pages        = {491--494},\n  publisher    = {{IEEE} Computer Society},\n  year         = {2008},\n  url          = {https://doi.org/10.1109/ISVLSI.2008.20},\n  doi          = {10.1109/ISVLSI.2008.20},\n  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},\n  biburl       = {https://dblp.org/rec/conf/isvlsi/IndrusiakOMMG08.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n A simplified executable model to evaluate latency and throughput of networks-on-chip.\n \n \n \n \n\n\n \n Ost, L.; Moraes, F. G.; Möller, L.; Indrusiak, L. S.; Glesner, M.; Määttä, S.; and Nurmi, J.\n\n\n \n\n\n\n In Lubaszewski, M.; Renovell, M.; and Gupta, R. K., editor(s), Proceedings of the 21st Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2008, Gramado, Brazil, September 1-4, 2008, pages 170–175, 2008. ACM\n \n\n\n\n
\n\n\n\n \n \n \"APaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/sbcci/OstMMIGMN08,\n  author       = {Luciano Ost and\n                  Fernando Gehm Moraes and\n                  Leandro M{\\"{o}}ller and\n                  Leandro Soares Indrusiak and\n                  Manfred Glesner and\n                  Sanna M{\\"{a}}{\\"{a}}tt{\\"{a}} and\n                  Jari Nurmi},\n  editor       = {Marcelo Lubaszewski and\n                  Michel Renovell and\n                  Rajesh K. Gupta},\n  title        = {A simplified executable model to evaluate latency and throughput of\n                  networks-on-chip},\n  booktitle    = {Proceedings of the 21st Annual Symposium on Integrated Circuits and\n                  Systems Design, {SBCCI} 2008, Gramado, Brazil, September 1-4, 2008},\n  pages        = {170--175},\n  publisher    = {{ACM}},\n  year         = {2008},\n  url          = {https://doi.org/10.1145/1404371.1404420},\n  doi          = {10.1145/1404371.1404420},\n  timestamp    = {Sun, 02 Oct 2022 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/conf/sbcci/OstMMIGMN08.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n MOTIM: an industrial application using nocs.\n \n \n \n \n\n\n \n Moraes, F. G.; Carara, E.; Pigatto, D. V.; and Calazans, N. L. V.\n\n\n \n\n\n\n In Lubaszewski, M.; Renovell, M.; and Gupta, R. K., editor(s), Proceedings of the 21st Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2008, Gramado, Brazil, September 1-4, 2008, pages 182–187, 2008. ACM\n \n\n\n\n
\n\n\n\n \n \n \"MOTIM:Paper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/sbcci/MoraesCPC08,\n  author       = {Fernando Gehm Moraes and\n                  Everton Carara and\n                  Daniel V. Pigatto and\n                  Ney Laert Vilar Calazans},\n  editor       = {Marcelo Lubaszewski and\n                  Michel Renovell and\n                  Rajesh K. Gupta},\n  title        = {{MOTIM:} an industrial application using nocs},\n  booktitle    = {Proceedings of the 21st Annual Symposium on Integrated Circuits and\n                  Systems Design, {SBCCI} 2008, Gramado, Brazil, September 1-4, 2008},\n  pages        = {182--187},\n  publisher    = {{ACM}},\n  year         = {2008},\n  url          = {https://doi.org/10.1145/1404371.1404422},\n  doi          = {10.1145/1404371.1404422},\n  timestamp    = {Sun, 02 Oct 2022 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/conf/sbcci/MoraesCPC08.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Validation of executable application models mapped onto network-on-chip platforms.\n \n \n \n \n\n\n \n Määttä, S.; Indrusiak, L. S.; Ost, L.; Möller, L.; Nurmi, J.; Glesner, M.; and Moraes, F.\n\n\n \n\n\n\n In IEEE Third International Symposium on Industrial Embedded Systems, SIES 2008, Montpellier / La Grande Motte, France, June 11-13, 2008, pages 118–125, 2008. IEEE\n \n\n\n\n
\n\n\n\n \n \n \"ValidationPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/sies/IndrusiakOMNGM08,\n  author       = {Sanna M{\\"{a}}{\\"{a}}tt{\\"{a}} and\n                  Leandro Soares Indrusiak and\n                  Luciano Ost and\n                  Leandro M{\\"{o}}ller and\n                  Jari Nurmi and\n                  Manfred Glesner and\n                  Fernando Moraes},\n  title        = {Validation of executable application models mapped onto network-on-chip\n                  platforms},\n  booktitle    = {{IEEE} Third International Symposium on Industrial Embedded Systems,\n                  {SIES} 2008, Montpellier / La Grande Motte, France, June 11-13, 2008},\n  pages        = {118--125},\n  publisher    = {{IEEE}},\n  year         = {2008},\n  url          = {https://doi.org/10.1109/SIES.2008.4577689},\n  doi          = {10.1109/SIES.2008.4577689},\n  timestamp    = {Mon, 03 Jan 2022 00:00:00 +0100},\n  biburl       = {https://dblp.org/rec/conf/sies/IndrusiakOMNGM08.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n  \n 2007\n \n \n (21)\n \n \n
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\n \n\n \n \n \n \n \n \n Wrapper design for the reuse of a bus, network-on-chip, or other functional interconnect as test access mechanism.\n \n \n \n \n\n\n \n Amory, A. M.; Goossens, K.; Marinissen, E. J.; Lubaszewski, M.; and Moraes, F.\n\n\n \n\n\n\n IET Comput. Digit. Tech., 1(3): 197–206. 2007.\n \n\n\n\n
\n\n\n\n \n \n \"WrapperPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@article{DBLP:journals/iet-cdt/AmoryGMLM07,\n  author       = {Alexandre M. Amory and\n                  Kees Goossens and\n                  Erik Jan Marinissen and\n                  Marcelo Lubaszewski and\n                  Fernando Moraes},\n  title        = {Wrapper design for the reuse of a bus, network-on-chip, or other functional\n                  interconnect as test access mechanism},\n  journal      = {{IET} Comput. Digit. Tech.},\n  volume       = {1},\n  number       = {3},\n  pages        = {197--206},\n  year         = {2007},\n  url          = {https://doi.org/10.1049/iet-cdt:20060152},\n  doi          = {10.1049/IET-CDT:20060152},\n  timestamp    = {Mon, 05 Feb 2024 00:00:00 +0100},\n  biburl       = {https://dblp.org/rec/journals/iet-cdt/AmoryGMLM07.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Run-time mapping and communication strategies for Homogeneous NoC-Based MPSoCs.\n \n \n \n \n\n\n \n Sassatelli, G.; Saint-Jean, N.; Benoit, P.; Torres, L.; Robert, M.; Woszezenki, C. R.; Grehs, I.; and Moraes, F. G.\n\n\n \n\n\n\n In Pocek, K. L.; and Buell, D. A., editor(s), IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2007, 23-25 April 2007, Napa, California, USA, pages 295–296, 2007. IEEE Computer Society\n \n\n\n\n
\n\n\n\n \n \n \"Run-timePaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/fccm/SassatelliSBTRWGM07,\n  author       = {Gilles Sassatelli and\n                  Nicolas Saint{-}Jean and\n                  Pascal Benoit and\n                  Lionel Torres and\n                  Michel Robert and\n                  Cristiane R. Woszezenki and\n                  Ismael Grehs and\n                  Fernando Gehm Moraes},\n  editor       = {Kenneth L. Pocek and\n                  Duncan A. Buell},\n  title        = {Run-time mapping and communication strategies for Homogeneous NoC-Based\n                  MPSoCs},\n  booktitle    = {{IEEE} Symposium on Field-Programmable Custom Computing Machines,\n                  {FCCM} 2007, 23-25 April 2007, Napa, California, {USA}},\n  pages        = {295--296},\n  publisher    = {{IEEE} Computer Society},\n  year         = {2007},\n  url          = {https://doi.org/10.1109/FCCM.2007.27},\n  doi          = {10.1109/FCCM.2007.27},\n  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},\n  biburl       = {https://dblp.org/rec/conf/fccm/SassatelliSBTRWGM07.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n SCAFFI: An intrachip FPGA asynchronous interface based on hard macros.\n \n \n \n \n\n\n \n Pontes, J. J. H.; Soares, R.; Carvalho, E.; Moraes, F.; and Calazans, N.\n\n\n \n\n\n\n In 25th International Conference on Computer Design, ICCD 2007, 7-10 October 2007, Lake Tahoe, CA, USA, Proceedings, pages 541–546, 2007. IEEE\n \n\n\n\n
\n\n\n\n \n \n \"SCAFFI:Paper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/iccd/PontesSCMC07,\n  author       = {Julian J. H. Pontes and\n                  Rafael Soares and\n                  Ewerson Carvalho and\n                  Fernando Moraes and\n                  Ney Calazans},\n  title        = {{SCAFFI:} An intrachip {FPGA} asynchronous interface based on hard\n                  macros},\n  booktitle    = {25th International Conference on Computer Design, {ICCD} 2007, 7-10\n                  October 2007, Lake Tahoe, CA, USA, Proceedings},\n  pages        = {541--546},\n  publisher    = {{IEEE}},\n  year         = {2007},\n  url          = {https://doi.org/10.1109/ICCD.2007.4601950},\n  doi          = {10.1109/ICCD.2007.4601950},\n  timestamp    = {Thu, 23 Mar 2023 00:00:00 +0100},\n  biburl       = {https://dblp.org/rec/conf/iccd/PontesSCMC07.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Reducing the Power Consumption in Networks-on-Chip through Data Coding Schemes.\n \n \n \n \n\n\n \n Palma, J. C. S.; Indrusiak, L. S.; Moraes, F. G.; Reis, R.; and Glesner, M.\n\n\n \n\n\n\n In 14th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2007, Marrakech, Morocco, December 11-14, 2007, pages 1007–1010, 2007. IEEE\n \n\n\n\n
\n\n\n\n \n \n \"ReducingPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/icecsys/PalmaIMRG07,\n  author       = {Jos{\\'{e}} Carlos S. Palma and\n                  Leandro Soares Indrusiak and\n                  Fernando Gehm Moraes and\n                  Ricardo Reis and\n                  Manfred Glesner},\n  title        = {Reducing the Power Consumption in Networks-on-Chip through Data Coding\n                  Schemes},\n  booktitle    = {14th {IEEE} International Conference on Electronics, Circuits, and\n                  Systems, {ICECS} 2007, Marrakech, Morocco, December 11-14, 2007},\n  pages        = {1007--1010},\n  publisher    = {{IEEE}},\n  year         = {2007},\n  url          = {https://doi.org/10.1109/ICECS.2007.4511163},\n  doi          = {10.1109/ICECS.2007.4511163},\n  timestamp    = {Tue, 22 Oct 2019 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/conf/icecsys/PalmaIMRG07.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n A Cryptographic Coarse Grain Reconfigurable Architecture Robust Against DPA.\n \n \n \n \n\n\n \n Mesquita, D.; Badrignans, B.; Torres, L.; Sassatelli, G.; Robert, M.; and Moraes, F.\n\n\n \n\n\n\n In 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), Proceedings, 26-30 March 2007, Long Beach, California, USA, pages 1–8, 2007. IEEE\n \n\n\n\n
\n\n\n\n \n \n \"APaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/ipps/MesquitaBTSRM07,\n  author       = {Daniel Mesquita and\n                  Beno{\\^{\\i}}t Badrignans and\n                  Lionel Torres and\n                  Gilles Sassatelli and\n                  Michel Robert and\n                  Fernando Moraes},\n  title        = {A Cryptographic Coarse Grain Reconfigurable Architecture Robust Against\n                  {DPA}},\n  booktitle    = {21th International Parallel and Distributed Processing Symposium {(IPDPS}\n                  2007), Proceedings, 26-30 March 2007, Long Beach, California, {USA}},\n  pages        = {1--8},\n  publisher    = {{IEEE}},\n  year         = {2007},\n  url          = {https://doi.org/10.1109/IPDPS.2007.370380},\n  doi          = {10.1109/IPDPS.2007.370380},\n  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},\n  biburl       = {https://dblp.org/rec/conf/ipps/MesquitaBTSRM07.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Evaluation of Algorithms for Low Energy Mapping onto NoCs.\n \n \n \n \n\n\n \n Marcon, C. A. M.; Moreno, E. I.; Calazans, N. L. V.; and Moraes, F. G.\n\n\n \n\n\n\n In International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pages 389–392, 2007. IEEE\n \n\n\n\n
\n\n\n\n \n \n \"EvaluationPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/iscas/MarconMCM07,\n  author       = {C{\\'{e}}sar A. M. Marcon and\n                  Edson I. Moreno and\n                  Ney Laert Vilar Calazans and\n                  Fernando Gehm Moraes},\n  title        = {Evaluation of Algorithms for Low Energy Mapping onto NoCs},\n  booktitle    = {International Symposium on Circuits and Systems {(ISCAS} 2007), 27-20\n                  May 2007, New Orleans, Louisiana, {USA}},\n  pages        = {389--392},\n  publisher    = {{IEEE}},\n  year         = {2007},\n  url          = {https://doi.org/10.1109/ISCAS.2007.378471},\n  doi          = {10.1109/ISCAS.2007.378471},\n  timestamp    = {Sun, 02 Oct 2022 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/conf/iscas/MarconMCM07.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Inserting Data Encoding Techniques into NoC-Based Systems.\n \n \n \n \n\n\n \n Palma, J. C. S.; Indrusiak, L. S.; Moraes, F. G.; Ortiz, A. G.; Glesner, M.; and Reis, R. A. L.\n\n\n \n\n\n\n In 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), May 9-11, 2007, Porto Alegre, Brazil, pages 299–304, 2007. IEEE Computer Society\n \n\n\n\n
\n\n\n\n \n \n \"InsertingPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/isvlsi/PalmaSMOGR07,\n  author       = {Jos{\\'{e}} Carlos S. Palma and\n                  Leandro Soares Indrusiak and\n                  Fernando Gehm Moraes and\n                  Alberto Garc{\\'{\\i}}a Ortiz and\n                  Manfred Glesner and\n                  Ricardo A. L. Reis},\n  title        = {Inserting Data Encoding Techniques into NoC-Based Systems},\n  booktitle    = {2007 {IEEE} Computer Society Annual Symposium on {VLSI} {(ISVLSI}\n                  2007), May 9-11, 2007, Porto Alegre, Brazil},\n  pages        = {299--304},\n  publisher    = {{IEEE} Computer Society},\n  year         = {2007},\n  url          = {https://doi.org/10.1109/ISVLSI.2007.58},\n  doi          = {10.1109/ISVLSI.2007.58},\n  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},\n  biburl       = {https://dblp.org/rec/conf/isvlsi/PalmaSMOGR07.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n MOTIM - A Scalable Architecture for Ethernet Switches.\n \n \n \n \n\n\n \n Bastos, E.; Carara, E.; Pigatto, D. V.; Calazans, N. L. V.; and Moraes, F.\n\n\n \n\n\n\n In 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), May 9-11, 2007, Porto Alegre, Brazil, pages 451–452, 2007. IEEE Computer Society\n \n\n\n\n
\n\n\n\n \n \n \"MOTIMPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/isvlsi/BastosCPCM07,\n  author       = {Erico Bastos and\n                  Everton Carara and\n                  Daniel V. Pigatto and\n                  Ney Laert Vilar Calazans and\n                  Fernando Moraes},\n  title        = {{MOTIM} - {A} Scalable Architecture for Ethernet Switches},\n  booktitle    = {2007 {IEEE} Computer Society Annual Symposium on {VLSI} {(ISVLSI}\n                  2007), May 9-11, 2007, Porto Alegre, Brazil},\n  pages        = {451--452},\n  publisher    = {{IEEE} Computer Society},\n  year         = {2007},\n  url          = {https://doi.org/10.1109/ISVLSI.2007.70},\n  doi          = {10.1109/ISVLSI.2007.70},\n  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},\n  biburl       = {https://dblp.org/rec/conf/isvlsi/BastosCPCM07.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Congestion-Aware Task Mapping in NoC-based MPSoCs with Dynamic Workload.\n \n \n \n \n\n\n \n Carvalho, E.; Calazans, N. L. V.; and Moraes, F. G.\n\n\n \n\n\n\n In 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), May 9-11, 2007, Porto Alegre, Brazil, pages 459–460, 2007. IEEE Computer Society\n \n\n\n\n
\n\n\n\n \n \n \"Congestion-AwarePaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/isvlsi/CarvalhoCM07,\n  author       = {Ewerson Carvalho and\n                  Ney Laert Vilar Calazans and\n                  Fernando Gehm Moraes},\n  title        = {Congestion-Aware Task Mapping in NoC-based MPSoCs with Dynamic Workload},\n  booktitle    = {2007 {IEEE} Computer Society Annual Symposium on {VLSI} {(ISVLSI}\n                  2007), May 9-11, 2007, Porto Alegre, Brazil},\n  pages        = {459--460},\n  publisher    = {{IEEE} Computer Society},\n  year         = {2007},\n  url          = {https://doi.org/10.1109/ISVLSI.2007.32},\n  doi          = {10.1109/ISVLSI.2007.32},\n  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},\n  biburl       = {https://dblp.org/rec/conf/isvlsi/CarvalhoCM07.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n A NoC-based Infrastructure to Enable Dynamic Self Reconfigurable Systems.\n \n \n \n\n\n \n Möller, L.; Grehs, I.; Carvalho, E.; Soares, R.; Calazans, N.; and Moraes, F.\n\n\n \n\n\n\n In Sassatelli, G.; Glesner, M.; Bobda, C.; and Benoit, P., editor(s), Proceedings of the 3rd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, ReCoSoC 2007, Montpellier, France, June 2007, pages 23–30, 2007. Univ. Montpellier II\n \n\n\n\n
\n\n\n\n \n\n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/recosoc/MollerGCSCM07,\n  author       = {Leandro M{\\"{o}}ller and\n                  Ismael Grehs and\n                  Ewerson Carvalho and\n                  Rafael Soares and\n                  Ney Calazans and\n                  Fernando Moraes},\n  editor       = {Gilles Sassatelli and\n                  Manfred Glesner and\n                  Christophe Bobda and\n                  Pascal Benoit},\n  title        = {A NoC-based Infrastructure to Enable Dynamic Self Reconfigurable Systems},\n  booktitle    = {Proceedings of the 3rd International Workshop on Reconfigurable Communication-centric\n                  Systems-on-Chip, ReCoSoC 2007, Montpellier, France, June 2007},\n  pages        = {23--30},\n  publisher    = {Univ. Montpellier {II}},\n  year         = {2007},\n  timestamp    = {Tue, 10 Mar 2020 00:00:00 +0100},\n  biburl       = {https://dblp.org/rec/conf/recosoc/MollerGCSCM07.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n SPP-NIDS - A Sea of Processors Platform for Network Intrusion Detection Systems.\n \n \n \n \n\n\n \n Caruso, L. C.; Guindani, G. M.; Schmitt, H.; Calazans, N.; and Moraes, F.\n\n\n \n\n\n\n In 18th IEEE International Workshop on Rapid System Prototyping (RSP 2007), 28-30 May 2007, Porto Alegre, RS, Brazil, pages 27–33, 2007. IEEE Computer Society\n \n\n\n\n
\n\n\n\n \n \n \"SPP-NIDSPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/rsp/CarusoGSCM07,\n  author       = {Luis Carlos Caruso and\n                  Guilherme Montez Guindani and\n                  Hugo Schmitt and\n                  Ney Calazans and\n                  Fernando Moraes},\n  title        = {{SPP-NIDS} - {A} Sea of Processors Platform for Network Intrusion\n                  Detection Systems},\n  booktitle    = {18th {IEEE} International Workshop on Rapid System Prototyping {(RSP}\n                  2007), 28-30 May 2007, Porto Alegre, RS, Brazil},\n  pages        = {27--33},\n  publisher    = {{IEEE} Computer Society},\n  year         = {2007},\n  url          = {https://doi.org/10.1109/RSP.2007.35},\n  doi          = {10.1109/RSP.2007.35},\n  timestamp    = {Thu, 23 Mar 2023 00:00:00 +0100},\n  biburl       = {https://dblp.org/rec/conf/rsp/CarusoGSCM07.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Heuristics for Dynamic Task Mapping in NoC-based Heterogeneous MPSoCs.\n \n \n \n \n\n\n \n Carvalho, E.; Calazans, N.; and Moraes, F.\n\n\n \n\n\n\n In 18th IEEE International Workshop on Rapid System Prototyping (RSP 2007), 28-30 May 2007, Porto Alegre, RS, Brazil, pages 34–40, 2007. IEEE Computer Society\n \n\n\n\n
\n\n\n\n \n \n \"HeuristicsPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/rsp/CarvalhoCM07,\n  author       = {Ewerson Carvalho and\n                  Ney Calazans and\n                  Fernando Moraes},\n  title        = {Heuristics for Dynamic Task Mapping in NoC-based Heterogeneous MPSoCs},\n  booktitle    = {18th {IEEE} International Workshop on Rapid System Prototyping {(RSP}\n                  2007), 28-30 May 2007, Porto Alegre, RS, Brazil},\n  pages        = {34--40},\n  publisher    = {{IEEE} Computer Society},\n  year         = {2007},\n  url          = {https://doi.org/10.1109/RSP.2007.26},\n  doi          = {10.1109/RSP.2007.26},\n  timestamp    = {Thu, 23 Mar 2023 00:00:00 +0100},\n  biburl       = {https://dblp.org/rec/conf/rsp/CarvalhoCM07.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Communication Models in Networks-on-Chip.\n \n \n \n \n\n\n \n Carara, E.; Mello, A.; and Moraes, F.\n\n\n \n\n\n\n In 18th IEEE International Workshop on Rapid System Prototyping (RSP 2007), 28-30 May 2007, Porto Alegre, RS, Brazil, pages 57–60, 2007. IEEE Computer Society\n \n\n\n\n
\n\n\n\n \n \n \"CommunicationPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/rsp/CararaMM07,\n  author       = {Everton Carara and\n                  Aline Mello and\n                  Fernando Moraes},\n  title        = {Communication Models in Networks-on-Chip},\n  booktitle    = {18th {IEEE} International Workshop on Rapid System Prototyping {(RSP}\n                  2007), 28-30 May 2007, Porto Alegre, RS, Brazil},\n  pages        = {57--60},\n  publisher    = {{IEEE} Computer Society},\n  year         = {2007},\n  url          = {https://doi.org/10.1109/RSP.2007.17},\n  doi          = {10.1109/RSP.2007.17},\n  timestamp    = {Thu, 23 Mar 2023 00:00:00 +0100},\n  biburl       = {https://dblp.org/rec/conf/rsp/CararaMM07.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Architectural Issues in Homogeneous NoC-Based MPSoC.\n \n \n \n \n\n\n \n Sassatelli, G.; Saint-Jean, N.; Woszezenki, C. R.; Grehs, I.; and Moraes, F. G.\n\n\n \n\n\n\n In 18th IEEE International Workshop on Rapid System Prototyping (RSP 2007), 28-30 May 2007, Porto Alegre, RS, Brazil, pages 139–142, 2007. IEEE Computer Society\n \n\n\n\n
\n\n\n\n \n \n \"ArchitecturalPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/rsp/SassatelliSWGM07,\n  author       = {Gilles Sassatelli and\n                  Nicolas Saint{-}Jean and\n                  Cristiane R. Woszezenki and\n                  Ismael Grehs and\n                  Fernando Gehm Moraes},\n  title        = {Architectural Issues in Homogeneous NoC-Based MPSoC},\n  booktitle    = {18th {IEEE} International Workshop on Rapid System Prototyping {(RSP}\n                  2007), 28-30 May 2007, Porto Alegre, RS, Brazil},\n  pages        = {139--142},\n  publisher    = {{IEEE} Computer Society},\n  year         = {2007},\n  url          = {https://doi.org/10.1109/RSP.2007.12},\n  doi          = {10.1109/RSP.2007.12},\n  timestamp    = {Thu, 23 Mar 2023 00:00:00 +0100},\n  biburl       = {https://dblp.org/rec/conf/rsp/SassatelliSWGM07.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Buffer sizing for QoS flows in wormhole packet switching NoCs.\n \n \n \n \n\n\n \n Tedesco, L.; Moraes, F.; and Calazans, N.\n\n\n \n\n\n\n In Petraglia, A.; Pedroni, V. A.; and Cauwenberghs, G., editor(s), Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2007, Copacabana, Rio de Janeiro, Brazil, September 3-6, 2007, pages 99–104, 2007. ACM\n \n\n\n\n
\n\n\n\n \n \n \"BufferPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/sbcci/TedescoMC07,\n  author       = {Leonel Tedesco and\n                  Fernando Moraes and\n                  Ney Calazans},\n  editor       = {Antonio Petraglia and\n                  Volnei A. Pedroni and\n                  Gert Cauwenberghs},\n  title        = {Buffer sizing for QoS flows in wormhole packet switching NoCs},\n  booktitle    = {Proceedings of the 20th Annual Symposium on Integrated Circuits and\n                  Systems Design, {SBCCI} 2007, Copacabana, Rio de Janeiro, Brazil,\n                  September 3-6, 2007},\n  pages        = {99--104},\n  publisher    = {{ACM}},\n  year         = {2007},\n  url          = {https://doi.org/10.1145/1284480.1284513},\n  doi          = {10.1145/1284480.1284513},\n  timestamp    = {Sun, 02 Oct 2022 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/conf/sbcci/TedescoMC07.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Router architecture for high-performance NoCs.\n \n \n \n \n\n\n \n Carara, E.; Moraes, F.; and Calazans, N.\n\n\n \n\n\n\n In Petraglia, A.; Pedroni, V. A.; and Cauwenberghs, G., editor(s), Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2007, Copacabana, Rio de Janeiro, Brazil, September 3-6, 2007, pages 111–116, 2007. ACM\n \n\n\n\n
\n\n\n\n \n \n \"RouterPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/sbcci/CararaMC07,\n  author       = {Everton Carara and\n                  Fernando Moraes and\n                  Ney Calazans},\n  editor       = {Antonio Petraglia and\n                  Volnei A. Pedroni and\n                  Gert Cauwenberghs},\n  title        = {Router architecture for high-performance NoCs},\n  booktitle    = {Proceedings of the 20th Annual Symposium on Integrated Circuits and\n                  Systems Design, {SBCCI} 2007, Copacabana, Rio de Janeiro, Brazil,\n                  September 3-6, 2007},\n  pages        = {111--116},\n  publisher    = {{ACM}},\n  year         = {2007},\n  url          = {https://doi.org/10.1145/1284480.1284515},\n  doi          = {10.1145/1284480.1284515},\n  timestamp    = {Sun, 02 Oct 2022 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/conf/sbcci/CararaMC07.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n QoS in Networks-on-Chip - Beyond Priority and Circuit Switching Techniques.\n \n \n \n \n\n\n \n Mello, A.; Calazans, N.; and Moraes, F.\n\n\n \n\n\n\n In VLSI-SoC: Advanced Topics on Systems on a Chip - A Selection of Extended Versions of the Best Papers of the Fourteenth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC2007), October 15-17, 2007, Atlanta, USA, volume 291, of IFIP, pages 1–22, 2007. Springer\n \n\n\n\n
\n\n\n\n \n \n \"QoSPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/vlsi/MelloCM07,\n  author       = {Aline Mello and\n                  Ney Calazans and\n                  Fernando Moraes},\n  title        = {QoS in Networks-on-Chip - Beyond Priority and Circuit Switching Techniques},\n  booktitle    = {VLSI-SoC: Advanced Topics on Systems on a Chip - {A} Selection of\n                  Extended Versions of the Best Papers of the Fourteenth International\n                  Conference on Very Large Scale Integration of System on Chip (VLSI-SoC2007),\n                  October 15-17, 2007, Atlanta, {USA}},\n  series       = {{IFIP}},\n  volume       = {291},\n  pages        = {1--22},\n  publisher    = {Springer},\n  year         = {2007},\n  url          = {https://doi.org/10.1007/978-0-387-89558-1\\_7},\n  doi          = {10.1007/978-0-387-89558-1\\_7},\n  timestamp    = {Sun, 02 Oct 2022 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/conf/vlsi/MelloCM07.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n DfT for the Reuse of Networks-on-Chip as Test Access Mechanism.\n \n \n \n \n\n\n \n Amory, A. M.; Ferlini, F.; Lubaszewski, M.; and Moraes, F.\n\n\n \n\n\n\n In 25th IEEE VLSI Test Symposium (VTS 2007), 6-10 May 2007, Berkeley, California, USA, pages 435–440, 2007. IEEE Computer Society\n \n\n\n\n
\n\n\n\n \n \n \"DfTPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/vts/AmoryFLM07,\n  author       = {Alexandre M. Amory and\n                  Frederico Ferlini and\n                  Marcelo Lubaszewski and\n                  Fernando Moraes},\n  title        = {DfT for the Reuse of Networks-on-Chip as Test Access Mechanism},\n  booktitle    = {25th {IEEE} {VLSI} Test Symposium {(VTS} 2007), 6-10 May 2007, Berkeley,\n                  California, {USA}},\n  pages        = {435--440},\n  publisher    = {{IEEE} Computer Society},\n  year         = {2007},\n  url          = {https://doi.org/10.1109/VTS.2007.26},\n  doi          = {10.1109/VTS.2007.26},\n  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},\n  biburl       = {https://dblp.org/rec/conf/vts/AmoryFLM07.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Exploring NoC Mapping Strategies: An Energy and Timing Aware Technique.\n \n \n \n \n\n\n \n Marcon, C. A. M.; Calazans, N. L. V.; Moraes, F. G.; Susin, A. A.; Reis, I. M.; and Hessel, F.\n\n\n \n\n\n\n CoRR, abs/0710.4738. 2007.\n \n\n\n\n
\n\n\n\n \n \n \"ExploringPaper\n  \n \n\n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@article{DBLP:journals/corr/abs-0710-4738,\n  author       = {C{\\'{e}}sar A. M. Marcon and\n                  Ney Laert Vilar Calazans and\n                  Fernando Gehm Moraes and\n                  Altamiro Amadeu Susin and\n                  Igor M. Reis and\n                  Fabiano Hessel},\n  title        = {Exploring NoC Mapping Strategies: An Energy and Timing Aware Technique},\n  journal      = {CoRR},\n  volume       = {abs/0710.4738},\n  year         = {2007},\n  url          = {http://arxiv.org/abs/0710.4738},\n  eprinttype    = {arXiv},\n  eprint       = {0710.4738},\n  timestamp    = {Mon, 13 Aug 2018 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/journals/corr/abs-0710-4738.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Test Time Reduction Reusing Multiple Processors in a Network-on-Chip Based Architecture.\n \n \n \n \n\n\n \n Amory, A. M.; Lubaszewski, M.; Moraes, F. G.; and Moreno, E. I.\n\n\n \n\n\n\n CoRR, abs/0710.4795. 2007.\n \n\n\n\n
\n\n\n\n \n \n \"TestPaper\n  \n \n\n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@article{DBLP:journals/corr/abs-0710-4795,\n  author       = {Alexandre M. Amory and\n                  Marcelo Lubaszewski and\n                  Fernando Gehm Moraes and\n                  Edson I. Moreno},\n  title        = {Test Time Reduction Reusing Multiple Processors in a Network-on-Chip\n                  Based Architecture},\n  journal      = {CoRR},\n  volume       = {abs/0710.4795},\n  year         = {2007},\n  url          = {http://arxiv.org/abs/0710.4795},\n  eprinttype    = {arXiv},\n  eprint       = {0710.4795},\n  timestamp    = {Mon, 13 Aug 2018 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/journals/corr/abs-0710-4795.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n MultiNoC: A Multiprocessing System Enabled by a Network on Chip.\n \n \n \n \n\n\n \n Mello, A.; Möller, L.; Calazans, N.; and Moraes, F.\n\n\n \n\n\n\n CoRR, abs/0710.4843. 2007.\n \n\n\n\n
\n\n\n\n \n \n \"MultiNoC:Paper\n  \n \n\n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@article{DBLP:journals/corr/abs-0710-4843,\n  author       = {Aline Mello and\n                  Leandro M{\\"{o}}ller and\n                  Ney Calazans and\n                  Fernando Moraes},\n  title        = {MultiNoC: {A} Multiprocessing System Enabled by a Network on Chip},\n  journal      = {CoRR},\n  volume       = {abs/0710.4843},\n  year         = {2007},\n  url          = {http://arxiv.org/abs/0710.4843},\n  eprinttype    = {arXiv},\n  eprint       = {0710.4843},\n  timestamp    = {Fri, 10 Jun 2022 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/journals/corr/abs-0710-4843.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n  \n 2006\n \n \n (9)\n \n \n
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\n \n\n \n \n \n \n \n \n Wrapper Design for the Reuse of Networks-on-Chip as Test Access Mechanism.\n \n \n \n \n\n\n \n Amory, A. M.; Goossens, K.; Marinissen, E. J.; Lubaszewski, M.; and Moraes, F.\n\n\n \n\n\n\n In 11th European Test Symposium, ETS 2006, Southhampton, UK, May 21-24, 2006, pages 213–218, 2006. IEEE Computer Society\n \n\n\n\n
\n\n\n\n \n \n \"WrapperPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/ets/AmoryGMLM06,\n  author       = {Alexandre M. Amory and\n                  Kees Goossens and\n                  Erik Jan Marinissen and\n                  Marcelo Lubaszewski and\n                  Fernando Moraes},\n  title        = {Wrapper Design for the Reuse of Networks-on-Chip as Test Access Mechanism},\n  booktitle    = {11th European Test Symposium, {ETS} 2006, Southhampton, UK, May 21-24,\n                  2006},\n  pages        = {213--218},\n  publisher    = {{IEEE} Computer Society},\n  year         = {2006},\n  url          = {https://doi.org/10.1109/ETS.2006.48},\n  doi          = {10.1109/ETS.2006.48},\n  timestamp    = {Mon, 05 Feb 2024 00:00:00 +0100},\n  biburl       = {https://dblp.org/rec/conf/ets/AmoryGMLM06.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n A Leak Resistant Architecture Against Side Channel Attacks.\n \n \n \n \n\n\n \n Mesquita, D.; Badrignans, B.; Torres, L.; Sassatelli, G.; Robert, M.; Bajard, J.; and Moraes, F. G.\n\n\n \n\n\n\n In Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), Madrid, Spain, August 28-30, 2006, pages 1–4, 2006. IEEE\n \n\n\n\n
\n\n\n\n \n \n \"APaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/fpl/MesquitaBTSRBM06,\n  author       = {Daniel Mesquita and\n                  Beno{\\^{\\i}}t Badrignans and\n                  Lionel Torres and\n                  Gilles Sassatelli and\n                  Michel Robert and\n                  Jean{-}Claude Bajard and\n                  Fernando Gehm Moraes},\n  title        = {A Leak Resistant Architecture Against Side Channel Attacks},\n  booktitle    = {Proceedings of the 2006 International Conference on Field Programmable\n                  Logic and Applications (FPL), Madrid, Spain, August 28-30, 2006},\n  pages        = {1--4},\n  publisher    = {{IEEE}},\n  year         = {2006},\n  url          = {https://doi.org/10.1109/FPL.2006.311335},\n  doi          = {10.1109/FPL.2006.311335},\n  timestamp    = {Sun, 02 Oct 2022 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/conf/fpl/MesquitaBTSRBM06.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Reconfigurable Systems Enabled by a Network-on-Chip.\n \n \n \n \n\n\n \n Möller, L.; Grehs, I.; Calazans, N.; and Moraes, F.\n\n\n \n\n\n\n In Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), Madrid, Spain, August 28-30, 2006, pages 1–4, 2006. IEEE\n \n\n\n\n
\n\n\n\n \n \n \"ReconfigurablePaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/fpl/MollerGCM06,\n  author       = {Leandro M{\\"{o}}ller and\n                  Ismael Grehs and\n                  Ney Calazans and\n                  Fernando Moraes},\n  title        = {Reconfigurable Systems Enabled by a Network-on-Chip},\n  booktitle    = {Proceedings of the 2006 International Conference on Field Programmable\n                  Logic and Applications (FPL), Madrid, Spain, August 28-30, 2006},\n  pages        = {1--4},\n  publisher    = {{IEEE}},\n  year         = {2006},\n  url          = {https://doi.org/10.1109/FPL.2006.311329},\n  doi          = {10.1109/FPL.2006.311329},\n  timestamp    = {Sun, 02 Oct 2022 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/conf/fpl/MollerGCM06.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Evaluation of current QoS Mechanisms in Networks on Chip.\n \n \n \n \n\n\n \n Mello, A.; Tedesco, L.; Calazans, N.; and Moraes, F.\n\n\n \n\n\n\n In International Symposium on System-on-Chip, SoC 2006, Tampere, Finland, November 13-16, 2006, pages 1–4, 2006. IEEE\n \n\n\n\n
\n\n\n\n \n \n \"EvaluationPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/issoc/MelloTCM06,\n  author       = {Aline Mello and\n                  Leonel Tedesco and\n                  Ney Calazans and\n                  Fernando Moraes},\n  title        = {Evaluation of current QoS Mechanisms in Networks on Chip},\n  booktitle    = {International Symposium on System-on-Chip, SoC 2006, Tampere, Finland,\n                  November 13-16, 2006},\n  pages        = {1--4},\n  publisher    = {{IEEE}},\n  year         = {2006},\n  url          = {https://doi.org/10.1109/ISSOC.2006.321981},\n  doi          = {10.1109/ISSOC.2006.321981},\n  timestamp    = {Sun, 02 Oct 2022 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/conf/issoc/MelloTCM06.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n A Leak Resistant SoC to Counteract Side Channel Attacks.\n \n \n \n \n\n\n \n Mesquita, D.; Badrignans, B.; Torres, L.; Sassatelli, G.; Robert, M.; and Moraes, F. G.\n\n\n \n\n\n\n In International Symposium on System-on-Chip, SoC 2006, Tampere, Finland, November 13-16, 2006, pages 1–4, 2006. IEEE\n \n\n\n\n
\n\n\n\n \n \n \"APaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/issoc/MesquitaBTSRM06,\n  author       = {Daniel Mesquita and\n                  Beno{\\^{\\i}}t Badrignans and\n                  Lionel Torres and\n                  Gilles Sassatelli and\n                  Michel Robert and\n                  Fernando Gehm Moraes},\n  title        = {A Leak Resistant SoC to Counteract Side Channel Attacks},\n  booktitle    = {International Symposium on System-on-Chip, SoC 2006, Tampere, Finland,\n                  November 13-16, 2006},\n  pages        = {1--4},\n  publisher    = {{IEEE}},\n  year         = {2006},\n  url          = {https://doi.org/10.1109/ISSOC.2006.322005},\n  doi          = {10.1109/ISSOC.2006.322005},\n  timestamp    = {Sun, 02 Oct 2022 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/conf/issoc/MesquitaBTSRM06.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Evaluating the Impact of Data Encoding Techniques on the Power Consumption in Networks-on-Chip.\n \n \n \n \n\n\n \n Palma, J. C. S.; Reis, R. A. L.; Indrusiak, L. S.; Ortiz, A. G.; Glesner, M.; and Moraes, F. G.\n\n\n \n\n\n\n In 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2-3 March 2006, Karlsruhe, Germany, pages 426–427, 2006. IEEE Computer Society\n \n\n\n\n
\n\n\n\n \n \n \"EvaluatingPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/isvlsi/PalmaRIOGM06,\n  author       = {Jos{\\'{e}} Carlos S. Palma and\n                  Ricardo A. L. Reis and\n                  Leandro Soares Indrusiak and\n                  Alberto Garc{\\'{\\i}}a Ortiz and\n                  Manfred Glesner and\n                  Fernando Gehm Moraes},\n  title        = {Evaluating the Impact of Data Encoding Techniques on the Power Consumption\n                  in Networks-on-Chip},\n  booktitle    = {2006 {IEEE} Computer Society Annual Symposium on {VLSI} {(ISVLSI}\n                  2006), 2-3 March 2006, Karlsruhe, Germany},\n  pages        = {426--427},\n  publisher    = {{IEEE} Computer Society},\n  year         = {2006},\n  url          = {https://doi.org/10.1109/ISVLSI.2006.42},\n  doi          = {10.1109/ISVLSI.2006.42},\n  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},\n  biburl       = {https://dblp.org/rec/conf/isvlsi/PalmaRIOGM06.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Adaptive Coding in Networks-on-Chip: Transition Activity Reduction Versus Power Overhead of the Codec Circuitry.\n \n \n \n \n\n\n \n Palma, J. C. S.; Indrusiak, L. S.; Moraes, F. G.; Ortiz, A. G.; Glesner, M.; and Reis, R. A. L.\n\n\n \n\n\n\n In Vounckx, J.; Azémard, N.; and Maurine, P., editor(s), Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 16th International Workshop, PATMOS 2006, Montpellier, France, September 13-15, 2006, Proceedings, volume 4148, of Lecture Notes in Computer Science, pages 603–613, 2006. Springer\n \n\n\n\n
\n\n\n\n \n \n \"AdaptivePaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/patmos/PalmaIMOGR06,\n  author       = {Jos{\\'{e}} Carlos S. Palma and\n                  Leandro Soares Indrusiak and\n                  Fernando Gehm Moraes and\n                  Alberto Garc{\\'{\\i}}a Ortiz and\n                  Manfred Glesner and\n                  Ricardo A. L. Reis},\n  editor       = {Johan Vounckx and\n                  Nadine Az{\\'{e}}mard and\n                  Philippe Maurine},\n  title        = {Adaptive Coding in Networks-on-Chip: Transition Activity Reduction\n                  Versus Power Overhead of the Codec Circuitry},\n  booktitle    = {Integrated Circuit and System Design. Power and Timing Modeling, Optimization\n                  and Simulation, 16th International Workshop, {PATMOS} 2006, Montpellier,\n                  France, September 13-15, 2006, Proceedings},\n  series       = {Lecture Notes in Computer Science},\n  volume       = {4148},\n  pages        = {603--613},\n  publisher    = {Springer},\n  year         = {2006},\n  url          = {https://doi.org/10.1007/11847083\\_59},\n  doi          = {10.1007/11847083\\_59},\n  timestamp    = {Tue, 14 May 2019 10:00:54 +0200},\n  biburl       = {https://dblp.org/rec/conf/patmos/PalmaIMOGR06.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Infrastructure for dynamic reconfigurable systems: choices and trade-offs.\n \n \n \n \n\n\n \n Möller, L.; Soares, R.; Carvalho, E.; Grehs, I.; Calazans, N.; and Moraes, F.\n\n\n \n\n\n\n In Jr., C. J. N. C.; Jacobi, R. P.; and Becker, J., editor(s), Proceedings of the 19th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2006, Ouro Preto, MG, Brazil, August 28 - September 1, 2006, pages 44–49, 2006. ACM\n \n\n\n\n
\n\n\n\n \n \n \"InfrastructurePaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/sbcci/MollerSCGCM06,\n  author       = {Leandro M{\\"{o}}ller and\n                  Rafael Soares and\n                  Ewerson Carvalho and\n                  Ismael Grehs and\n                  Ney Calazans and\n                  Fernando Moraes},\n  editor       = {Claudionor Jos{\\'{e}} Nunes Coelho Jr. and\n                  Ricardo P. Jacobi and\n                  J{\\"{u}}rgen Becker},\n  title        = {Infrastructure for dynamic reconfigurable systems: choices and trade-offs},\n  booktitle    = {Proceedings of the 19th Annual Symposium on Integrated Circuits and\n                  Systems Design, {SBCCI} 2006, Ouro Preto, MG, Brazil, August 28 -\n                  September 1, 2006},\n  pages        = {44--49},\n  publisher    = {{ACM}},\n  year         = {2006},\n  url          = {https://doi.org/10.1145/1150343.1150360},\n  doi          = {10.1145/1150343.1150360},\n  timestamp    = {Sun, 02 Oct 2022 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/conf/sbcci/MollerSCGCM06.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Application driven traffic modeling for NoCs.\n \n \n \n \n\n\n \n Tedesco, L.; Mello, A.; Giacomet, L.; Calazans, N.; and Moraes, F. G.\n\n\n \n\n\n\n In Jr., C. J. N. C.; Jacobi, R. P.; and Becker, J., editor(s), Proceedings of the 19th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2006, Ouro Preto, MG, Brazil, August 28 - September 1, 2006, pages 62–67, 2006. ACM\n \n\n\n\n
\n\n\n\n \n \n \"ApplicationPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/sbcci/TedescoMGCM06,\n  author       = {Leonel Tedesco and\n                  Aline Mello and\n                  Leonardo Giacomet and\n                  Ney Calazans and\n                  Fernando Gehm Moraes},\n  editor       = {Claudionor Jos{\\'{e}} Nunes Coelho Jr. and\n                  Ricardo P. Jacobi and\n                  J{\\"{u}}rgen Becker},\n  title        = {Application driven traffic modeling for NoCs},\n  booktitle    = {Proceedings of the 19th Annual Symposium on Integrated Circuits and\n                  Systems Design, {SBCCI} 2006, Ouro Preto, MG, Brazil, August 28 -\n                  September 1, 2006},\n  pages        = {62--67},\n  publisher    = {{ACM}},\n  year         = {2006},\n  url          = {https://doi.org/10.1145/1150343.1150364},\n  doi          = {10.1145/1150343.1150364},\n  timestamp    = {Sun, 02 Oct 2022 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/conf/sbcci/TedescoMGCM06.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n  \n 2005\n \n \n (11)\n \n \n
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\n \n\n \n \n \n \n \n \n MAIA: a framework for networks on chip generation and verification.\n \n \n \n \n\n\n \n Ost, L.; Mello, A.; Palma, J.; Moraes, F. G.; and Calazans, N.\n\n\n \n\n\n\n In Tang, T., editor(s), Proceedings of the 2005 Conference on Asia South Pacific Design Automation, ASP-DAC 2005, Shanghai, China, January 18-21, 2005, pages 49–52, 2005. ACM Press\n \n\n\n\n
\n\n\n\n \n \n \"MAIA:Paper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/aspdac/OstMPMC05,\n  author       = {Luciano Ost and\n                  Aline Mello and\n                  Jos{\\'{e}} Palma and\n                  Fernando Gehm Moraes and\n                  Ney Calazans},\n  editor       = {Tingao Tang},\n  title        = {{MAIA:} a framework for networks on chip generation and verification},\n  booktitle    = {Proceedings of the 2005 Conference on Asia South Pacific Design Automation,\n                  {ASP-DAC} 2005, Shanghai, China, January 18-21, 2005},\n  pages        = {49--52},\n  publisher    = {{ACM} Press},\n  year         = {2005},\n  url          = {https://doi.org/10.1145/1120725.1120741},\n  doi          = {10.1145/1120725.1120741},\n  timestamp    = {Sun, 02 Oct 2022 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/conf/aspdac/OstMPMC05.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Test Time Reduction Reusing Multiple Processors in a Network-on-Chip Based Architecture.\n \n \n \n \n\n\n \n Amory, A. M.; Lubaszewski, M.; Moraes, F. G.; and Moreno, E. I.\n\n\n \n\n\n\n In 2005 Design, Automation and Test in Europe Conference and Exposition (DATE 2005), 7-11 March 2005, Munich, Germany, pages 62–63, 2005. IEEE Computer Society\n \n\n\n\n
\n\n\n\n \n \n \"TestPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/date/AmoryLMM05,\n  author       = {Alexandre M. Amory and\n                  Marcelo Lubaszewski and\n                  Fernando Gehm Moraes and\n                  Edson I. Moreno},\n  title        = {Test Time Reduction Reusing Multiple Processors in a Network-on-Chip\n                  Based Architecture},\n  booktitle    = {2005 Design, Automation and Test in Europe Conference and Exposition\n                  {(DATE} 2005), 7-11 March 2005, Munich, Germany},\n  pages        = {62--63},\n  publisher    = {{IEEE} Computer Society},\n  year         = {2005},\n  url          = {https://doi.org/10.1109/DATE.2005.304},\n  doi          = {10.1109/DATE.2005.304},\n  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},\n  biburl       = {https://dblp.org/rec/conf/date/AmoryLMM05.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Exploring NoC Mapping Strategies: An Energy and Timing Aware Technique.\n \n \n \n \n\n\n \n Marcon, C. A. M.; Calazans, N. L. V.; Moraes, F. G.; Susin, A. A.; Reis, I. M.; and Hessel, F.\n\n\n \n\n\n\n In 2005 Design, Automation and Test in Europe Conference and Exposition (DATE 2005), 7-11 March 2005, Munich, Germany, pages 502–507, 2005. IEEE Computer Society\n \n\n\n\n
\n\n\n\n \n \n \"ExploringPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/date/MarconCMSRH05,\n  author       = {C{\\'{e}}sar A. M. Marcon and\n                  Ney Laert Vilar Calazans and\n                  Fernando Gehm Moraes and\n                  Altamiro Amadeu Susin and\n                  Igor M. Reis and\n                  Fabiano Hessel},\n  title        = {Exploring NoC Mapping Strategies: An Energy and Timing Aware Technique},\n  booktitle    = {2005 Design, Automation and Test in Europe Conference and Exposition\n                  {(DATE} 2005), 7-11 March 2005, Munich, Germany},\n  pages        = {502--507},\n  publisher    = {{IEEE} Computer Society},\n  year         = {2005},\n  url          = {https://doi.org/10.1109/DATE.2005.149},\n  doi          = {10.1109/DATE.2005.149},\n  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},\n  biburl       = {https://dblp.org/rec/conf/date/MarconCMSRH05.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n A scalable test strategy for network-on-chip routers.\n \n \n \n \n\n\n \n Amory, A. M.; Brião, E. W.; Cota, É. F.; Lubaszewski, M.; and Moraes, F. G.\n\n\n \n\n\n\n In Proceedings 2005 IEEE International Test Conference, ITC 2005, Austin, TX, USA, November 8-10, 2005, pages 9, 2005. IEEE Computer Society\n \n\n\n\n
\n\n\n\n \n \n \"APaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
\n
@inproceedings{DBLP:conf/itc/AmoryBCLM05,\n  author       = {Alexandre M. Amory and\n                  Eduardo Wenzel Bri{\\~{a}}o and\n                  {\\'{E}}rika F. Cota and\n                  Marcelo Lubaszewski and\n                  Fernando Gehm Moraes},\n  title        = {A scalable test strategy for network-on-chip routers},\n  booktitle    = {Proceedings 2005 {IEEE} International Test Conference, {ITC} 2005,\n                  Austin, TX, USA, November 8-10, 2005},\n  pages        = {9},\n  publisher    = {{IEEE} Computer Society},\n  year         = {2005},\n  url          = {https://doi.org/10.1109/TEST.2005.1584020},\n  doi          = {10.1109/TEST.2005.1584020},\n  timestamp    = {Thu, 23 Mar 2023 00:00:00 +0100},\n  biburl       = {https://dblp.org/rec/conf/itc/AmoryBCLM05.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n A new hardware countermeasure for masking power signatures of crypto cores.\n \n \n \n\n\n \n Mesquita, D.; Techer, J.; Torres, L.; Sassatelli, G.; Cambon, G.; Robert, M.; and Moraes, F.\n\n\n \n\n\n\n In Sassatelli, G.; Glesner, M.; Torres, L.; Indrusiak, L. S.; and Hollstein, T., editor(s), Proceedings of the 1st International Workshop on Reconfigurable Communication-centric Systems-on-Chip, ReCoSoC 2005, Montpellier, France, June 2005, pages 169–176, 2005. Univ. Montpellier II\n \n\n\n\n
\n\n\n\n \n\n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/recosoc/MesquitaTTSCRM05,\n  author       = {Daniel Mesquita and\n                  Jean{-}Denis Techer and\n                  Lionel Torres and\n                  Gilles Sassatelli and\n                  Gaston Cambon and\n                  Michel Robert and\n                  Fernando Moraes},\n  editor       = {Gilles Sassatelli and\n                  Manfred Glesner and\n                  Lionel Torres and\n                  Leandro Soares Indrusiak and\n                  Thomas Hollstein},\n  title        = {A new hardware countermeasure for masking power signatures of crypto\n                  cores},\n  booktitle    = {Proceedings of the 1st International Workshop on Reconfigurable Communication-centric\n                  Systems-on-Chip, ReCoSoC 2005, Montpellier, France, June 2005},\n  pages        = {169--176},\n  publisher    = {Univ. Montpellier {II}},\n  year         = {2005},\n  timestamp    = {Tue, 10 Mar 2020 00:00:00 +0100},\n  biburl       = {https://dblp.org/rec/conf/recosoc/MesquitaTTSCRM05.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Current mask generation: a transistor level security against DPA attacks.\n \n \n \n \n\n\n \n Mesquita, D.; Techer, J.; Torres, L.; Sassatelli, G.; Cambon, G.; Robert, M.; and Moraes, F.\n\n\n \n\n\n\n In Galup-Montoro, C.; Bampi, S.; and Orailoglu, A., editor(s), Proceedings of the 18th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2005, Florianolpolis, Brazil, September 4-7, 2005, pages 115–120, 2005. ACM\n \n\n\n\n
\n\n\n\n \n \n \"CurrentPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
\n
@inproceedings{DBLP:conf/sbcci/MesquitaTTSCRM05,\n  author       = {Daniel Mesquita and\n                  Jean{-}Denis Techer and\n                  Lionel Torres and\n                  Gilles Sassatelli and\n                  Gaston Cambon and\n                  Michel Robert and\n                  Fernando Moraes},\n  editor       = {Carlos Galup{-}Montoro and\n                  Sergio Bampi and\n                  Alex Orailoglu},\n  title        = {Current mask generation: a transistor level security against {DPA}\n                  attacks},\n  booktitle    = {Proceedings of the 18th Annual Symposium on Integrated Circuits and\n                  Systems Design, {SBCCI} 2005, Florianolpolis, Brazil, September 4-7,\n                  2005},\n  pages        = {115--120},\n  publisher    = {{ACM}},\n  year         = {2005},\n  url          = {https://doi.org/10.1145/1081081.1081114},\n  doi          = {10.1145/1081081.1081114},\n  timestamp    = {Sun, 02 Oct 2022 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/conf/sbcci/MesquitaTTSCRM05.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Virtual channels in networks on chip: implementation and evaluation on hermes NoC.\n \n \n \n \n\n\n \n Mello, A.; Tedesco, L.; Calazans, N.; and Moraes, F.\n\n\n \n\n\n\n In Galup-Montoro, C.; Bampi, S.; and Orailoglu, A., editor(s), Proceedings of the 18th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2005, Florianolpolis, Brazil, September 4-7, 2005, pages 178–183, 2005. ACM\n \n\n\n\n
\n\n\n\n \n \n \"VirtualPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
\n
@inproceedings{DBLP:conf/sbcci/MelloTCM05,\n  author       = {Aline Mello and\n                  Leonel Tedesco and\n                  Ney Calazans and\n                  Fernando Moraes},\n  editor       = {Carlos Galup{-}Montoro and\n                  Sergio Bampi and\n                  Alex Orailoglu},\n  title        = {Virtual channels in networks on chip: implementation and evaluation\n                  on hermes NoC},\n  booktitle    = {Proceedings of the 18th Annual Symposium on Integrated Circuits and\n                  Systems Design, {SBCCI} 2005, Florianolpolis, Brazil, September 4-7,\n                  2005},\n  pages        = {178--183},\n  publisher    = {{ACM}},\n  year         = {2005},\n  url          = {https://doi.org/10.1145/1081081.1081128},\n  doi          = {10.1145/1081081.1081128},\n  timestamp    = {Sun, 02 Oct 2022 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/conf/sbcci/MelloTCM05.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Traffic generation and performance evaluation for mesh-based NoCs.\n \n \n \n \n\n\n \n Tedesco, L.; Mello, A.; Garibotti, D.; Calazans, N.; and Moraes, F.\n\n\n \n\n\n\n In Galup-Montoro, C.; Bampi, S.; and Orailoglu, A., editor(s), Proceedings of the 18th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2005, Florianolpolis, Brazil, September 4-7, 2005, pages 184–189, 2005. ACM\n \n\n\n\n
\n\n\n\n \n \n \"TrafficPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
\n
@inproceedings{DBLP:conf/sbcci/TedescoMGCM05,\n  author       = {Leonel Tedesco and\n                  Aline Mello and\n                  Diego Garibotti and\n                  Ney Calazans and\n                  Fernando Moraes},\n  editor       = {Carlos Galup{-}Montoro and\n                  Sergio Bampi and\n                  Alex Orailoglu},\n  title        = {Traffic generation and performance evaluation for mesh-based NoCs},\n  booktitle    = {Proceedings of the 18th Annual Symposium on Integrated Circuits and\n                  Systems Design, {SBCCI} 2005, Florianolpolis, Brazil, September 4-7,\n                  2005},\n  pages        = {184--189},\n  publisher    = {{ACM}},\n  year         = {2005},\n  url          = {https://doi.org/10.1145/1081081.1081129},\n  doi          = {10.1145/1081081.1081129},\n  timestamp    = {Sun, 02 Oct 2022 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/conf/sbcci/TedescoMGCM05.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Mapping embedded systems onto NoCs: the traffic effect on dynamic energy estimation.\n \n \n \n \n\n\n \n Palma, J. C. S.; Marcon, C. A. M.; Moraes, F. G.; Calazans, N. L. V.; Reis, R. A. L.; and Susin, A. A.\n\n\n \n\n\n\n In Galup-Montoro, C.; Bampi, S.; and Orailoglu, A., editor(s), Proceedings of the 18th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2005, Florianolpolis, Brazil, September 4-7, 2005, pages 196–201, 2005. ACM\n \n\n\n\n
\n\n\n\n \n \n \"MappingPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/sbcci/PalmaMMCRS05,\n  author       = {Jos{\\'{e}} Carlos S. Palma and\n                  C{\\'{e}}sar A. M. Marcon and\n                  Fernando Gehm Moraes and\n                  Ney Laert Vilar Calazans and\n                  Ricardo A. L. Reis and\n                  Altamiro Amadeu Susin},\n  editor       = {Carlos Galup{-}Montoro and\n                  Sergio Bampi and\n                  Alex Orailoglu},\n  title        = {Mapping embedded systems onto NoCs: the traffic effect on dynamic\n                  energy estimation},\n  booktitle    = {Proceedings of the 18th Annual Symposium on Integrated Circuits and\n                  Systems Design, {SBCCI} 2005, Florianolpolis, Brazil, September 4-7,\n                  2005},\n  pages        = {196--201},\n  publisher    = {{ACM}},\n  year         = {2005},\n  url          = {https://doi.org/10.1145/1081081.1081131},\n  doi          = {10.1145/1081081.1081131},\n  timestamp    = {Sun, 02 Oct 2022 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/conf/sbcci/PalmaMMCRS05.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Modeling the Traffic Effect for the Application Cores Mapping Problem onto NoCs.\n \n \n \n \n\n\n \n Marcon, C. A. M.; Palma, J. C. S.; Calazans, N. L. V.; Moraes, F. G.; Susin, A. A.; and da Luz Reis, R. A.\n\n\n \n\n\n\n In da Luz Reis, R. A.; Osseiran, A.; and Pfleiderer, H., editor(s), VLSI-SoC: From Systems To Silicon, Proceedings of IFIP TC 10, WG 10.5, Thirteenth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC 2005), October 17-19, 2005, Perth, Australia, volume 240, of IFIP, pages 179–194, 2005. Springer\n \n\n\n\n
\n\n\n\n \n \n \"ModelingPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
\n
@inproceedings{DBLP:conf/vlsi/MarconPCMSR05,\n  author       = {C{\\'{e}}sar A. M. Marcon and\n                  Jos{\\'{e}} Carlos S. Palma and\n                  Ney Laert Vilar Calazans and\n                  Fernando Gehm Moraes and\n                  Altamiro Amadeu Susin and\n                  Ricardo Augusto da Luz Reis},\n  editor       = {Ricardo Augusto da Luz Reis and\n                  Adam Osseiran and\n                  Hans{-}J{\\"{o}}rg Pfleiderer},\n  title        = {Modeling the Traffic Effect for the Application Cores Mapping Problem\n                  onto NoCs},\n  booktitle    = {VLSI-SoC: From Systems To Silicon, Proceedings of {IFIP} {TC} 10,\n                  {WG} 10.5, Thirteenth International Conference on Very Large Scale\n                  Integration of System on Chip (VLSI-SoC 2005), October 17-19, 2005,\n                  Perth, Australia},\n  series       = {{IFIP}},\n  volume       = {240},\n  pages        = {179--194},\n  publisher    = {Springer},\n  year         = {2005},\n  url          = {https://doi.org/10.1007/978-0-387-73661-7\\_12},\n  doi          = {10.1007/978-0-387-73661-7\\_12},\n  timestamp    = {Sun, 02 Oct 2022 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/conf/vlsi/MarconPCMSR05.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Current Mask Generation: an Analog Circuit to Thwart DPA Attacks.\n \n \n \n \n\n\n \n Mesquita, D.; Techer, J.; Torres, L.; Robert, M.; Cathébras, G.; Sassatelli, G.; and Moraes, F. G.\n\n\n \n\n\n\n In da Luz Reis, R. A.; Osseiran, A.; and Pfleiderer, H., editor(s), VLSI-SoC: From Systems To Silicon, Proceedings of IFIP TC 10, WG 10.5, Thirteenth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC 2005), October 17-19, 2005, Perth, Australia, volume 240, of IFIP, pages 317–330, 2005. Springer\n \n\n\n\n
\n\n\n\n \n \n \"CurrentPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/vlsi/MesquitaTTRCSM05,\n  author       = {Daniel Mesquita and\n                  Jean{-}Denis Techer and\n                  Lionel Torres and\n                  Michel Robert and\n                  Guy Cath{\\'{e}}bras and\n                  Gilles Sassatelli and\n                  Fernando Gehm Moraes},\n  editor       = {Ricardo Augusto da Luz Reis and\n                  Adam Osseiran and\n                  Hans{-}J{\\"{o}}rg Pfleiderer},\n  title        = {Current Mask Generation: an Analog Circuit to Thwart {DPA} Attacks},\n  booktitle    = {VLSI-SoC: From Systems To Silicon, Proceedings of {IFIP} {TC} 10,\n                  {WG} 10.5, Thirteenth International Conference on Very Large Scale\n                  Integration of System on Chip (VLSI-SoC 2005), October 17-19, 2005,\n                  Perth, Australia},\n  series       = {{IFIP}},\n  volume       = {240},\n  pages        = {317--330},\n  publisher    = {Springer},\n  year         = {2005},\n  url          = {https://doi.org/10.1007/978-0-387-73661-7\\_20},\n  doi          = {10.1007/978-0-387-73661-7\\_20},\n  timestamp    = {Tue, 26 Jun 2018 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/conf/vlsi/MesquitaTTRCSM05.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n  \n 2004\n \n \n (5)\n \n \n
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\n \n\n \n \n \n \n \n \n HERMES: an infrastructure for low area overhead packet-switching networks on chip.\n \n \n \n \n\n\n \n Moraes, F. G.; Calazans, N.; Mello, A.; Möller, L.; and Ost, L.\n\n\n \n\n\n\n Integr., 38(1): 69–93. 2004.\n \n\n\n\n
\n\n\n\n \n \n \"HERMES:Paper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@article{DBLP:journals/integration/MoraesCMMO04,\n  author       = {Fernando Gehm Moraes and\n                  Ney Calazans and\n                  Aline Mello and\n                  Leandro M{\\"{o}}ller and\n                  Luciano Ost},\n  title        = {{HERMES:} an infrastructure for low area overhead packet-switching\n                  networks on chip},\n  journal      = {Integr.},\n  volume       = {38},\n  number       = {1},\n  pages        = {69--93},\n  year         = {2004},\n  url          = {https://doi.org/10.1016/j.vlsi.2004.03.003},\n  doi          = {10.1016/J.VLSI.2004.03.003},\n  timestamp    = {Sun, 02 Oct 2022 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/journals/integration/MoraesCMMO04.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n MultiNoC: A Multiprocessing System Enabled by a Network on Chip.\n \n \n \n \n\n\n \n Mello, A.; Möller, L.; Calazans, N.; and Moraes, F. G.\n\n\n \n\n\n\n In 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France, pages 234–239, 2004. IEEE Computer Society\n \n\n\n\n
\n\n\n\n \n \n \"MultiNoC:Paper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
\n
@inproceedings{DBLP:conf/date/MelloMCM04,\n  author       = {Aline Mello and\n                  Leandro M{\\"{o}}ller and\n                  Ney Calazans and\n                  Fernando Gehm Moraes},\n  title        = {MultiNoC: {A} Multiprocessing System Enabled by a Network on Chip},\n  booktitle    = {2004 Design, Automation and Test in Europe Conference and Exposition\n                  {(DATE} 2004), 16-20 February 2004, Paris, France},\n  pages        = {234--239},\n  publisher    = {{IEEE} Computer Society},\n  year         = {2004},\n  url          = {https://doi.org/10.1109/DATE.2005.218},\n  doi          = {10.1109/DATE.2005.218},\n  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},\n  biburl       = {https://dblp.org/rec/conf/date/MelloMCM04.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n FiPRe: An Implementation Model to Enable Self-Reconfigurable Applications.\n \n \n \n \n\n\n \n Möller, L.; Calazans, N. L. V.; Moraes, F. G.; Brião, E. W.; Carvalho, E.; and Camozzato, D.\n\n\n \n\n\n\n In Becker, J.; Platzner, M.; and Vernalde, S., editor(s), Field Programmable Logic and Application, 14th International Conference , FPL 2004, Leuven, Belgium, August 30-September 1, 2004, Proceedings, volume 3203, of Lecture Notes in Computer Science, pages 1042–1046, 2004. Springer\n \n\n\n\n
\n\n\n\n \n \n \"FiPRe:Paper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/fpl/MollerCMBCC04,\n  author       = {Leandro M{\\"{o}}ller and\n                  Ney Laert Vilar Calazans and\n                  Fernando Gehm Moraes and\n                  Eduardo Wenzel Bri{\\~{a}}o and\n                  Ewerson Carvalho and\n                  Daniel Camozzato},\n  editor       = {J{\\"{u}}rgen Becker and\n                  Marco Platzner and\n                  Serge Vernalde},\n  title        = {FiPRe: An Implementation Model to Enable Self-Reconfigurable Applications},\n  booktitle    = {Field Programmable Logic and Application, 14th International Conference\n                  , {FPL} 2004, Leuven, Belgium, August 30-September 1, 2004, Proceedings},\n  series       = {Lecture Notes in Computer Science},\n  volume       = {3203},\n  pages        = {1042--1046},\n  publisher    = {Springer},\n  year         = {2004},\n  url          = {https://doi.org/10.1007/978-3-540-30117-2\\_123},\n  doi          = {10.1007/978-3-540-30117-2\\_123},\n  timestamp    = {Fri, 19 Jul 2019 13:02:47 +0200},\n  biburl       = {https://dblp.org/rec/conf/fpl/MollerCMBCC04.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n PaDReH: a framework for the design and implementation of dynamically and partially reconfigurable systems.\n \n \n \n \n\n\n \n Carvalho, E.; Calazans, N.; Brião, E. W.; and Moraes, F.\n\n\n \n\n\n\n In da Silva Barros, E. N.; Wagner, F. R.; Carro, L.; and Rammig, F., editor(s), Proceedings of the 17th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2004, Pernambuco, Brazil, September 7-11, 2004, pages 10–15, 2004. ACM\n \n\n\n\n
\n\n\n\n \n \n \"PaDReH:Paper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/sbcci/CarvalhoCBM04,\n  author       = {Ewerson Carvalho and\n                  Ney Calazans and\n                  Eduardo Wenzel Bri{\\~{a}}o and\n                  Fernando Moraes},\n  editor       = {Edna Natividade da Silva Barros and\n                  Fl{\\'{a}}vio Rech Wagner and\n                  Luigi Carro and\n                  Franz{-}Josef Rammig},\n  title        = {PaDReH: a framework for the design and implementation of dynamically\n                  and partially reconfigurable systems},\n  booktitle    = {Proceedings of the 17th Annual Symposium on Integrated Circuits and\n                  Systems Design, {SBCCI} 2004, Pernambuco, Brazil, September 7-11,\n                  2004},\n  pages        = {10--15},\n  publisher    = {{ACM}},\n  year         = {2004},\n  url          = {https://doi.org/10.1145/1016568.1016580},\n  doi          = {10.1145/1016568.1016580},\n  timestamp    = {Sun, 02 Oct 2022 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/conf/sbcci/CarvalhoCBM04.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Reducing test time with processor reuse in network-on-chip based systems.\n \n \n \n \n\n\n \n Amory, A. M.; Cota, É. F.; Lubaszewski, M.; and Moraes, F. G.\n\n\n \n\n\n\n In da Silva Barros, E. N.; Wagner, F. R.; Carro, L.; and Rammig, F., editor(s), Proceedings of the 17th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2004, Pernambuco, Brazil, September 7-11, 2004, pages 111–116, 2004. ACM\n \n\n\n\n
\n\n\n\n \n \n \"ReducingPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
\n
@inproceedings{DBLP:conf/sbcci/AmoryCLM04,\n  author       = {Alexandre M. Amory and\n                  {\\'{E}}rika F. Cota and\n                  Marcelo Lubaszewski and\n                  Fernando Gehm Moraes},\n  editor       = {Edna Natividade da Silva Barros and\n                  Fl{\\'{a}}vio Rech Wagner and\n                  Luigi Carro and\n                  Franz{-}Josef Rammig},\n  title        = {Reducing test time with processor reuse in network-on-chip based systems},\n  booktitle    = {Proceedings of the 17th Annual Symposium on Integrated Circuits and\n                  Systems Design, {SBCCI} 2004, Pernambuco, Brazil, September 7-11,\n                  2004},\n  pages        = {111--116},\n  publisher    = {{ACM}},\n  year         = {2004},\n  url          = {https://doi.org/10.1145/1016568.1016602},\n  doi          = {10.1145/1016568.1016602},\n  timestamp    = {Sun, 02 Oct 2022 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/conf/sbcci/AmoryCLM04.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n  \n 2003\n \n \n (11)\n \n \n
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\n \n\n \n \n \n \n \n \n Development of a Tool-Set for Remote and Partial Reconfiguration of FPGAs.\n \n \n \n \n\n\n \n Moraes, F. G.; Mesquita, D.; Palma, J. C. S.; Möller, L.; and Calazans, N. L. V.\n\n\n \n\n\n\n In 2003 Design, Automation and Test in Europe Conference and Exposition (DATE 2003), 3-7 March 2003, Munich, Germany, pages 11122–11123, 2003. IEEE Computer Society\n \n\n\n\n
\n\n\n\n \n \n \"DevelopmentPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/date/MoraesMPMC03,\n  author       = {Fernando Gehm Moraes and\n                  Daniel Mesquita and\n                  Jos{\\'{e}} Carlos S. Palma and\n                  Leandro M{\\"{o}}ller and\n                  Ney Laert Vilar Calazans},\n  title        = {Development of a Tool-Set for Remote and Partial Reconfiguration of\n                  FPGAs},\n  booktitle    = {2003 Design, Automation and Test in Europe Conference and Exposition\n                  {(DATE} 2003), 3-7 March 2003, Munich, Germany},\n  pages        = {11122--11123},\n  publisher    = {{IEEE} Computer Society},\n  year         = {2003},\n  url          = {https://doi.ieeecomputersociety.org/10.1109/DATE.2003.10217},\n  doi          = {10.1109/DATE.2003.10217},\n  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},\n  biburl       = {https://dblp.org/rec/conf/date/MoraesMPMC03.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Design of a fingerprint system using a hardware/software environment.\n \n \n \n \n\n\n \n Bonato, V.; Molz, R. F.; Furtado, J. C.; Ferrão, M. F.; and Moraes, F. G.\n\n\n \n\n\n\n In Trimberger, S.; and Tessier, R., editor(s), Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2003, Monterey, CA, USA, February 23-25, 2003, pages 240, 2003. ACM\n \n\n\n\n
\n\n\n\n \n \n \"DesignPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/fpga/BonatoMFFM03,\n  author       = {Vanderlei Bonato and\n                  Rolf Fredi Molz and\n                  Jo{\\~{a}}o Carlos Furtado and\n                  Marcos Fl{\\^{o}}res Ferr{\\~{a}}o and\n                  Fernando Gehm Moraes},\n  editor       = {Steve Trimberger and\n                  Russell Tessier},\n  title        = {Design of a fingerprint system using a hardware/software environment},\n  booktitle    = {Proceedings of the {ACM/SIGDA} International Symposium on Field Programmable\n                  Gate Arrays, {FPGA} 2003, Monterey, CA, USA, February 23-25, 2003},\n  pages        = {240},\n  publisher    = {{ACM}},\n  year         = {2003},\n  url          = {https://doi.org/10.1145/611817.611860},\n  doi          = {10.1145/611817.611860},\n  timestamp    = {Sun, 02 Oct 2022 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/conf/fpga/BonatoMFFM03.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Propose of a Hardware Implementation for Fingerprint Systems.\n \n \n \n \n\n\n \n Bonato, V.; Molz, R. F.; Furtado, J. C.; Ferrão, M. F.; and Moraes, F. G.\n\n\n \n\n\n\n In Cheung, P. Y. K.; Constantinides, G. A.; and de Sousa, J. T., editor(s), Field Programmable Logic and Application, 13th International Conference, FPL 2003, Lisbon, Portugal, September 1-3, 2003, Proceedings, volume 2778, of Lecture Notes in Computer Science, pages 1158–1161, 2003. Springer\n \n\n\n\n
\n\n\n\n \n \n \"ProposePaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/fpl/BonatoMFFM03,\n  author       = {Vanderlei Bonato and\n                  Rolf Fredi Molz and\n                  Jo{\\~{a}}o Carlos Furtado and\n                  Marcos Fl{\\^{o}}res Ferr{\\~{a}}o and\n                  Fernando Gehm Moraes},\n  editor       = {Peter Y. K. Cheung and\n                  George A. Constantinides and\n                  Jos{\\'{e}} T. de Sousa},\n  title        = {Propose of a Hardware Implementation for Fingerprint Systems},\n  booktitle    = {Field Programmable Logic and Application, 13th International Conference,\n                  {FPL} 2003, Lisbon, Portugal, September 1-3, 2003, Proceedings},\n  series       = {Lecture Notes in Computer Science},\n  volume       = {2778},\n  pages        = {1158--1161},\n  publisher    = {Springer},\n  year         = {2003},\n  url          = {https://doi.org/10.1007/978-3-540-45234-8\\_143},\n  doi          = {10.1007/978-3-540-45234-8\\_143},\n  timestamp    = {Tue, 14 May 2019 10:00:48 +0200},\n  biburl       = {https://dblp.org/rec/conf/fpl/BonatoMFFM03.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Remote and Partial Reconfiguration of FPGAs: Tools and Trends.\n \n \n \n \n\n\n \n Mesquita, D.; Moraes, F. G.; Palma, J.; Möller, L.; and Calazans, N. L. V.\n\n\n \n\n\n\n In 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 22-26 April 2003, Nice, France, CD-ROM/Abstracts Proceedings, pages 177, 2003. IEEE Computer Society\n \n\n\n\n
\n\n\n\n \n \n \"RemotePaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/ipps/MesquitaMPMC03,\n  author       = {Daniel Mesquita and\n                  Fernando Gehm Moraes and\n                  Jos{\\'{e}} Palma and\n                  Leandro M{\\"{o}}ller and\n                  Ney Laert Vilar Calazans},\n  title        = {Remote and Partial Reconfiguration of FPGAs: Tools and Trends},\n  booktitle    = {17th International Parallel and Distributed Processing Symposium {(IPDPS}\n                  2003), 22-26 April 2003, Nice, France, CD-ROM/Abstracts Proceedings},\n  pages        = {177},\n  publisher    = {{IEEE} Computer Society},\n  year         = {2003},\n  url          = {https://doi.org/10.1109/IPDPS.2003.1213326},\n  doi          = {10.1109/IPDPS.2003.1213326},\n  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},\n  biburl       = {https://dblp.org/rec/conf/ipps/MesquitaMPMC03.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Exploiting reconfigurability for low-power control of embedded processors.\n \n \n \n \n\n\n \n Carro, L.; de Faria Corrêa, E.; Cardozo, R.; Moraes, F.; and Bampi, S.\n\n\n \n\n\n\n In Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pages 421–424, 2003. IEEE\n \n\n\n\n
\n\n\n\n \n \n \"ExploitingPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/iscas/CarroCCMB03,\n  author       = {Luigi Carro and\n                  Edgard de Faria Corr{\\^{e}}a and\n                  R. Cardozo and\n                  Fernando Moraes and\n                  Sergio Bampi},\n  title        = {Exploiting reconfigurability for low-power control of embedded processors},\n  booktitle    = {Proceedings of the 2003 International Symposium on Circuits and Systems,\n                  {ISCAS} 2003, Bangkok, Thailand, May 25-28, 2003},\n  pages        = {421--424},\n  publisher    = {{IEEE}},\n  year         = {2003},\n  url          = {https://doi.org/10.1109/ISCAS.2003.1206303},\n  doi          = {10.1109/ISCAS.2003.1206303},\n  timestamp    = {Sun, 02 Oct 2022 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/conf/iscas/CarroCCMB03.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Design and Prototyping of Direct Torque Control of Induction Motors in FPGAs.\n \n \n \n \n\n\n \n Ferreira, S. B.; Haffner, J. F.; Pereira, L. F. A.; and Moraes, F.\n\n\n \n\n\n\n In Proceedings of the 16th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2003, Sao Paulo, Brazil, September 8-11, 2003, pages 105–110, 2003. IEEE Computer Society\n \n\n\n\n
\n\n\n\n \n \n \"DesignPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/sbcci/FerreiraHPM03,\n  author       = {Sandro Binsfeld Ferreira and\n                  Jos{\\'{e}} Felipe Haffner and\n                  Lu{\\'{\\i}}s Fernando Alves Pereira and\n                  Fernando Moraes},\n  title        = {Design and Prototyping of Direct Torque Control of Induction Motors\n                  in FPGAs},\n  booktitle    = {Proceedings of the 16th Annual Symposium on Integrated Circuits and\n                  Systems Design, {SBCCI} 2003, Sao Paulo, Brazil, September 8-11, 2003},\n  pages        = {105--110},\n  publisher    = {{IEEE} Computer Society},\n  year         = {2003},\n  url          = {https://doi.org/10.1109/SBCCI.2003.1232814},\n  doi          = {10.1109/SBCCI.2003.1232814},\n  timestamp    = {Sun, 02 Oct 2022 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/conf/sbcci/FerreiraHPM03.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n From VHDL Register Transfer Level to SystemC Transaction Level Modeling: A Comparative Case Study.\n \n \n \n \n\n\n \n Calazans, N. L. V.; Moreno, E. I.; Hessel, F.; da Rosa, V. M.; Moraes, F.; and Carara, E.\n\n\n \n\n\n\n In Proceedings of the 16th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2003, Sao Paulo, Brazil, September 8-11, 2003, pages 355, 2003. IEEE Computer Society\n \n\n\n\n
\n\n\n\n \n \n \"FromPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/sbcci/CalazansMHRMC03,\n  author       = {Ney Laert Vilar Calazans and\n                  Edson I. Moreno and\n                  Fabiano Hessel and\n                  Vitor M. da Rosa and\n                  Fernando Moraes and\n                  Everton Carara},\n  title        = {From {VHDL} Register Transfer Level to SystemC Transaction Level Modeling:\n                  {A} Comparative Case Study},\n  booktitle    = {Proceedings of the 16th Annual Symposium on Integrated Circuits and\n                  Systems Design, {SBCCI} 2003, Sao Paulo, Brazil, September 8-11, 2003},\n  pages        = {355},\n  publisher    = {{IEEE} Computer Society},\n  year         = {2003},\n  url          = {https://doi.org/10.1109/SBCCI.2003.1232853},\n  doi          = {10.1109/SBCCI.2003.1232853},\n  timestamp    = {Sun, 02 Oct 2022 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/conf/sbcci/CalazansMHRMC03.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Software-Based Test for Nonprogrammable Cores in Bus-Based System-On-Chip Architectures.\n \n \n \n \n\n\n \n Amory, A. M.; Oliveira, L. A.; and Moraes, F. G.\n\n\n \n\n\n\n In Glesner, M.; da Luz Reis, R. A.; Indrusiak, L. S.; III, V. J. M.; and Eveking, H., editor(s), VLSI-SOC: From Systems to Chips - IFIP TC 10/ WG 10.5 Twelfth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC 2003), December 1-3, 2003, Darmstadt, Germany, volume 200, of IFIP, pages 165–179, 2003. Springer\n \n\n\n\n
\n\n\n\n \n \n \"Software-BasedPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
\n
@inproceedings{DBLP:conf/vlsi/AmoryOM03a,\n  author       = {Alexandre M. Amory and\n                  Leandro A. Oliveira and\n                  Fernando Gehm Moraes},\n  editor       = {Manfred Glesner and\n                  Ricardo Augusto da Luz Reis and\n                  Leandro Soares Indrusiak and\n                  Vincent John Mooney III and\n                  Hans Eveking},\n  title        = {Software-Based Test for Nonprogrammable Cores in Bus-Based System-On-Chip\n                  Architectures},\n  booktitle    = {{VLSI-SOC:} From Systems to Chips - {IFIP} {TC} 10/ {WG} 10.5 Twelfth\n                  International Conference on Very Large Scale Integration of System\n                  on Chip (VLSI-SoC 2003), December 1-3, 2003, Darmstadt, Germany},\n  series       = {{IFIP}},\n  volume       = {200},\n  pages        = {165--179},\n  publisher    = {Springer},\n  year         = {2003},\n  url          = {https://doi.org/10.1007/0-387-33403-3\\_11},\n  doi          = {10.1007/0-387-33403-3\\_11},\n  timestamp    = {Wed, 25 Sep 2019 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/conf/vlsi/AmoryOM03a.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n Software-Based Test for Non-Programmable Cores in Bus-Based System-on-Chip Architectures.\n \n \n \n\n\n \n Amory, A. M.; Oliveira, L. A.; and Moraes, F. G.\n\n\n \n\n\n\n In Glesner, M.; da Luz Reis, R. A.; Eveking, H.; III, V. J. M.; Indrusiak, L. S.; and Zipf, P., editor(s), IFIP VLSI-SoC 2003, IFIP WG 10.5 International Conference on Very Large Scale Integration of System-on-Chip, Darmstadt, Germany, 1-3 December 2003, pages 174–179, 2003. Technische Universität Darmstadt, Insitute of Microelectronic Systems\n \n\n\n\n
\n\n\n\n \n\n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/vlsi/AmoryOM03,\n  author       = {Alexandre M. Amory and\n                  Leandro A. Oliveira and\n                  Fernando Gehm Moraes},\n  editor       = {Manfred Glesner and\n                  Ricardo Augusto da Luz Reis and\n                  Hans Eveking and\n                  Vincent John Mooney III and\n                  Leandro Soares Indrusiak and\n                  Peter Zipf},\n  title        = {Software-Based Test for Non-Programmable Cores in Bus-Based System-on-Chip\n                  Architectures},\n  booktitle    = {{IFIP} VLSI-SoC 2003, {IFIP} {WG} 10.5 International Conference on\n                  Very Large Scale Integration of System-on-Chip, Darmstadt, Germany,\n                  1-3 December 2003},\n  pages        = {174--179},\n  publisher    = {Technische Universit{\\"{a}}t Darmstadt, Insitute of Microelectronic\n                  Systems},\n  year         = {2003},\n  timestamp    = {Thu, 07 Oct 2004 09:29:26 +0200},\n  biburl       = {https://dblp.org/rec/conf/vlsi/AmoryOM03.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n Are coarse grain reconfigurable architectures suitable for cryptography?.\n \n \n \n\n\n \n Mesquita, D.; Torres, L.; Moraes, F. G.; Sassatelli, G.; and Robert, M.\n\n\n \n\n\n\n In Glesner, M.; da Luz Reis, R. A.; Eveking, H.; III, V. J. M.; Indrusiak, L. S.; and Zipf, P., editor(s), IFIP VLSI-SoC 2003, IFIP WG 10.5 International Conference on Very Large Scale Integration of System-on-Chip, Darmstadt, Germany, 1-3 December 2003, pages 276–281, 2003. Technische Universität Darmstadt, Insitute of Microelectronic Systems\n \n\n\n\n
\n\n\n\n \n\n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/vlsi/MesquitaTMSR03,\n  author       = {Daniel Mesquita and\n                  Lionel Torres and\n                  Fernando Gehm Moraes and\n                  Gilles Sassatelli and\n                  Michel Robert},\n  editor       = {Manfred Glesner and\n                  Ricardo Augusto da Luz Reis and\n                  Hans Eveking and\n                  Vincent John Mooney III and\n                  Leandro Soares Indrusiak and\n                  Peter Zipf},\n  title        = {Are coarse grain reconfigurable architectures suitable for cryptography?},\n  booktitle    = {{IFIP} VLSI-SoC 2003, {IFIP} {WG} 10.5 International Conference on\n                  Very Large Scale Integration of System-on-Chip, Darmstadt, Germany,\n                  1-3 December 2003},\n  pages        = {276--281},\n  publisher    = {Technische Universit{\\"{a}}t Darmstadt, Insitute of Microelectronic\n                  Systems},\n  year         = {2003},\n  timestamp    = {Thu, 22 Jan 2004 00:00:00 +0100},\n  biburl       = {https://dblp.org/rec/conf/vlsi/MesquitaTMSR03.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n A Low Area Overhead Packet-switched Network on Chip: Architecture and Prototyping.\n \n \n \n\n\n \n Moraes, F. G.; Mello, A.; Möller, L.; Ost, L.; and Calazans, N. L. V.\n\n\n \n\n\n\n In Glesner, M.; da Luz Reis, R. A.; Eveking, H.; III, V. J. M.; Indrusiak, L. S.; and Zipf, P., editor(s), IFIP VLSI-SoC 2003, IFIP WG 10.5 International Conference on Very Large Scale Integration of System-on-Chip, Darmstadt, Germany, 1-3 December 2003, pages 318–323, 2003. Technische Universität Darmstadt, Insitute of Microelectronic Systems\n \n\n\n\n
\n\n\n\n \n\n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/vlsi/MoraesMMOC03,\n  author       = {Fernando Gehm Moraes and\n                  Aline Mello and\n                  Leandro M{\\"{o}}ller and\n                  Luciano Ost and\n                  Ney Laert Vilar Calazans},\n  editor       = {Manfred Glesner and\n                  Ricardo Augusto da Luz Reis and\n                  Hans Eveking and\n                  Vincent John Mooney III and\n                  Leandro Soares Indrusiak and\n                  Peter Zipf},\n  title        = {A Low Area Overhead Packet-switched Network on Chip: Architecture\n                  and Prototyping},\n  booktitle    = {{IFIP} VLSI-SoC 2003, {IFIP} {WG} 10.5 International Conference on\n                  Very Large Scale Integration of System-on-Chip, Darmstadt, Germany,\n                  1-3 December 2003},\n  pages        = {318--323},\n  publisher    = {Technische Universit{\\"{a}}t Darmstadt, Insitute of Microelectronic\n                  Systems},\n  year         = {2003},\n  timestamp    = {Fri, 10 Jun 2022 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/conf/vlsi/MoraesMMOC03.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n  \n 2002\n \n \n (4)\n \n \n
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\n \n\n \n \n \n \n \n \n Prototyping of embedded digital systems from SDL language: a case study.\n \n \n \n \n\n\n \n Marcon, C. A. M.; Hessel, F.; Amory, A. M.; Ries, L. H. L.; Moraes, F. G.; and Calazans, N. L. V.\n\n\n \n\n\n\n In Seventh IEEE International High-Level Design Validation and Test Workshop 2002, Cannes, France, October 27-29, 2002, pages 133–138, 2002. IEEE Computer Society\n \n\n\n\n
\n\n\n\n \n \n \"PrototypingPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/hldvt/MarconHARMC02,\n  author       = {C{\\'{e}}sar A. M. Marcon and\n                  Fabiano Hessel and\n                  Alexandre M. Amory and\n                  Luis H. L. Ries and\n                  Fernando Gehm Moraes and\n                  Ney Laert Vilar Calazans},\n  title        = {Prototyping of embedded digital systems from {SDL} language: a case\n                  study},\n  booktitle    = {Seventh {IEEE} International High-Level Design Validation and Test\n                  Workshop 2002, Cannes, France, October 27-29, 2002},\n  pages        = {133--138},\n  publisher    = {{IEEE} Computer Society},\n  year         = {2002},\n  url          = {https://doi.org/10.1109/HLDVT.2002.1224442},\n  doi          = {10.1109/HLDVT.2002.1224442},\n  timestamp    = {Thu, 23 Mar 2023 00:00:00 +0100},\n  biburl       = {https://dblp.org/rec/conf/hldvt/MarconHARMC02.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n A Heterogeneous and Distributed Co-Simulation Environment.\n \n \n \n \n\n\n \n Amory, A. M.; Moraes, F.; Oliveira, L. A.; Calazans, N.; and Hessel, F.\n\n\n \n\n\n\n In Proceedings of the 15th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2002, Porto Alegre, Brazil, September 9-14, 2002, pages 115–120, 2002. IEEE Computer Society\n \n\n\n\n
\n\n\n\n \n \n \"APaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/sbcci/Amory0OCH02,\n  author       = {Alexandre M. Amory and\n                  Fernando Moraes and\n                  Leandro A. Oliveira and\n                  Ney Calazans and\n                  Fabiano Hessel},\n  title        = {A Heterogeneous and Distributed Co-Simulation Environment},\n  booktitle    = {Proceedings of the 15th Annual Symposium on Integrated Circuits and\n                  Systems Design, {SBCCI} 2002, Porto Alegre, Brazil, September 9-14,\n                  2002},\n  pages        = {115--120},\n  publisher    = {{IEEE} Computer Society},\n  year         = {2002},\n  url          = {https://dl.acm.org/doi/10.5555/827246.827374},\n  doi          = {10.5555/827246.827374},\n  timestamp    = {Fri, 10 Jun 2022 11:12:41 +0200},\n  biburl       = {https://dblp.org/rec/conf/sbcci/Amory0OCH02.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Core Communication Interface for FPGAs.\n \n \n \n \n\n\n \n Palma, J. C. S.; de Mello, A. V.; Möller, L.; Moraes, F.; and Calazans, N.\n\n\n \n\n\n\n In Proceedings of the 15th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2002, Porto Alegre, Brazil, September 9-14, 2002, pages 183–190, 2002. IEEE Computer Society\n \n\n\n\n
\n\n\n\n \n \n \"CorePaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/sbcci/PalmaMM0C02,\n  author       = {Jos{\\'{e}} Carlos S. Palma and\n                  Aline Vieira de Mello and\n                  Leandro M{\\"{o}}ller and\n                  Fernando Moraes and\n                  Ney Calazans},\n  title        = {Core Communication Interface for FPGAs},\n  booktitle    = {Proceedings of the 15th Annual Symposium on Integrated Circuits and\n                  Systems Design, {SBCCI} 2002, Porto Alegre, Brazil, September 9-14,\n                  2002},\n  pages        = {183--190},\n  publisher    = {{IEEE} Computer Society},\n  year         = {2002},\n  url          = {https://dl.acm.org/doi/10.5555/827246.827400},\n  doi          = {10.5555/827246.827400},\n  timestamp    = {Fri, 10 Jun 2022 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/conf/sbcci/PalmaMM0C02.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Requirements, Primitives and Models for Systems Specification.\n \n \n \n \n\n\n \n Marcon, C. A. M.; Calazans, N. L. V.; and Moraes, F. G.\n\n\n \n\n\n\n In Proceedings of the 15th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2002, Porto Alegre, Brazil, September 9-14, 2002, pages 323–330, 2002. IEEE Computer Society\n \n\n\n\n
\n\n\n\n \n \n \"Requirements,Paper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/sbcci/MarconCM02,\n  author       = {C{\\'{e}}sar Augusto Missio Marcon and\n                  Ney Laert Vilar Calazans and\n                  Fernando Gehm Moraes},\n  title        = {Requirements, Primitives and Models for Systems Specification},\n  booktitle    = {Proceedings of the 15th Annual Symposium on Integrated Circuits and\n                  Systems Design, {SBCCI} 2002, Porto Alegre, Brazil, September 9-14,\n                  2002},\n  pages        = {323--330},\n  publisher    = {{IEEE} Computer Society},\n  year         = {2002},\n  url          = {https://dl.acm.org/doi/10.5555/827246.827355},\n  doi          = {10.5555/827246.827355},\n  timestamp    = {Fri, 10 Jun 2022 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/conf/sbcci/MarconCM02.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n  \n 2001\n \n \n (4)\n \n \n
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\n \n\n \n \n \n \n \n Projeto para Prototipação de um IP Soft Core MAC Ethernet.\n \n \n \n\n\n \n Calazans, N. L. V.; Moraes, F. G.; Torok, D. L.; and Andreoli, A. V.\n\n\n \n\n\n\n RITA, 8(1): 23–41. 2001.\n \n\n\n\n
\n\n\n\n \n\n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@article{DBLP:journals/rita/CalazansMTA01,\n  author       = {Ney Laert Vilar Calazans and\n                  Fernando Gehm Moraes and\n                  Delfim Luiz Torok and\n                  Andrey V. Andreoli},\n  title        = {Projeto para Prototipa{\\c{c}}{\\~{a}}o de um {IP} Soft Core {MAC} Ethernet},\n  journal      = {{RITA}},\n  volume       = {8},\n  number       = {1},\n  pages        = {23--41},\n  year         = {2001},\n  timestamp    = {Mon, 24 May 2004 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/journals/rita/CalazansMTA01.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Integrating the teaching of computer organization and architecture with digital hardware design early in undergraduate courses.\n \n \n \n \n\n\n \n Calazans, N. L. V.; and Moraes, F. G.\n\n\n \n\n\n\n IEEE Trans. Educ., 44(2): 109–119. 2001.\n \n\n\n\n
\n\n\n\n \n \n \"IntegratingPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@article{DBLP:journals/te/CalazansM01,\n  author       = {Ney Laert Vilar Calazans and\n                  Fernando Gehm Moraes},\n  title        = {Integrating the teaching of computer organization and architecture\n                  with digital hardware design early in undergraduate courses},\n  journal      = {{IEEE} Trans. Educ.},\n  volume       = {44},\n  number       = {2},\n  pages        = {109--119},\n  year         = {2001},\n  url          = {https://doi.org/10.1109/13.925805},\n  doi          = {10.1109/13.925805},\n  timestamp    = {Sun, 02 Oct 2022 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/journals/te/CalazansM01.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Using the CAN Protocol and Reconfigurable Computing Technology for Web-Based Smart House Auto.\n \n \n \n \n\n\n \n Moraes, F.; Amory, A. M.; Calazans, N.; Bezerra, E.; and Petrini, J.\n\n\n \n\n\n\n In Proceedings of the 14th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2001, Pirenopolis, Brazil, September 10-15, 2001, pages 38–43, 2001. IEEE Computer Society\n \n\n\n\n
\n\n\n\n \n \n \"UsingPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
\n
@inproceedings{DBLP:conf/sbcci/0001AC0P01,\n  author       = {Fernando Moraes and\n                  Alexandre M. Amory and\n                  Ney Calazans and\n                  Eduardo Bezerra and\n                  Juracy Petrini},\n  title        = {Using the {CAN} Protocol and Reconfigurable Computing Technology for\n                  Web-Based Smart House Auto},\n  booktitle    = {Proceedings of the 14th Annual Symposium on Integrated Circuits and\n                  Systems Design, {SBCCI} 2001, Pirenopolis, Brazil, September 10-15,\n                  2001},\n  pages        = {38--43},\n  publisher    = {{IEEE} Computer Society},\n  year         = {2001},\n  url          = {https://dl.acm.org/doi/10.5555/882483.883919},\n  doi          = {10.5555/882483.883919},\n  timestamp    = {Fri, 03 Jun 2022 10:49:44 +0200},\n  biburl       = {https://dblp.org/rec/conf/sbcci/0001AC0P01.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Interconnection Length Estimation at Logic-Level.\n \n \n \n \n\n\n \n dos Santos Martins, J. B.; Moraes, F.; and Reis, R.\n\n\n \n\n\n\n In Proceedings of the 14th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2001, Pirenopolis, Brazil, September 10-15, 2001, pages 98–102, 2001. IEEE Computer Society\n \n\n\n\n
\n\n\n\n \n \n \"InterconnectionPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/sbcci/Martins0001,\n  author       = {Jo{\\~{a}}o Baptista dos Santos Martins and\n                  Fernando Moraes and\n                  Ricardo Reis},\n  title        = {Interconnection Length Estimation at Logic-Level},\n  booktitle    = {Proceedings of the 14th Annual Symposium on Integrated Circuits and\n                  Systems Design, {SBCCI} 2001, Pirenopolis, Brazil, September 10-15,\n                  2001},\n  pages        = {98--102},\n  publisher    = {{IEEE} Computer Society},\n  year         = {2001},\n  url          = {https://dl.acm.org/doi/10.5555/882483.883900},\n  doi          = {10.5555/882483.883900},\n  timestamp    = {Fri, 03 Jun 2022 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/conf/sbcci/Martins0001.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n  \n 2000\n \n \n (3)\n \n \n
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\n \n\n \n \n \n \n \n \n WTROPIC: A WWW-Based Macro-Cell Generator.\n \n \n \n \n\n\n \n Fragoso, J. L.; Moraes, F.; and Reis, R.\n\n\n \n\n\n\n In Proceedings of the 13th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2000, Manaus, Brazil, September 18-24, 2000, pages 133–138, 2000. IEEE Computer Society\n \n\n\n\n
\n\n\n\n \n \n \"WTROPIC:Paper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/sbcci/Fragoso0000,\n  author       = {Jo{\\~{a}}o Leonardo Fragoso and\n                  Fernando Moraes and\n                  Ricardo Reis},\n  title        = {{WTROPIC:} {A} WWW-Based Macro-Cell Generator},\n  booktitle    = {Proceedings of the 13th Annual Symposium on Integrated Circuits and\n                  Systems Design, {SBCCI} 2000, Manaus, Brazil, September 18-24, 2000},\n  pages        = {133--138},\n  publisher    = {{IEEE} Computer Society},\n  year         = {2000},\n  url          = {https://dl.acm.org/doi/10.5555/827245.827330},\n  doi          = {10.5555/827245.827330},\n  timestamp    = {Fri, 03 Jun 2022 10:50:13 +0200},\n  biburl       = {https://dblp.org/rec/conf/sbcci/Fragoso0000.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n Design of a Classification System for Rectangular Shapes Using a Co-Design Environment.\n \n \n \n \n\n\n \n Molz, R. F.; Engel, P. M.; Moraes, F. G.; Torres, L.; and Robert, M.\n\n\n \n\n\n\n In Proceedings of the 13th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2000, Manaus, Brazil, September 18-24, 2000, pages 281–288, 2000. IEEE Computer Society\n \n\n\n\n
\n\n\n\n \n \n \"DesignPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/sbcci/MolzEMTR00,\n  author       = {Rolf Fredi Molz and\n                  Paulo Martins Engel and\n                  Fernando Gehm Moraes and\n                  Lionel Torres and\n                  Michel Robert},\n  title        = {Design of a Classification System for Rectangular Shapes Using a Co-Design\n                  Environment},\n  booktitle    = {Proceedings of the 13th Annual Symposium on Integrated Circuits and\n                  Systems Design, {SBCCI} 2000, Manaus, Brazil, September 18-24, 2000},\n  pages        = {281--288},\n  publisher    = {{IEEE} Computer Society},\n  year         = {2000},\n  url          = {https://dl.acm.org/doi/10.5555/827245.827324},\n  doi          = {10.5555/827245.827324},\n  timestamp    = {Thu, 02 Jun 2022 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/conf/sbcci/MolzEMTR00.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n \n\n \n \n \n \n \n \n LASCA-Interconnect Parasitic Extraction Tool for Deep-Submicron IC Design.\n \n \n \n \n\n\n \n Ferreira, F. K.; Moraes, F.; and Reis, R.\n\n\n \n\n\n\n In Proceedings of the 13th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2000, Manaus, Brazil, September 18-24, 2000, pages 327–332, 2000. IEEE Computer Society\n \n\n\n\n
\n\n\n\n \n \n \"LASCA-InterconnectPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/sbcci/Ferreira0000,\n  author       = {F. K. Ferreira and\n                  Fernando Moraes and\n                  Ricardo Reis},\n  title        = {LASCA-Interconnect Parasitic Extraction Tool for Deep-Submicron {IC}\n                  Design},\n  booktitle    = {Proceedings of the 13th Annual Symposium on Integrated Circuits and\n                  Systems Design, {SBCCI} 2000, Manaus, Brazil, September 18-24, 2000},\n  pages        = {327--332},\n  publisher    = {{IEEE} Computer Society},\n  year         = {2000},\n  url          = {https://dl.acm.org/doi/10.5555/827245.827294},\n  doi          = {10.5555/827245.827294},\n  timestamp    = {Thu, 02 Jun 2022 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/conf/sbcci/Ferreira0000.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n  \n 1999\n \n \n (1)\n \n \n
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\n \n\n \n \n \n \n \n A Virtual CMOS Library Approach for East Layout Synthesis.\n \n \n \n\n\n \n Moraes, F.; Robert, M.; and Auvergne, D.\n\n\n \n\n\n\n In Silveira, L. M.; Devadas, S.; and da Luz Reis, R. A., editor(s), VLSI: Systems on a Chip, IFIP TC10/WG10.5 Tenth International Conference on Very Large Scale Integration (VLSI '99), December 1-4, 1999, Lisbon, Portugal, volume 162, of IFIP Conference Proceedings, pages 415–426, 1999. Kluwer\n \n\n\n\n
\n\n\n\n \n\n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/ifip10-5/MoraesRA99,\n  author       = {Fernando Moraes and\n                  Michel Robert and\n                  Daniel Auvergne},\n  editor       = {L. Miguel Silveira and\n                  Srinivas Devadas and\n                  Ricardo Augusto da Luz Reis},\n  title        = {A Virtual {CMOS} Library Approach for East Layout Synthesis},\n  booktitle    = {{VLSI:} Systems on a Chip, {IFIP} {TC10/WG10.5} Tenth International\n                  Conference on Very Large Scale Integration {(VLSI} '99), December\n                  1-4, 1999, Lisbon, Portugal},\n  series       = {{IFIP} Conference Proceedings},\n  volume       = {162},\n  pages        = {415--426},\n  publisher    = {Kluwer},\n  year         = {1999},\n  timestamp    = {Tue, 10 Mar 2020 00:00:00 +0100},\n  biburl       = {https://dblp.org/rec/conf/ifip10-5/MoraesRA99.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n  \n 1998\n \n \n (1)\n \n \n
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\n \n\n \n \n \n \n \n \n An Improved Path Enumeration Method Considering Different Fall and Rise Gate Delays.\n \n \n \n \n\n\n \n Güntzel, J. L.; Pinto, A. C. M.; Moraes, F.; and Reis, R.\n\n\n \n\n\n\n In Proceedings of the 11th Annual Symposium on Integrated Circuits Design, SBCCI 1998, Rio de Janiero, Brazil, September 30 - October 2, 1998, pages 208–212, 1998. IEEE Computer Society\n \n\n\n\n
\n\n\n\n \n \n \"AnPaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/sbcci/X98a,\n  author       = {Jos{\\'{e}} Lu{\\'{\\i}}s G{\\"{u}}ntzel and\n                  Ana Cristina Medina Pinto and\n                  Fernando Moraes and\n                  Ricardo Reis},\n  title        = {An Improved Path Enumeration Method Considering Different Fall and\n                  Rise Gate Delays},\n  booktitle    = {Proceedings of the 11th Annual Symposium on Integrated Circuits Design,\n                  {SBCCI} 1998, Rio de Janiero, Brazil, September 30 - October 2, 1998},\n  pages        = {208--212},\n  publisher    = {{IEEE} Computer Society},\n  year         = {1998},\n  url          = {https://doi.ieeecomputersociety.org/10.1109/SBCCI.1998.715443},\n  doi          = {10.1109/SBCCI.1998.715443},\n  timestamp    = {Tue, 25 Jul 2023 01:00:00 +0200},\n  biburl       = {https://dblp.org/rec/conf/sbcci/X98a.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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\n  \n 1994\n \n \n (1)\n \n \n
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\n \n\n \n \n \n \n \n \n Influence of Locig Block Layout Architecture on FPGA Performance.\n \n \n \n \n\n\n \n Robert, M.; Torres, L.; Moraes, F.; and Auvergne, D.\n\n\n \n\n\n\n In Hartenstein, R. W.; and Servít, M., editor(s), Field-Programmable Logic, Architectures, Synthesis and Applications, 4th International Workshop on Field-Programmable Logic and Applications, FPL '94, Prague, Czech Republic, September 7-9, 1994, Proceedings, volume 849, of Lecture Notes in Computer Science, pages 34–44, 1994. Springer\n \n\n\n\n
\n\n\n\n \n \n \"InfluencePaper\n  \n \n\n \n \n doi\n  \n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@inproceedings{DBLP:conf/fpl/RobertTMA94,\n  author       = {Michel Robert and\n                  Lionel Torres and\n                  Fernando Moraes and\n                  Daniel Auvergne},\n  editor       = {Reiner W. Hartenstein and\n                  Michal Serv{\\'{\\i}}t},\n  title        = {Influence of Locig Block Layout Architecture on {FPGA} Performance},\n  booktitle    = {Field-Programmable Logic, Architectures, Synthesis and Applications,\n                  4th International Workshop on Field-Programmable Logic and Applications,\n                  {FPL} '94, Prague, Czech Republic, September 7-9, 1994, Proceedings},\n  series       = {Lecture Notes in Computer Science},\n  volume       = {849},\n  pages        = {34--44},\n  publisher    = {Springer},\n  year         = {1994},\n  url          = {https://doi.org/10.1007/3-540-58419-6\\_67},\n  doi          = {10.1007/3-540-58419-6\\_67},\n  timestamp    = {Tue, 10 Mar 2020 00:00:00 +0100},\n  biburl       = {https://dblp.org/rec/conf/fpl/RobertTMA94.bib},\n  bibsource    = {dblp computer science bibliography, https://dblp.org}\n}\n\n
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