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\n  \n 2024\n \n \n (5)\n \n \n
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\n \n\n \n \n \n \n \n In-Memory Wallace Tree Multipliers Based on Majority Gates Within Voltage-Gated SOT-MRAM Crossbar Arrays.\n \n \n \n\n\n \n Hui, Y.; Li, Q.; Wang, L.; Liu, C.; Zhang, D.; and Miao, X.\n\n\n \n\n\n\n IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2024.\n \n\n\n\n
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@article{hui2024memory,\n  title={In-Memory Wallace Tree Multipliers Based on Majority Gates Within Voltage-Gated SOT-MRAM Crossbar Arrays},\n  author={Hui, Yajuan and Li, Qingzhen and Wang, Leimin and Liu, Cheng and Zhang, Deming and Miao, Xiangshui},\n  journal={IEEE Transactions on Very Large Scale Integration (VLSI) Systems},\n  year={2024},\n  publisher={IEEE}\n}\n\n
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\n \n\n \n \n \n \n \n Advancements in Accelerating Deep Neural Network Inference on AIoT Devices: A Survey.\n \n \n \n\n\n \n Cheng, L.; Gu, Y.; Liu, Q.; Yang, L.; Liu, C.; and Wang, Y.\n\n\n \n\n\n\n IEEE Transactions on Sustainable Computing. 2024.\n \n\n\n\n
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@article{cheng2024advancements,\n  title={Advancements in Accelerating Deep Neural Network Inference on AIoT Devices: A Survey},\n  author={Cheng, Long and Gu, Yan and Liu, Qingzhi and Yang, Lei and Liu, Cheng and Wang, Ying},\n  journal={IEEE Transactions on Sustainable Computing},\n  year={2024},\n  publisher={IEEE}\n}\n\n
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\n \n\n \n \n \n \n \n An Energy-Efficient In-Memory Accelerator for Graph Construction and Updating.\n \n \n \n\n\n \n Chen, M.; Liu, C.; Liang, S.; He, L.; Wang, Y.; Zhang, L.; Li, H.; and Li, X.\n\n\n \n\n\n\n IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 2024.\n \n\n\n\n
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@article{chen2024energy,\n  title={An Energy-Efficient In-Memory Accelerator for Graph Construction and Updating},\n  author={Chen, Mingkai and Liu, Cheng and Liang, Shengwen and He, Lei and Wang, Ying and Zhang, Lei and Li, Huawei and Li, Xiaowei},\n  journal={IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems},\n  year={2024},\n  publisher={IEEE}\n}\n\n
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\n \n\n \n \n \n \n \n MRFI: An Open Source Multi-Resolution Fault Injection Framework for Neural Network Processing.\n \n \n \n\n\n \n Huang, H.; Liu, C.; Liu, B.; Li, H.; and Li, X.\n\n\n \n\n\n\n IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2024.\n \n\n\n\n
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@article{huang2024mrfi,\n  title={MRFI: An Open Source Multi-Resolution Fault Injection Framework for Neural Network Processing},\n  author={Huang, Haitong and Liu, Cheng and Liu, Bo and Li, Huawei and Li, Xiaowei},\n  journal={IEEE Transactions on Very Large Scale Integration (VLSI) Systems},\n  year={2024},\n  publisher={IEEE}\n}\n\n
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\n \n\n \n \n \n \n \n 容错深度学习加速器跨层优化.\n \n \n \n\n\n \n 张青; 刘成; 刘波; 黄海同; 王颖; 李华伟; and 李晓维\n\n\n \n\n\n\n 计算机研究与发展. 2024.\n \n\n\n\n
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@article{zhang2024crosslayer,\n  title={容错深度学习加速器跨层优化},\n  author={张青 and 刘成 and 刘波 and 黄海同 and 王颖 and 李华伟 and 李晓维},\n  journal={计算机研究与发展},\n  year={2024}\n}\n\n\n
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\n  \n 2023\n \n \n (15)\n \n \n
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\n \n\n \n \n \n \n \n Statistical Modeling of Soft Error Influence on Neural Networks.\n \n \n \n\n\n \n Huang, H.; Xue, X.; Liu, C.; Wang, Y.; Luo, T.; Cheng, L.; Li, H.; and Li, X.\n\n\n \n\n\n\n IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 2023.\n \n\n\n\n
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@article{huang2023statistical,\n  title={Statistical Modeling of Soft Error Influence on Neural Networks},\n  author={Huang, Haitong and Xue, Xinghua and Liu, Cheng and Wang, Ying and Luo, Tao and Cheng, Long and Li, Huawei and Li, Xiaowei},\n  journal={IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems},\n  year={2023},\n  publisher={IEEE}\n}\n\n
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\n \n\n \n \n \n \n \n S $^$\\$2$\\$ $ Loop: A Lightweight Spectral-Spatio Loop Closure Detector for Resource-Constrained Platforms.\n \n \n \n\n\n \n He, Y.; Zhang, L.; Liu, C.; Zhang, L.; and Wang, Y.\n\n\n \n\n\n\n IEEE Robotics and Automation Letters, 8(3): 1826–1833. 2023.\n \n\n\n\n
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@article{he2023s,\n  title={S $\\^{}$\\{$2$\\}$ $ Loop: A Lightweight Spectral-Spatio Loop Closure Detector for Resource-Constrained Platforms},\n  author={He, Yuquan and Zhang, Long and Liu, Cheng and Zhang, Lei and Wang, Ying},\n  journal={IEEE Robotics and Automation Letters},\n  volume={8},\n  number={3},\n  pages={1826--1833},\n  year={2023},\n  publisher={IEEE}\n}\n\n
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\n \n\n \n \n \n \n \n ApproxABFT: Approximate algorithm-based fault tolerance for vision transformers.\n \n \n \n\n\n \n Xue, X.; Liu, C.; Huang, H.; Liu, B.; Wang, Y.; Yang, B.; Luo, T.; Zhang, L.; Li, H.; and Li, X.\n\n\n \n\n\n\n arXiv preprint arXiv:2302.10469. 2023.\n \n\n\n\n
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@article{xue2023approxabft,\n  title={ApproxABFT: Approximate algorithm-based fault tolerance for vision transformers},\n  author={Xue, Xinghua and Liu, Cheng and Huang, Haitong and Liu, Bo and Wang, Ying and Yang, Bing and Luo, Tao and Zhang, Lei and Li, Huawei and Li, Xiaowei},\n  journal={arXiv preprint arXiv:2302.10469},\n  year={2023}\n}\n\n
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\n \n\n \n \n \n \n \n MA-BERT: Towards Matrix Arithmetic-only BERT Inference by Eliminating Complex Non-linear Functions.\n \n \n \n\n\n \n Ming, N. W.; Wang, Z.; Liu, C.; Goh, R. S. M.; and Luo, T.\n\n\n \n\n\n\n In The 11th International Conference on Learning Representations (ICLR), 2023. \n \n\n\n\n
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@inproceedings{ming2023ma,\n  title={MA-BERT: Towards Matrix Arithmetic-only BERT Inference by Eliminating Complex Non-linear Functions},\n  author={Ming, Neo Wei and Wang, Zhehui and Liu, Cheng and Goh, Rick Siow Mong and Luo, Tao},\n  booktitle={The 11th International Conference on Learning Representations (ICLR)},\n  year={2023}\n}\n\n
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\n \n\n \n \n \n \n \n Layer-Puzzle: Allocating and Scheduling Multi-task on Multi-core NPUs by Using Layer Heterogeneity.\n \n \n \n\n\n \n Gao, C.; Wang, Y.; Liu, C.; Wang, M.; Chen, W.; Han, Y.; and Zhang, L.\n\n\n \n\n\n\n In 2023 Design, Automation & Test in Europe Conference & Exhibition (DATE), pages 1–6, 2023. IEEE\n \n\n\n\n
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@inproceedings{gao2023layer,\n  title={Layer-Puzzle: Allocating and Scheduling Multi-task on Multi-core NPUs by Using Layer Heterogeneity},\n  author={Gao, Chengsi and Wang, Ying and Liu, Cheng and Wang, Mengdi and Chen, Weiwei and Han, Yinhe and Zhang, Lei},\n  booktitle={2023 Design, Automation \\& Test in Europe Conference \\& Exhibition (DATE)},\n  pages={1--6},\n  year={2023},\n  organization={IEEE}\n}\n\n
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\n \n\n \n \n \n \n \n MRFI: An Open Source Multi-Resolution Fault Injection Framework for Neural Network Processing.\n \n \n \n\n\n \n Huang, H.; Liu, C.; Xue, X.; Wang, Y.; Li, H.; and Li, X.\n\n\n \n\n\n\n arXiv preprint arXiv:2306.11758. 2023.\n \n\n\n\n
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@article{huang2023mrfi,\n  title={MRFI: An Open Source Multi-Resolution Fault Injection Framework for Neural Network Processing},\n  author={Huang, Haitong and Liu, Cheng and Xue, Xinghua and Wang, Ying and Li, Huawei and Li, Xiaowei},\n  journal={arXiv preprint arXiv:2306.11758},\n  year={2023}\n}\n\n
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\n \n\n \n \n \n \n \n Deep Learning Accelerator in Loop Reliability Evaluation for Autonomous Driving.\n \n \n \n\n\n \n Huang, H.; and Liu, C.\n\n\n \n\n\n\n arXiv preprint arXiv:2306.11759. 2023.\n \n\n\n\n
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@article{huang2023deep,\n  title={Deep Learning Accelerator in Loop Reliability Evaluation for Autonomous Driving},\n  author={Huang, Haitong and Liu, Cheng},\n  journal={arXiv preprint arXiv:2306.11759},\n  year={2023}\n}\n\n
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\n \n\n \n \n \n \n \n Built-in Fault-Tolerant Computing Paradigm for Resilient Large-Scale Chip Design A Self-Test, Self-Diagnosis, and Self-Repair-Based Approach.\n \n \n \n\n\n \n Book, P. S.\n\n\n \n\n\n\n . 2023.\n \n\n\n\n
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@article{book2023built,\n  title={Built-in Fault-Tolerant Computing Paradigm for Resilient Large-Scale Chip Design A Self-Test, Self-Diagnosis, and Self-Repair-Based Approach},\n  author={Book, Pre-order Softcover},\n  year={2023}\n}\n\n
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\n \n\n \n \n \n \n \n Exploring Winograd convolution for cost-effective neural network fault tolerance.\n \n \n \n\n\n \n Xue, X.; Liu, C.; Liu, B.; Huang, H.; Wang, Y.; Luo, T.; Zhang, L.; Li, H.; and Li, X.\n\n\n \n\n\n\n IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2023.\n \n\n\n\n
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@article{xue2023exploring,\n  title={Exploring Winograd convolution for cost-effective neural network fault tolerance},\n  author={Xue, Xinghua and Liu, Cheng and Liu, Bo and Huang, Haitong and Wang, Ying and Luo, Tao and Zhang, Lei and Li, Huawei and Li, Xiaowei},\n  journal={IEEE Transactions on Very Large Scale Integration (VLSI) Systems},\n  year={2023},\n  publisher={IEEE}\n}\n\n
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\n \n\n \n \n \n \n \n Soft Error Reliability Analysis of Vision Transformers.\n \n \n \n\n\n \n Xue, X.; Liu, C.; Wang, Y.; Yang, B.; Luo, T.; Zhang, L.; Li, H.; and Li, X.\n\n\n \n\n\n\n IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2023.\n \n\n\n\n
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@article{xue2023soft,\n  title={Soft Error Reliability Analysis of Vision Transformers},\n  author={Xue, Xinghua and Liu, Cheng and Wang, Ying and Yang, Bing and Luo, Tao and Zhang, Lei and Li, Huawei and Li, Xiaowei},\n  journal={IEEE Transactions on Very Large Scale Integration (VLSI) Systems},\n  year={2023},\n  publisher={IEEE}\n}\n\n
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\n \n\n \n \n \n \n \n A deep reinforcement learning-based preemptive approach for cost-aware cloud job scheduling.\n \n \n \n\n\n \n Cheng, L.; Wang, Y.; Cheng, F.; Liu, C.; Zhao, Z.; and Wang, Y.\n\n\n \n\n\n\n IEEE Transactions on Sustainable Computing. 2023.\n \n\n\n\n
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@article{cheng2023deep,\n  title={A deep reinforcement learning-based preemptive approach for cost-aware cloud job scheduling},\n  author={Cheng, Long and Wang, Yue and Cheng, Feng and Liu, Cheng and Zhao, Zhiming and Wang, Ying},\n  journal={IEEE Transactions on Sustainable Computing},\n  year={2023},\n  publisher={IEEE}\n}\n\n
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\n \n\n \n \n \n \n \n Logic-in-Memory Based on Majority Gates With Voltage-Gated SOT-MRAM Crossbar Arrays.\n \n \n \n\n\n \n Hui, Y.; Li, Q.; Liu, C.; Zhang, D.; and Miao, X.\n\n\n \n\n\n\n IEEE Transactions on Circuits and Systems II: Express Briefs,1–6. 2023.\n \n\n\n\n
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@article{hui2023logic,\n  title={Logic-in-Memory Based on Majority Gates With Voltage-Gated SOT-MRAM Crossbar Arrays},\n  author={Hui, Yajuan and Li, Qingzhen and Liu, Cheng and Zhang, Deming and Miao, Xiangshui},\n  journal={IEEE Transactions on Circuits and Systems II: Express Briefs},\n  pages={1--6},\n  year={2023},\n  publisher={IEEE}\n}\n\n
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\n \n\n \n \n \n \n \n PDG: A Prefetcher for Dynamic Graph Updating.\n \n \n \n\n\n \n Zhang, X.; Liu, C.; Ni, J.; Cheng, Y.; Zhang, L.; Li, H.; and Li, X.\n\n\n \n\n\n\n IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,1–14. 2023.\n \n\n\n\n
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@article{zhang2023pdg,\n  title={PDG: A Prefetcher for Dynamic Graph Updating},\n  author={Zhang, Xinmiao and Liu, Cheng and Ni, Jiacheng and Cheng, Yuanqing and Zhang, Lei and Li, Huawei and Li, Xiaowei},\n  journal={IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems},\n  pages={1--14},\n  year={2023},\n  publisher={IEEE}\n}\n\n
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\n \n\n \n \n \n \n \n Cross-Layer Optimization for Fault-Tolerant Deep Learning.\n \n \n \n\n\n \n Zhang, Q.; Liu, C.; Liu, B.; Huang, H.; Wang, Y.; Li, H.; and Li, X.\n\n\n \n\n\n\n In The 4th CCF Integrated Circuit Design and Automation Conference, pages 1–16, 2023. CCF\n \n\n\n\n
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@inproceedings{zhang2023cross,\n  title={Cross-Layer Optimization for Fault-Tolerant Deep Learning},\n  author={Zhang, Qing and Liu, Cheng and Liu, Bo and Huang, Haitong and Wang, Ying and Li, Huawei and Li, Xiaowei},\n  booktitle={The 4th CCF Integrated Circuit Design and Automation Conference},\n  pages={1--16},\n  year={2023},\n  organization={CCF}\n}\n\n
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\n \n\n \n \n \n \n \n DeepBurning-MixQ: An Open Source Mixed-Precision Neural Network Accelerator Design Framework for FPGAs.\n \n \n \n\n\n \n Luo, E.; Huang, H.; Liu, C.; Li, G.; Yang, B.; Wang, Y.; Li, H.; and Li, X.\n\n\n \n\n\n\n In 2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD), pages 1–9, 2023. IEEE\n \n\n\n\n
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@inproceedings{luo2023deepburning,\n  title={DeepBurning-MixQ: An Open Source Mixed-Precision Neural Network Accelerator Design Framework for FPGAs},\n  author={Luo, Erjing and Huang, Haitong and Liu, Cheng and Li, Guoyu and Yang, Bing and Wang, Ying and Li, Huawei and Li, Xiaowei},\n  booktitle={2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD)},\n  pages={1--9},\n  year={2023},\n  organization={IEEE}\n}\n\n
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\n \n\n \n \n \n \n \n Winograd convolution: A perspective from fault tolerance.\n \n \n \n\n\n \n Xue, X.; Huang, H.; Liu, C.; Luo, T.; Zhang, L.; and Wang, Y.\n\n\n \n\n\n\n In Proceedings of the 59th ACM/IEEE Design Automation Conference, pages 853–858, 2022. \n \n\n\n\n
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@inproceedings{xue2022winograd,\n  title={Winograd convolution: A perspective from fault tolerance},\n  author={Xue, Xinghua and Huang, Haitong and Liu, Cheng and Luo, Tao and Zhang, Lei and Wang, Ying},\n  booktitle={Proceedings of the 59th ACM/IEEE Design Automation Conference},\n  pages={853--858},\n  year={2022}\n}\n\n
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\n \n\n \n \n \n \n \n On-line fault protection for ReRAM-based neural networks.\n \n \n \n\n\n \n Li, W.; Wang, Y.; Liu, C.; He, Y.; Liu, L.; Li, H.; and Li, X.\n\n\n \n\n\n\n IEEE Transactions on Computers, 72(2): 423–437. 2022.\n \n\n\n\n
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@article{li2022line,\n  title={On-line fault protection for ReRAM-based neural networks},\n  author={Li, Wen and Wang, Ying and Liu, Cheng and He, Yintao and Liu, Lian and Li, Huawei and Li, Xiaowei},\n  journal={IEEE Transactions on Computers},\n  volume={72},\n  number={2},\n  pages={423--437},\n  year={2022},\n  publisher={IEEE}\n}\n\n
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@article{choong2022hardware,\n  title={Hardware-software co-exploration with racetrack memory based in-memory computing for CNN inference in embedded systems},\n  author={Choong, Benjamin Chen Ming and Luo, Tao and Liu, Cheng and He, Bingsheng and Zhang, Wei and Zhou, Joey Tianyi},\n  journal={Journal of Systems Architecture},\n  volume={128},\n  pages={102507},\n  year={2022},\n  publisher={North-Holland}\n}\n\n
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\n \n\n \n \n \n \n \n A framework for neural network architecture and compile co-optimization.\n \n \n \n\n\n \n Chen, W.; Wang, Y.; Xu, Y.; Gao, C.; Liu, C.; and Zhang, L.\n\n\n \n\n\n\n ACM Transactions on Embedded Computing Systems, 22(1): 1–24. 2022.\n \n\n\n\n
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@article{chen2022framework,\n  title={A framework for neural network architecture and compile co-optimization},\n  author={Chen, Weiwei and Wang, Ying and Xu, Ying and Gao, Chengsi and Liu, Cheng and Zhang, Lei},\n  journal={ACM Transactions on Embedded Computing Systems},\n  volume={22},\n  number={1},\n  pages={1--24},\n  year={2022},\n  publisher={ACM New York, NY}\n}\n\n
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\n \n\n \n \n \n \n \n NoCeption: A fast PPA prediction framework for network-on-chips using graph neural network.\n \n \n \n\n\n \n Li, F.; Wang, Y.; Liu, C.; Li, H.; and Li, X.\n\n\n \n\n\n\n In 2022 Design, Automation & Test in Europe Conference & Exhibition (DATE), pages 1035–1040, 2022. IEEE\n \n\n\n\n
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@inproceedings{li2022noception,\n  title={NoCeption: A fast PPA prediction framework for network-on-chips using graph neural network},\n  author={Li, Fuping and Wang, Ying and Liu, Cheng and Li, Huawei and Li, Xiaowei},\n  booktitle={2022 Design, Automation \\& Test in Europe Conference \\& Exhibition (DATE)},\n  pages={1035--1040},\n  year={2022},\n  organization={IEEE}\n}\n\n
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\n \n\n \n \n \n \n \n Special session: Fault-tolerant deep learning: A hierarchical perspective.\n \n \n \n\n\n \n Liu, C.; Gao, Z.; Liu, S.; Ning, X.; Li, H.; and Li, X.\n\n\n \n\n\n\n In 2022 IEEE 40th VLSI Test Symposium (VTS), pages 1–12, 2022. IEEE\n \n\n\n\n
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@inproceedings{liu2022special,\n  title={Special session: Fault-tolerant deep learning: A hierarchical perspective},\n  author={Liu, Cheng and Gao, Zhen and Liu, Siting and Ning, Xuefei and Li, Huawei and Li, Xiaowei},\n  booktitle={2022 IEEE 40th VLSI Test Symposium (VTS)},\n  pages={1--12},\n  year={2022},\n  organization={IEEE}\n}\n\n
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\n \n\n \n \n \n \n \n VStore: in-storage graph based vector search accelerator.\n \n \n \n\n\n \n Liang, S.; Wang, Y.; Yuan, Z.; Liu, C.; Li, H.; and Li, X.\n\n\n \n\n\n\n In Proceedings of the 59th ACM/IEEE Design Automation Conference, pages 997–1002, 2022. \n \n\n\n\n
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@inproceedings{liang2022vstore,\n  title={VStore: in-storage graph based vector search accelerator},\n  author={Liang, Shengwen and Wang, Ying and Yuan, Ziming and Liu, Cheng and Li, Huawei and Li, Xiaowei},\n  booktitle={Proceedings of the 59th ACM/IEEE Design Automation Conference},\n  pages={997--1002},\n  year={2022}\n}\n\n
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\n \n\n \n \n \n \n \n Processing-in-SRAM acceleration for ultra-low power visual 3D perception.\n \n \n \n\n\n \n He, Y.; Qu, S.; Lin, G.; Liu, C.; Zhang, L.; and Wang, Y.\n\n\n \n\n\n\n In Proceedings of the 59th ACM/IEEE Design Automation Conference, pages 295–300, 2022. \n \n\n\n\n
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@inproceedings{he2022processing,\n  title={Processing-in-SRAM acceleration for ultra-low power visual 3D perception},\n  author={He, Yuquan and Qu, Songyun and Lin, Gangliang and Liu, Cheng and Zhang, Lei and Wang, Ying},\n  booktitle={Proceedings of the 59th ACM/IEEE Design Automation Conference},\n  pages={295--300},\n  year={2022}\n}\n\n
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\n \n\n \n \n \n \n \n Variation enhanced attacks against rram-based neuromorphic computing system.\n \n \n \n\n\n \n Lv, H.; Li, B.; Zhang, L.; Liu, C.; and Wang, Y.\n\n\n \n\n\n\n IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 42(5): 1588–1596. 2022.\n \n\n\n\n
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@article{lv2022variation,\n  title={Variation enhanced attacks against rram-based neuromorphic computing system},\n  author={Lv, Hao and Li, Bing and Zhang, Lei and Liu, Cheng and Wang, Ying},\n  journal={IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems},\n  volume={42},\n  number={5},\n  pages={1588--1596},\n  year={2022},\n  publisher={IEEE}\n}\n\n
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\n \n\n \n \n \n \n \n Network Pruning for Bit-Serial Accelerators.\n \n \n \n\n\n \n Zhao, X.; Wang, Y.; Liu, C.; Shi, C.; Tu, K.; and Zhang, L.\n\n\n \n\n\n\n IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 2022.\n \n\n\n\n
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@article{zhao2022network,\n  title={Network Pruning for Bit-Serial Accelerators},\n  author={Zhao, Xiandong and Wang, Ying and Liu, Cheng and Shi, Cong and Tu, Kaijie and Zhang, Lei},\n  journal={IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems},\n  year={2022},\n  publisher={IEEE}\n}\n\n
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\n \n\n \n \n \n \n \n Reexamining CGRA memory sub-system for higher memory utilization and performance.\n \n \n \n\n\n \n Dai, L.; Wang, Y.; Liu, C.; Li, F.; Li, H.; and Li, X.\n\n\n \n\n\n\n In 2022 IEEE 40th International Conference on Computer Design (ICCD), pages 42–49, 2022. IEEE\n \n\n\n\n
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@inproceedings{dai2022reexamining,\n  title={Reexamining CGRA memory sub-system for higher memory utilization and performance},\n  author={Dai, Lei and Wang, Ying and Liu, Cheng and Li, Fuping and Li, Huawei and Li, Xiaowei},\n  booktitle={2022 IEEE 40th International Conference on Computer Design (ICCD)},\n  pages={42--49},\n  year={2022},\n  organization={IEEE}\n}\n\n
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@article{xu2021reliability,\n  title={Reliability Evaluation and Analysis of FPGA-Based Neural Network Acceleration System},\n  author={Xu, Dawen and Zhu, Ziyang and Liu, Cheng and Wang, Ying and Zhao, Shuang and Zhang, Lei and Liang, Huaguo and Li, Huawei and Cheng, Kwang-Ting},\n  journal={IEEE Transactions on Very Large Scale Integration (VLSI) Systems},\n  year={2021},\n  publisher={IEEE}\n}\n\n
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@article{cheng2021network,\n  title={Network-aware locality scheduling for distributed data operators in data centers},\n  author={Cheng, Long and Wang, Ying and Liu, Qingzhi and Epema, Dick HJ and Liu, Cheng and Mao, Ying and Murphy, John},\n  journal={IEEE Transactions on Parallel and Distributed Systems},\n  volume={32},\n  number={6},\n  pages={1494--1510},\n  year={2021},\n  publisher={IEEE}\n}\n\n
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\n \n\n \n \n \n \n \n VADER: Leveraging the Natural Variation of Hardware to Enhance Adversarial Attack.\n \n \n \n\n\n \n Lv, H.; Li, B.; Wang, Y.; Liu, C.; and Zhang, L.\n\n\n \n\n\n\n In Proceedings of the 26th Asia and South Pacific Design Automation Conference, pages 487–492, 2021. \n \n\n\n\n
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@inproceedings{lv2021vader,\n  title={VADER: Leveraging the Natural Variation of Hardware to Enhance Adversarial Attack},\n  author={Lv, Hao and Li, Bing and Wang, Ying and Liu, Cheng and Zhang, Lei},\n  booktitle={Proceedings of the 26th Asia and South Pacific Design Automation Conference},\n  pages={487--492},\n  year={2021}\n}\n\n
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\n \n\n \n \n \n \n \n MT-DLA: An efficient multi-task deep learning accelerator design.\n \n \n \n\n\n \n Wang, M.; Li, B.; Wang, Y.; Liu, C.; Ma, X.; Zhao, X.; and Zhang, L.\n\n\n \n\n\n\n In Proceedings of the 2021 on Great Lakes Symposium on VLSI, pages 1–8, 2021. \n \n\n\n\n
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@inproceedings{wang2021mt,\n  title={MT-DLA: An efficient multi-task deep learning accelerator design},\n  author={Wang, Mengdi and Li, Bing and Wang, Ying and Liu, Cheng and Ma, Xiaohan and Zhao, Xiandong and Zhang, Lei},\n  booktitle={Proceedings of the 2021 on Great Lakes Symposium on VLSI},\n  pages={1--8},\n  year={2021}\n}\n\n
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\n \n\n \n \n \n \n \n CHaNAS: coordinated search for network architecture and scheduling policy.\n \n \n \n\n\n \n Chen, W.; Wang, Y.; Lin, G.; Gao, C.; Liu, C.; and Zhang, L.\n\n\n \n\n\n\n In Proceedings of the 22nd ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, and Tools for Embedded Systems, pages 42–53, 2021. \n \n\n\n\n
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@inproceedings{chen2021chanas,\n  title={CHaNAS: coordinated search for network architecture and scheduling policy},\n  author={Chen, Weiwei and Wang, Ying and Lin, Gangliang and Gao, Chengsi and Liu, Cheng and Zhang, Lei},\n  booktitle={Proceedings of the 22nd ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, and Tools for Embedded Systems},\n  pages={42--53},\n  year={2021}\n}\n\n
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@inproceedings{li2021glist,\n  title={$\\{$GLIST$\\}$: Towards $\\{$in-storage$\\}$ graph learning},\n  author={Li, Cangyuan and Wang, Ying and Liu, Cheng and Liang, Shengwen and Li, Huawei and Li, Xiaowei},\n  booktitle={2021 USENIX Annual Technical Conference (USENIX ATC 21)},\n  pages={225--238},\n  year={2021}\n}\n\n
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@inproceedings{ma2021nasa,\n  title={NASA: accelerating neural network design with a NAS processor},\n  author={Ma, Xiaohan and Si, Chang and Wang, Ying and Liu, Cheng and Zhang, Lei},\n  booktitle={2021 ACM/IEEE 48th Annual International Symposium on Computer Architecture (ISCA)},\n  pages={790--803},\n  year={2021},\n  organization={IEEE}\n}\n\n
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@article{xu2021r2f,\n  title={R2F: A remote retraining framework for AIoT processors with computing errors},\n  author={Xu, Dawen and He, Meng and Liu, Cheng and Wang, Ying and Cheng, Long and Li, Huawei and Li, Xiaowei and Cheng, Kwang-Ting},\n  journal={IEEE Transactions on Very Large Scale Integration (VLSI) Systems},\n  volume={29},\n  number={11},\n  pages={1955--1966},\n  year={2021},\n  publisher={IEEE}\n}\n\n
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@inproceedings{he2021picovo,\n  title={Picovo: A lightweight rgb-d visual odometry targeting resource-constrained iot devices},\n  author={He, Yuquan and Wang, Ying and Liu, Cheng and Zhang, Lei},\n  booktitle={2021 IEEE International Conference on Robotics and Automation (ICRA)},\n  pages={5567--5573},\n  year={2021},\n  organization={IEEE}\n}\n\n
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@article{liu2021hyca,\n  title={HyCA: A hybrid computing architecture for fault-tolerant deep learning},\n  author={Liu, Cheng and Chu, Cheng and Xu, Dawen and Wang, Ying and Wang, Qianlong and Li, Huawei and Li, Xiaowei and Cheng, Kwang-Ting},\n  journal={IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems},\n  volume={41},\n  number={10},\n  pages={3400--3413},\n  year={2021},\n  publisher={IEEE}\n}\n\n
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\n \n\n \n \n \n \n \n Gcim: a near-data processing accelerator for graph construction.\n \n \n \n\n\n \n He, L.; Liu, C.; Wang, Y.; Liang, S.; Li, H.; and Li, X.\n\n\n \n\n\n\n In 2021 58th ACM/IEEE Design Automation Conference (DAC), pages 205–210, 2021. IEEE\n \n\n\n\n
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@inproceedings{he2021gcim,\n  title={Gcim: a near-data processing accelerator for graph construction},\n  author={He, Lei and Liu, Cheng and Wang, Ying and Liang, Shengwen and Li, Huawei and Li, Xiaowei},\n  booktitle={2021 58th ACM/IEEE Design Automation Conference (DAC)},\n  pages={205--210},\n  year={2021},\n  organization={IEEE}\n}\n\n
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@inproceedings{he2021tare,\n  title={Tare: task-adaptive in-situ reram computing for graph learning},\n  author={He, Yintao and Wang, Ying and Liu, Cheng and Li, Huawei and Li, Xiaowei},\n  booktitle={2021 58th ACM/IEEE Design Automation Conference (DAC)},\n  pages={577--582},\n  year={2021},\n  organization={IEEE}\n}\n\n
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@inproceedings{wang2021network,\n  title={Network-on-interposer design for agile neural-network processor chip customization},\n  author={Wang, Mengdi and Wang, Ying and Liu, Cheng and Zhang, Lei},\n  booktitle={2021 58th ACM/IEEE Design Automation Conference (DAC)},\n  pages={49--54},\n  year={2021},\n  organization={IEEE}\n}\n\n
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\n \n\n \n \n \n \n \n Taming process variations in CNFET for efficient last-level cache design.\n \n \n \n\n\n \n Xu, D.; Feng, Z.; Liu, C.; Li, L.; Wang, Y.; Li, H.; and Li, X.\n\n\n \n\n\n\n IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 30(4): 418–431. 2021.\n \n\n\n\n
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@article{xu2021taming,\n  title={Taming process variations in CNFET for efficient last-level cache design},\n  author={Xu, Dawen and Feng, Zhuangyu and Liu, Cheng and Li, Li and Wang, Ying and Li, Huawei and Li, Xiaowei},\n  journal={IEEE Transactions on Very Large Scale Integration (VLSI) Systems},\n  volume={30},\n  number={4},\n  pages={418--431},\n  year={2021},\n  publisher={IEEE}\n}\n\n
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\n \n\n \n \n \n \n \n Energy-efficient accelerator design for deformable convolution networks.\n \n \n \n\n\n \n Xu, D.; Chu, C.; Liu, C.; Wang, Y.; Li, H.; Li, X.; and Cheng, K.\n\n\n \n\n\n\n arXiv preprint arXiv:2107.02547. 2021.\n \n\n\n\n
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@article{xu2021energy,\n  title={Energy-efficient accelerator design for deformable convolution networks},\n  author={Xu, Dawen and Chu, Cheng and Liu, Cheng and Wang, Ying and Li, Huawei and Li, Xiaowei and Cheng, Kwang-Ting},\n  journal={arXiv preprint arXiv:2107.02547},\n  year={2021}\n}\n\n
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\n  \n 2020\n \n \n (12)\n \n \n
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\n \n\n \n \n \n \n \n Linear Symmetric Quantization of Neural Networks for Low-precision Integer Hardware.\n \n \n \n\n\n \n Zhao, X.; Wang, Y.; Cai, X.; Liu, C.; and Zhang, L.\n\n\n \n\n\n\n In International Conference on Learning Representations (ICLR), 2020. https://openreview.net/forum?id=H1lBj2VFPS\n \n\n\n\n
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@inproceedings{zhao2020linear,\n  title={Linear Symmetric Quantization of Neural Networks for Low-precision Integer Hardware},\n  author={Zhao, Xiandong and Wang, Ying and Cai, Xuyi and Liu, Cheng and Zhang, Lei},\n  booktitle={International Conference on Learning Representations (ICLR)},\n  year={2020},\n  organization={https://openreview.net/forum?id=H1lBj2VFPS}\n}\n\n
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\n \n\n \n \n \n \n \n CNT-Cache: An energy-efficient carbon nanotube cache with adaptive encoding.\n \n \n \n\n\n \n Xu, D.; Chu, K.; Liu, C.; Wang, Y.; Zhang, L.; and Li, H.\n\n\n \n\n\n\n In 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pages 963–966, 2020. IEEE\n \n\n\n\n
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@inproceedings{xu2020cnt,\n  title={CNT-Cache: An energy-efficient carbon nanotube cache with adaptive encoding},\n  author={Xu, Dawen and Chu, Kexin and Liu, Cheng and Wang, Ying and Zhang, Lei and Li, Huawei},\n  booktitle={2020 Design, Automation \\& Test in Europe Conference \\& Exhibition (DATE)},\n  pages={963--966},\n  year={2020},\n  organization={IEEE}\n}\n\n
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\n \n\n \n \n \n \n \n You Only Search Once: A Fast Automation Framework for Single-Stage DNN/Accelerator Co-design.\n \n \n \n\n\n \n Chen, W.; Wang, Y.; Yang, S.; Liu, C.; and Zhang, L.\n\n\n \n\n\n\n In 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pages 1283–1286, 2020. \n \n\n\n\n
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@inproceedings{chen2020you,\n  title={You Only Search Once: A Fast Automation Framework for Single-Stage DNN/Accelerator Co-design},\n  author={Chen, Weiwei and Wang, Ying and Yang, Shuang and Liu, Cheng and Zhang, Lei},\n  booktitle={2020 Design, Automation \\& Test in Europe Conference \\& Exhibition (DATE)},\n  pages={1283--1286},\n  year={2020}\n}\n\n
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\n \n\n \n \n \n \n \n Towards best-effort approximation: applying NAS to general-purpose approximate computing.\n \n \n \n\n\n \n Chen, W.; Wang, Y.; Yang, S.; Liu, C.; and Zhang, L.\n\n\n \n\n\n\n In 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pages 1315–1318, 2020. IEEE\n \n\n\n\n
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@inproceedings{chen2020towards,\n  title={Towards best-effort approximation: applying NAS to general-purpose approximate computing},\n  author={Chen, Weiwei and Wang, Ying and Yang, Shuang and Liu, Chen and Zhang, Lei},\n  booktitle={2020 Design, Automation \\& Test in Europe Conference \\& Exhibition (DATE)},\n  pages={1315--1318},\n  year={2020},\n  organization={IEEE}\n}\n\n
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\n \n\n \n \n \n \n \n Accelerating generative neural networks on unmodified deep learning processors—A software approach.\n \n \n \n\n\n \n Xu, D.; Liu, C.; Wang, Y.; Tu, K.; He, B.; and Zhang, L.\n\n\n \n\n\n\n IEEE Transactions on Computers, 69(8): 1172–1184. 2020.\n \n\n\n\n
\n\n\n\n \n\n \n\n \n link\n  \n \n\n bibtex\n \n\n \n\n \n\n \n \n \n \n \n \n \n\n  \n \n \n\n\n\n
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@article{xu2020accelerating,\n  title={Accelerating generative neural networks on unmodified deep learning processors—A software approach},\n  author={Xu, Dawen and Liu, Cheng and Wang, Ying and Tu, Kaijie and He, Bingsheng and Zhang, Lei},\n  journal={IEEE Transactions on Computers},\n  volume={69},\n  number={8},\n  pages={1172--1184},\n  year={2020},\n  publisher={IEEE}\n}\n\n
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\n \n\n \n \n \n \n \n Persistent fault analysis of neural networks on FPGA-based acceleration system.\n \n \n \n\n\n \n Xu, D.; Zhu, Z.; Liu, C.; Wang, Y.; Li, H.; Zhang, L.; and Cheng, K.\n\n\n \n\n\n\n In 2020 IEEE 31st International Conference on Application-specific Systems, Architectures and Processors (ASAP), pages 85–92, 2020. IEEE\n \n\n\n\n
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@inproceedings{xu2020persistent,\n  title={Persistent fault analysis of neural networks on FPGA-based acceleration system},\n  author={Xu, Dawen and Zhu, Ziyang and Liu, Cheng and Wang, Ying and Li, Huawei and Zhang, Lei and Cheng, Kwang-Ting},\n  booktitle={2020 IEEE 31st International Conference on Application-specific Systems, Architectures and Processors (ASAP)},\n  pages={85--92},\n  year={2020},\n  organization={IEEE}\n}\n\n
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\n \n\n \n \n \n \n \n Multi-task Scheduling for PIM-based Heterogeneous Computing System.\n \n \n \n\n\n \n Xu, D.; Chu, C.; Liu, C.; Wang, Y.; Zhou, X.; Zhang, L.; Liang, H.; and Li, H.\n\n\n \n\n\n\n In Proceedings of the 2020 on Great Lakes Symposium on VLSI, pages 457–462, 2020. \n \n\n\n\n
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@inproceedings{xu2020multi,\n  title={Multi-task Scheduling for PIM-based Heterogeneous Computing System},\n  author={Xu, Dawen and Chu, Cheng and Liu, Cheng and Wang, Ying and Zhou, Xianzhong and Zhang, Lei and Liang, Huaguo and Li, Huawei},\n  booktitle={Proceedings of the 2020 on Great Lakes Symposium on VLSI},\n  pages={457--462},\n  year={2020}\n}\n\n
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\n \n\n \n \n \n \n \n Deepburning-gl: an automated framework for generating graph neural network accelerators.\n \n \n \n\n\n \n Liang, S.; Liu, C.; Wang, Y.; Li, H.; and Li, X.\n\n\n \n\n\n\n In Proceedings of the 39th International Conference on Computer-Aided Design, pages 1–9, 2020. \n \n\n\n\n
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@inproceedings{liang2020deepburning,\n  title={Deepburning-gl: an automated framework for generating graph neural network accelerators},\n  author={Liang, Shengwen and Liu, Cheng and Wang, Ying and Li, Huawei and Li, Xiaowei},\n  booktitle={Proceedings of the 39th International Conference on Computer-Aided Design},\n  pages={1--9},\n  year={2020}\n}\n\n
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\n \n\n \n \n \n \n \n A hybrid computing architecture for fault-tolerant deep learning accelerators.\n \n \n \n\n\n \n Xu, D.; Chu, C.; Wang, Q.; Liu, C.; Wang, Y.; Zhang, L.; Liang, H.; and Cheng, K.\n\n\n \n\n\n\n In 2020 IEEE 38th International Conference on Computer Design (ICCD), pages 478–485, 2020. IEEE\n \n\n\n\n
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@inproceedings{xu2020hybrid,\n  title={A hybrid computing architecture for fault-tolerant deep learning accelerators},\n  author={Xu, Dawen and Chu, Cheng and Wang, Qianlong and Liu, Cheng and Wang, Ying and Zhang, Lei and Liang, Huaguo and Cheng, Kwang-Ting},\n  booktitle={2020 IEEE 38th International Conference on Computer Design (ICCD)},\n  pages={478--485},\n  year={2020},\n  organization={IEEE}\n}\n\n
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\n \n\n \n \n \n \n \n ENGN: A high-throughput and energy-efficient accelerator for large graph neural networks.\n \n \n \n\n\n \n Liang, S.; Wang, Y.; Liu, C.; He, L.; Huawei, L.; Xu, D.; and Li, X.\n\n\n \n\n\n\n IEEE Transactions on Computers. 2020.\n \n\n\n\n
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@article{liang2020engn,\n  title={ENGN: A high-throughput and energy-efficient accelerator for large graph neural networks},\n  author={Liang, Shengwen and Wang, Ying and Liu, Cheng and He, Lei and Huawei, LI and Xu, Dawen and Li, Xiaowei},\n  journal={IEEE Transactions on Computers},\n  year={2020},\n  publisher={IEEE}\n}\n\n
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\n \n\n \n \n \n \n \n BitPruner: Network pruning for bit-serial accelerators.\n \n \n \n\n\n \n Zhao, X.; Wang, Y.; Liu, C.; Shi, C.; Tu, K.; and Zhang, L.\n\n\n \n\n\n\n In 2020 57th ACM/IEEE Design Automation Conference (DAC), pages 1–6, 2020. IEEE\n \n\n\n\n
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@inproceedings{zhao2020bitpruner,\n  title={BitPruner: Network pruning for bit-serial accelerators},\n  author={Zhao, Xiandong and Wang, Ying and Liu, Cheng and Shi, Cong and Tu, Kaijie and Zhang, Lei},\n  booktitle={2020 57th ACM/IEEE Design Automation Conference (DAC)},\n  pages={1--6},\n  year={2020},\n  organization={IEEE}\n}\n\n
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\n \n\n \n \n \n \n \n Energy efficient in-memory integer multiplication based on racetrack memory.\n \n \n \n\n\n \n Luo, T.; Zhang, W.; He, B.; Liu, C.; and Maskell, D.\n\n\n \n\n\n\n In 2020 IEEE 40th International Conference on Distributed Computing Systems (ICDCS), pages 1409–1414, 2020. IEEE\n \n\n\n\n
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@inproceedings{luo2020energy,\n  title={Energy efficient in-memory integer multiplication based on racetrack memory},\n  author={Luo, Tao and Zhang, Wei and He, Bingsheng and Liu, Cheng and Maskell, Douglas},\n  booktitle={2020 IEEE 40th International Conference on Distributed Computing Systems (ICDCS)},\n  pages={1409--1414},\n  year={2020},\n  organization={IEEE}\n}\n\n
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\n  \n 2019\n \n \n (6)\n \n \n
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\n \n\n \n \n \n \n \n Exploring emerging CNFET for efficient last level cache design.\n \n \n \n\n\n \n Xu, D.; Li, L.; Wang, Y.; Liu, C.; and Li, H.\n\n\n \n\n\n\n In Proceedings of the 24th Asia and South Pacific Design Automation Conference, pages 426–431, 2019. \n \n\n\n\n
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@inproceedings{xu2019exploring,\n  title={Exploring emerging CNFET for efficient last level cache design},\n  author={Xu, Dawen and Li, Li and Wang, Ying and Liu, Cheng and Li, Huawei},\n  booktitle={Proceedings of the 24th Asia and South Pacific Design Automation Conference},\n  pages={426--431},\n  year={2019}\n}\n\n
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\n \n\n \n \n \n \n \n A survey on graph processing accelerators: Challenges and opportunities.\n \n \n \n\n\n \n Gui, C.; Zheng, L.; He, B.; Liu, C.; Chen, X.; Liao, X.; and Jin, H.\n\n\n \n\n\n\n Journal of Computer Science and Technology, 34: 339–371. 2019.\n \n\n\n\n
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@article{gui2019survey,\n  title={A survey on graph processing accelerators: Challenges and opportunities},\n  author={Gui, Chuang-Yi and Zheng, Long and He, Bingsheng and Liu, Cheng and Chen, Xin-Yu and Liao, Xiao-Fei and Jin, Hai},\n  journal={Journal of Computer Science and Technology},\n  volume={34},\n  pages={339--371},\n  year={2019},\n  publisher={Springer US}\n}\n\n
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\n \n\n \n \n \n \n \n Resilient neural network training for accelerators with computing errors.\n \n \n \n\n\n \n Xu, D.; Xing, K.; Liu, C.; Wang, Y.; Dai, Y.; Cheng, L.; Li, H.; and Zhang, L.\n\n\n \n\n\n\n In 2019 IEEE 30th International Conference on Application-specific Systems, Architectures and Processors (ASAP), volume 2160, pages 99–102, 2019. IEEE\n \n\n\n\n
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@inproceedings{xu2019resilient,\n  title={Resilient neural network training for accelerators with computing errors},\n  author={Xu, Dawen and Xing, Kouzi and Liu, Cheng and Wang, Ying and Dai, Yulin and Cheng, Long and Li, Huawei and Zhang, Lei},\n  booktitle={2019 IEEE 30th International Conference on Application-specific Systems, Architectures and Processors (ASAP)},\n  volume={2160},\n  pages={99--102},\n  year={2019},\n  organization={IEEE}\n}\n\n
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\n \n\n \n \n \n \n \n Squeezing the last MHz for CNN acceleration on FPGAs.\n \n \n \n\n\n \n Li, L.; Xu, D.; Xing, K.; Liu, C.; Wang, Y.; Li, H.; and Li, X.\n\n\n \n\n\n\n In 2019 IEEE International Test Conference in Asia (ITC-Asia), pages 151–156, 2019. IEEE\n \n\n\n\n
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@inproceedings{li2019squeezing,\n  title={Squeezing the last MHz for CNN acceleration on FPGAs},\n  author={Li, Li and Xu, Dawen and Xing, Kouzi and Liu, Cheng and Wang, Ying and Li, Huawei and Li, Xiaowei},\n  booktitle={2019 IEEE International Test Conference in Asia (ITC-Asia)},\n  pages={151--156},\n  year={2019},\n  organization={IEEE}\n}\n\n
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\n \n\n \n \n \n \n \n Ins-dla: An in-ssd deep learning accelerator for near-data processing.\n \n \n \n\n\n \n Liang, S.; Wang, Y.; Liu, C.; Li, H.; and Li, X.\n\n\n \n\n\n\n In 2019 29th International Conference on Field Programmable Logic and Applications (FPL), pages 173–179, 2019. IEEE\n \n\n\n\n
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@inproceedings{liang2019ins,\n  title={Ins-dla: An in-ssd deep learning accelerator for near-data processing},\n  author={Liang, Shengwen and Wang, Ying and Liu, Cheng and Li, Huawei and Li, Xiaowei},\n  booktitle={2019 29th International Conference on Field Programmable Logic and Applications (FPL)},\n  pages={173--179},\n  year={2019},\n  organization={IEEE}\n}\n\n
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\n \n\n \n \n \n \n \n OBFS: OpenCL based BFS optimizations on software programmable FPGAs.\n \n \n \n\n\n \n Liu, C.; Chen, X.; He, B.; Liao, X.; Wang, Y.; and Zhang, L.\n\n\n \n\n\n\n In 2019 International Conference on Field-Programmable Technology (ICFPT), pages 315–318, 2019. IEEE\n \n\n\n\n
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@inproceedings{liu2019obfs,\n  title={OBFS: OpenCL based BFS optimizations on software programmable FPGAs},\n  author={Liu, Cheng and Chen, Xinyu and He, Bingsheng and Liao, Xiaofei and Wang, Ying and Zhang, Lei},\n  booktitle={2019 International Conference on Field-Programmable Technology (ICFPT)},\n  pages={315--318},\n  year={2019},\n  organization={IEEE}\n}\n\n
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\n  \n 2018\n \n \n (2)\n \n \n
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\n \n\n \n \n \n \n \n FCN-engine: Accelerating deconvolutional layers in classic CNN processors.\n \n \n \n\n\n \n Xu, D.; Tu, K.; Wang, Y.; Liu, C.; He, B.; and Li, H.\n\n\n \n\n\n\n In 2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pages 1–6, 2018. IEEE\n \n\n\n\n
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@inproceedings{xu2018fcn,\n  title={FCN-engine: Accelerating deconvolutional layers in classic CNN processors},\n  author={Xu, Dawen and Tu, Kaijie and Wang, Ying and Liu, Cheng and He, Bingsheng and Li, Huawei},\n  booktitle={2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)},\n  pages={1--6},\n  year={2018},\n  organization={IEEE}\n}\n\n
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\n \n\n \n \n \n \n \n A virtual channel allocation algorithm for noc.\n \n \n \n\n\n \n Bao, D.; Li, X.; Xin, Y.; Yang, J.; Ren, X.; Fu, F.; and Liu, C.\n\n\n \n\n\n\n In Machine Learning and Intelligent Communications: Second International Conference, MLICOM 2017, Weihai, China, August 5-6, 2017, Proceedings, Part II 2, pages 333–342, 2018. Springer International Publishing\n \n\n\n\n
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@inproceedings{bao2018virtual,\n  title={A virtual channel allocation algorithm for noc},\n  author={Bao, Dongxing and Li, Xiaoming and Xin, Yizong and Yang, Jiuru and Ren, Xiangshi and Fu, Fangfa and Liu, Cheng},\n  booktitle={Machine Learning and Intelligent Communications: Second International Conference, MLICOM 2017, Weihai, China, August 5-6, 2017, Proceedings, Part II 2},\n  pages={333--342},\n  year={2018},\n  organization={Springer International Publishing}\n}\n\n
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\n  \n 2016\n \n \n (2)\n \n \n
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\n \n\n \n \n \n \n \n A soft processor overlay with tightly-coupled FPGA accelerator.\n \n \n \n\n\n \n Ng, H.; Liu, C.; and So, H. K.\n\n\n \n\n\n\n arXiv preprint arXiv:1606.06483. 2016.\n \n\n\n\n
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@article{ng2016soft,\n  title={A soft processor overlay with tightly-coupled FPGA accelerator},\n  author={Ng, Ho-Cheung and Liu, Cheng and So, Hayden Kwok-Hay},\n  journal={arXiv preprint arXiv:1606.06483},\n  year={2016}\n}\n\n
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\n \n\n \n \n \n \n \n FPGA overlays.\n \n \n \n\n\n \n So, H. K.; and Liu, C.\n\n\n \n\n\n\n FPGAs for Software Programmers,285–305. 2016.\n \n\n\n\n
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@article{so2016fpga,\n  title={FPGA overlays},\n  author={So, Hayden Kwok-Hay and Liu, Cheng},\n  journal={FPGAs for Software Programmers},\n  pages={285--305},\n  year={2016},\n  publisher={Springer International Publishing}\n}\n\n
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\n  \n 2015\n \n \n (3)\n \n \n
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\n \n\n \n \n \n \n \n Automatic nested loop acceleration on FPGAs using soft CGRA overlay.\n \n \n \n\n\n \n Liu, C.; Ng, H.; and So, H. K.\n\n\n \n\n\n\n arXiv preprint arXiv:1509.00042. 2015.\n \n\n\n\n
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@article{liu2015automatic,\n  title={Automatic nested loop acceleration on FPGAs using soft CGRA overlay},\n  author={Liu, Cheng and Ng, Ho-Cheung and So, Hayden Kwok-Hay},\n  journal={arXiv preprint arXiv:1509.00042},\n  year={2015}\n}\n\n
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\n \n\n \n \n \n \n \n QuickDough: A rapid FPGA loop accelerator design framework using soft CGRA overlay.\n \n \n \n\n\n \n Liu, C.; Ng, H.; and So, H. K.\n\n\n \n\n\n\n In 2015 International Conference on Field Programmable Technology (FPT), pages 56–63, 2015. IEEE\n \n\n\n\n
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@inproceedings{liu2015quickdough,\n  title={QuickDough: A rapid FPGA loop accelerator design framework using soft CGRA overlay},\n  author={Liu, Cheng and Ng, Ho-Cheung and So, Hayden Kwok-Hay},\n  booktitle={2015 International Conference on Field Programmable Technology (FPT)},\n  pages={56--63},\n  year={2015},\n  organization={IEEE}\n}\n\n
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\n \n\n \n \n \n \n \n QuickDough: a rapid FPGA loop accelerator design framework using soft coarse-grained reconfigurable array overlay.\n \n \n \n\n\n \n Liu, C.\n\n\n \n\n\n\n HKU Theses Online (HKUTO). 2015.\n \n\n\n\n
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@article{liu2015quickdough,\n  title={QuickDough: a rapid FPGA loop accelerator design framework using soft coarse-grained reconfigurable array overlay},\n  author={Liu, Cheng},\n  journal={HKU Theses Online (HKUTO)},\n  year={2015},\n  publisher={The University of Hong Kong (Pokfulam, Hong Kong)}\n}\n\n
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\n  \n 2014\n \n \n (1)\n \n \n
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\n \n\n \n \n \n \n \n Economizing TSV Resources in 3-D Network-on-Chip Design.\n \n \n \n\n\n \n Wang, Y.; Han, Y.; Zhang, L.; Fu, B.; Liu, C.; Li, H.; and Li, X\n\n\n \n\n\n\n IEEE Transactions on Very Large Scale Integration (VLSI) Systems, (99): 1–13. 2014.\n \n\n\n\n
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@article{wang2014economizing,\n  title={Economizing TSV Resources in 3-D Network-on-Chip Design},\n  author={Wang, Y. and Han, Y.-H. and Zhang, L. and Fu, B.-Z. and Liu, C. and Li, H.-W. and Li, X},\n  journal={IEEE Transactions on Very Large Scale Integration (VLSI) Systems},\n  number={99},\n  pages={1--13},\n  year={2014},\n  publisher={IEEE}\n}\n\n
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\n  \n 2013\n \n \n (2)\n \n \n
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\n \n\n \n \n \n \n \n RevivePath: Resilient network-on-chip design through data path salvaging of router.\n \n \n \n\n\n \n Han, Y.; Liu, C.; Lu, H.; Li, W.; Zhang, L.; and Li, X.\n\n\n \n\n\n\n Journal of Computer Science and Technology, 28: 1045–1053. 2013.\n \n\n\n\n
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@article{han2013revivepath,\n  title={RevivePath: Resilient network-on-chip design through data path salvaging of router},\n  author={Han, Yin-He and Liu, Cheng and Lu, Hang and Li, Wen-Bo and Zhang, Lei and Li, Xiao-Wei},\n  journal={Journal of Computer Science and Technology},\n  volume={28},\n  pages={1045--1053},\n  year={2013},\n  publisher={Springer US}\n}\n\n
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\n \n\n \n \n \n \n \n A Soft Coarse-Grained Reconfigurable Array Based High-level Synthesis Methodology: Promoting Design Productivity and Exploring Extreme FPGA Frequency.\n \n \n \n\n\n \n Liu, C.; Yu, C.; and So, H.\n\n\n \n\n\n\n In Field-Programmable Custom Computing Machines (FCCM), 2013 IEEE 21st Annual International Symposium on, pages 228–228, 2013. \n \n\n\n\n
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@inproceedings{liu2013soft,\n  title={A Soft Coarse-Grained Reconfigurable Array Based High-level Synthesis Methodology: Promoting Design Productivity and Exploring Extreme FPGA Frequency},\n  author={Liu, Cheng and Yu, C.L. and So, H.K.-H.},\n  booktitle={Field-Programmable Custom Computing Machines (FCCM), 2013 IEEE 21st Annual International Symposium on},\n  pages={228--228},\n  year={2013}\n}\n\n
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\n  \n 2011\n \n \n (2)\n \n \n
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\n \n\n \n \n \n \n \n Vertical interconnects squeezing in symmetric 3D mesh Network-on-Chip.\n \n \n \n\n\n \n Liu, C.; Zhang, L.; Han, Y.; and Li, X.\n\n\n \n\n\n\n In 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011), pages 357–362, 2011. IEEE\n \n\n\n\n
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@inproceedings{liu2011vertical,\n  title={Vertical interconnects squeezing in symmetric 3D mesh Network-on-Chip},\n  author={Liu, Cheng and Zhang, Lei and Han, Yinhe and Li, Xiaowei},\n  booktitle={16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011)},\n  pages={357--362},\n  year={2011},\n  organization={IEEE}\n}\n\n
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\n \n\n \n \n \n \n \n A resilient on-chip router design through data path salvaging.\n \n \n \n\n\n \n Liu, C.; Zhang, L.; Han, Y.; and Li, X.\n\n\n \n\n\n\n In 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011), pages 437–442, 2011. IEEE\n \n\n\n\n
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@inproceedings{liu2011resilient,\n  title={A resilient on-chip router design through data path salvaging},\n  author={Liu, Cheng and Zhang, Lei and Han, Yinhe and Li, Xiaowei},\n  booktitle={16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011)},\n  pages={437--442},\n  year={2011},\n  organization={IEEE}\n}\n\n
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\n  \n 2009\n \n \n (1)\n \n \n
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\n \n\n \n \n \n \n \n 支持确定性/自适应路由的低延迟片上路由器设计.\n \n \n \n\n\n \n Zhang, Q.; Liu, C.; Xiao, L.; and Fu, F.\n\n\n \n\n\n\n 计算机辅助设计与图形学学报, (12): 1706–1714. 2009.\n \n\n\n\n
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@article{zhang2009deterministic,\n  title={支持确定性/自适应路由的低延迟片上路由器设计},\n  author={Zhang, Qingli and Liu, Cheng and Xiao, Liyi and Fu, Fangfa},\n  journal={计算机辅助设计与图形学学报},\n  number={12},\n  pages={1706--1714},\n  year={2009}\n}\n\n
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\n  \n 2008\n \n \n (1)\n \n \n
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\n \n\n \n \n \n \n \n Design and analysis of on-chip router.\n \n \n \n\n\n \n Liu, C.; Xiao, L.; and Fu, F.\n\n\n \n\n\n\n In 2008 9th International Conference on Solid-State and Integrated-Circuit Technology, pages 1835–1838, 2008. IEEE\n \n\n\n\n
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@inproceedings{liu2008design,\n  title={Design and analysis of on-chip router},\n  author={Liu, Cheng and Xiao, Liyi and Fu, Fangfa},\n  booktitle={2008 9th International Conference on Solid-State and Integrated-Circuit Technology},\n  pages={1835--1838},\n  year={2008},\n  organization={IEEE}\n}\n\n
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\n  \n 2007\n \n \n (1)\n \n \n
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\n \n\n \n \n \n \n \n NISAR: An AXI compliant on-chip NI architecture offering transaction reordering processing.\n \n \n \n\n\n \n Yang, X.; Qing-li, Z.; Fang-fa, F.; Ming-yan, Y.; and Cheng, L.\n\n\n \n\n\n\n In 2007 7th International Conference on ASIC, pages 890–893, 2007. IEEE\n \n\n\n\n
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@inproceedings{yang2007nisar,\n  title={NISAR: An AXI compliant on-chip NI architecture offering transaction reordering processing},\n  author={Yang, Xu and Qing-li, Zhang and Fang-fa, Fu and Ming-yan, Yu and Cheng, Liu},\n  booktitle={2007 7th International Conference on ASIC},\n  pages={890--893},\n  year={2007},\n  organization={IEEE}\n}\n\n
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