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\n\n \n \n \n \n \n HyPaFilter+: Enhanced hybrid packet filtering using hardware assisted classification and header space analysis.\n \n \n \n\n\n \n Fiessler, A.; Lorenz, C.; Hager, S.; Scheuermann, B.; and Moore, A. W.\n\n\n \n\n\n\n
IEEE/ACM Transactions on Networking, 25(6): 3655–3669. 2017.\n
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@Article{Fiessler2017HyPaFilter+,\n author = {Fiessler, Andreas and Lorenz, Claas and Hager, Sven and Scheuermann, Bj{\\"o}rn and Moore, Andrew W.},\n journal = {IEEE/ACM Transactions on Networking},\n title = {{HyPaFilter+: Enhanced hybrid packet filtering using hardware assisted classification and header space analysis}},\n year = {2017},\n number = {6},\n pages = {3655--3669},\n volume = {25},\n publisher = {IEEE},\n}\n\n
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\n\n \n \n \n \n \n Where has my time gone?.\n \n \n \n\n\n \n Zilberman, N.; Grosvenor, M.; Popescu, D. A.; Manihatty-Bojan, N.; Antichi, G.; Wójcik, M.; and Moore, A. W.\n\n\n \n\n\n\n In
International Conference on Passive and Active Network Measurement, pages 201–214, 2017. Springer, Cham\n
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@InProceedings{Zilberman2017Wherea,\n author = {Zilberman, Noa and Grosvenor, Matthew and Popescu, Diana Andreea and Manihatty-Bojan, Neelakandan and Antichi, Gianni and W{\\'o}jcik, Marcin and Moore, Andrew W.},\n booktitle = {International Conference on Passive and Active Network Measurement},\n title = {Where has my time gone?},\n year = {2017},\n organization = {Springer, Cham},\n pages = {201--214},\n}\n\n
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\n\n \n \n \n \n \n Enabling fast hierarchical heavy hitter detection using programmable data planes.\n \n \n \n\n\n \n Popescu, D. A.; Antichi, G.; and Moore, A. W.\n\n\n \n\n\n\n In
Proceedings of the Symposium on SDN Research, pages 191–192, 2017. \n
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@InProceedings{Popescu2017Enabling,\n author = {Popescu, Diana Andreea and Antichi, Gianni and Moore, Andrew W.},\n booktitle = {Proceedings of the Symposium on SDN Research},\n title = {Enabling fast hierarchical heavy hitter detection using programmable data planes},\n year = {2017},\n pages = {191--192},\n}\n\n
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\n\n \n \n \n \n \n Ptpmesh: Data center network latency measurements using ptp.\n \n \n \n\n\n \n Popescu, D. A.; and Moore, A. W.\n\n\n \n\n\n\n In
2017 IEEE 25th International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems (MASCOTS), pages 73–79, 2017. IEEE\n
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@InProceedings{Popescu2017Ptpmesh,\n author = {Popescu, Diana Andreea and Moore, Andrew W.},\n booktitle = {2017 IEEE 25th International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems (MASCOTS)},\n title = {{Ptpmesh: Data center network latency measurements using ptp}},\n year = {2017},\n organization = {IEEE},\n pages = {73--79},\n}\n\n
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\n\n \n \n \n \n \n Network traffic classification via neural networks.\n \n \n \n\n\n \n Michael, A. K. J.; Valla, E.; Neggatu, N. S.; and Moore, A. W.\n\n\n \n\n\n\n Technical Report 2017.\n
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@TechReport{Michael2017Network,\n author = {Michael, Ang Kun Joo and Valla, Emma and Neggatu, Natinael Solomon and Moore, Andrew W.},\n title = {Network traffic classification via neural networks},\n year = {2017},\n school = {University of Cambridge, Computer Laboratory},\n}\n\n
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\n\n \n \n \n \n \n Mind the Gap - A Comparison of Software Packet Generators.\n \n \n \n\n\n \n Emmerich, P.; Gallenmuller, S.; Antichi, G.; Moore, A. W.; and Carle, G.\n\n\n \n\n\n\n In
Proceedings - 2017 ACM/IEEE Symposium on Architectures for Networking and Communications Systems, ANCS 2017, pages 191–203, Jun 2017. IEEE\n
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@InProceedings{Emmerich2017Mind,\n author = {Emmerich, P. and Gallenmuller, S. and Antichi, G. and Moore, A. W. and Carle, G.},\n booktitle = {Proceedings - 2017 ACM/IEEE Symposium on Architectures for Networking and Communications Systems, ANCS 2017},\n title = {{Mind the Gap - A Comparison of Software Packet Generators}},\n year = {2017},\n month = {Jun},\n organization = {IEEE},\n pages = {191--203},\n abstract = {© 2017 IEEE. Network research relies on packet generators to assess performance and correctness of new ideas. Software-based generators in particular are widely used by academic researchers because of their flexibility, affordability, and open-source nature. The rise of new frameworks for fast IO on commodity hardware is making them even more attractive. Longstanding performance differences of software generation versus hardware in terms of throughput are no longer as big of a concern as they used to be few years ago. This paper investigates the properties of several high-per-formance software packet generators and the implications on their precision when a given traffic pattern needs to be generated. We believe that the evaluation strategy presented in this paper helps understanding the actual limitations in high-performance software packet generation, thus helping the research community to build better tools.},\n day = {30},\n doi = {10.1109/ANCS.2017.32},\n isbn = {9781509063864},\n publicationstatus = {published},\n}\n\n
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\n © 2017 IEEE. Network research relies on packet generators to assess performance and correctness of new ideas. Software-based generators in particular are widely used by academic researchers because of their flexibility, affordability, and open-source nature. The rise of new frameworks for fast IO on commodity hardware is making them even more attractive. Longstanding performance differences of software generation versus hardware in terms of throughput are no longer as big of a concern as they used to be few years ago. This paper investigates the properties of several high-per-formance software packet generators and the implications on their precision when a given traffic pattern needs to be generated. We believe that the evaluation strategy presented in this paper helps understanding the actual limitations in high-performance software packet generation, thus helping the research community to build better tools.\n
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\n\n \n \n \n \n \n Emu: Rapid Prototyping of Networking Services.\n \n \n \n\n\n \n Sultana, N.; Galea, S.; Greaves, D.; Wojcik, M.; Shipton, J.; Clegg, R.; Mai, L.; Bressana, P.; Soule, R.; Mortier, R.; and others\n\n\n \n\n\n\n In
2017 USENIX Annual Technical Conference (USENIX ATC ’17), pages 459–471, Jan 2017. USENIX Association\n
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\n\n \n\n \n\n \n link\n \n \n\n bibtex\n \n\n \n \n \n abstract \n \n\n \n\n \n \n \n \n \n \n \n\n \n \n \n\n\n\n
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@InProceedings{Sultana2017Emu,\n author = {Sultana, Nik and Galea, Salvator and Greaves, David and Wojcik, Marcin and Shipton, Jonny and Clegg, Richard and Mai, Luo and Bressana, Pietro and Soule, Robert and Mortier, Richard and others},\n booktitle = {2017 USENIX Annual Technical Conference (USENIX ATC ’17)},\n title = {{Emu: Rapid Prototyping of Networking Services}},\n year = {2017},\n month = {Jan},\n organization = {USENIX Association},\n pages = {459--471},\n abstract = {© USENIX Annual Technical Conference, USENIX ATC 2017. All rights reserved. Due to their performance and flexibility, FPGAs are an attractive platform for the execution of network functions. It has been a challenge for a long time though to make FPGA programming accessible to a large audience of developers. An appealing solution is to compile code from a general-purpose language to hardware using high-level synthesis. Unfortunately, current approaches to implement rich network functionality are insufficient because they lack: (i) libraries with abstractions for common network operations and data structures, (ii) bindings to the underlying “substrate” on the FPGA, and (iii) debugging and profiling support. This paper describes Emu, a new standard library for an FPGA hardware compiler that enables developers to rapidly create and deploy network functionality. Emu allows for high-performance designs without being bound to particular packet processing paradigms. Furthermore, it supports running the same programs on CPUs, in Mininet, and on FPGAs, providing a better development environment that includes advanced debugging capabilities. We demonstrate that network functions implemented using Emu have only negligible resource and performance overheads compared with natively-written hardware versions.},\n day = {1},\n isbn = {9781931971386},\n journal = {Proceedings of the 2017 USENIX Annual Technical Conference, USENIX ATC 2017},\n publicationstatus = {published},\n}\n\n
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\n © USENIX Annual Technical Conference, USENIX ATC 2017. All rights reserved. Due to their performance and flexibility, FPGAs are an attractive platform for the execution of network functions. It has been a challenge for a long time though to make FPGA programming accessible to a large audience of developers. An appealing solution is to compile code from a general-purpose language to hardware using high-level synthesis. Unfortunately, current approaches to implement rich network functionality are insufficient because they lack: (i) libraries with abstractions for common network operations and data structures, (ii) bindings to the underlying “substrate” on the FPGA, and (iii) debugging and profiling support. This paper describes Emu, a new standard library for an FPGA hardware compiler that enables developers to rapidly create and deploy network functionality. Emu allows for high-performance designs without being bound to particular packet processing paradigms. Furthermore, it supports running the same programs on CPUs, in Mininet, and on FPGAs, providing a better development environment that includes advanced debugging capabilities. We demonstrate that network functions implemented using Emu have only negligible resource and performance overheads compared with natively-written hardware versions.\n
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\n\n \n \n \n \n \n Exploration of FPGA-based packet switches for rack-scale computers on a board.\n \n \n \n\n\n \n Han, J. H.; Manihatty-Bojan, N.; and Moore, A. W.\n\n\n \n\n\n\n In
Proceedings - IEEE 25th Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2017, pages 133, Jun 2017. IEEE\n
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@InProceedings{Han2017Exploration,\n author = {Han, J. H. and Manihatty-Bojan, N. and Moore, A. W.},\n booktitle = {Proceedings - IEEE 25th Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2017},\n title = {{Exploration of FPGA-based packet switches for rack-scale computers on a board}},\n year = {2017},\n month = {Jun},\n organization = {IEEE},\n pages = {133},\n abstract = {© 2017 IEEE. This work explores the design space (bandwidthand port configuration) for an FPGA-based top-of-rack switchand, use our implementation, to provide an insight on which ofthese options is the best. We also propose an architecture fora rack-scale computer built on a printed circuit board (PCB) exploiting the FPGA-based switch.},\n day = {30},\n doi = {10.1109/FCCM.2017.35},\n isbn = {9781538640364},\n publicationstatus = {published},\n}\n\n
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\n © 2017 IEEE. This work explores the design space (bandwidthand port configuration) for an FPGA-based top-of-rack switchand, use our implementation, to provide an insight on which ofthese options is the best. We also propose an architecture fora rack-scale computer built on a printed circuit board (PCB) exploiting the FPGA-based switch.\n
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\n\n \n \n \n \n \n Classbench-ng: Recasting classbench after a decade of network evolution.\n \n \n \n\n\n \n Matoušek, J.; Antichi, G.; Lučanskỳ, Adam; Moore, A. W.; and Kořenek, J.\n\n\n \n\n\n\n In
2017 ACM/IEEE Symposium on Architectures for Networking and Communications Systems (ANCS), pages 204–216, Beijing, 2017. IEEE, IEEE\n
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@InProceedings{Matousek2017Classbench,\n author = {Matou{\\v{s}}ek, Ji{\\v{r}}{\\'\\i} and Antichi, Gianni and Lu{\\v{c}}ansk{\\`y}, Adam and Moore, Andrew W. and Ko{\\v{r}}enek, Jan},\n booktitle = {2017 ACM/IEEE Symposium on Architectures for Networking and Communications Systems (ANCS)},\n title = {{Classbench-ng: Recasting classbench after a decade of network evolution}},\n year = {2017},\n address = {Beijing},\n organization = {IEEE},\n pages = {204--216},\n publisher = {IEEE},\n abstract = {Internet evolution is driven by a continuous stream of new applications and users driving the demand for services. To keep up with this, a never-stopping research has been transforming the Internet ecosystem over the time. Technological changes on both protocols (the uptake of IPv6) and network architectures (the adoption of Software Defined Networking) introduced new challenges for ASIC designers. In particular, IPv6 and OpenFlow increased the complexity of the rule matching problem, pushing researchers to build new packet classiffication algorithms capable to keep pace with a steady growth of link speed. A lot of research effort identifies better lookup techniques capitalizing on the characteristics of rule sets. So far, the availability of small numbers of real rule sets and synthetic ones, generated with tools such as ClassBench, has boosted research in the IPv4 world. Starting from an analysis of rule sets taken from operational environments, we present ClassBench-ng, a new open source tool for the generation of synthetic IPv4, IPv6, and OpenFlow 1.0 rule sets exposing the same properties of real ones. We feel this tool can meet the requirements of nowadays researchers, boosting the rule matching research as ClassBench has done since ten years ago.},\n date = {18-19 May 2017},\n doi = {10.1109/ANCS.2017.33},\n eventdate = {18-19 May 2017},\n eventtitleaddon = {Beijing},\n file = {:https\\://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7966918:PDF},\n isbn = {978-1-5090-6387-1},\n journal = {2017 ACM/IEEE Symposium on Architectures for Networking and Communications Systems (ANCS)},\n keywords = {Tools, Internet, Protocols, IP networks, Hardware, Probability distribution, Ecosystems, ClassBench, OpenFlow, packet classification},\n}\n\n
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\n Internet evolution is driven by a continuous stream of new applications and users driving the demand for services. To keep up with this, a never-stopping research has been transforming the Internet ecosystem over the time. Technological changes on both protocols (the uptake of IPv6) and network architectures (the adoption of Software Defined Networking) introduced new challenges for ASIC designers. In particular, IPv6 and OpenFlow increased the complexity of the rule matching problem, pushing researchers to build new packet classiffication algorithms capable to keep pace with a steady growth of link speed. A lot of research effort identifies better lookup techniques capitalizing on the characteristics of rule sets. So far, the availability of small numbers of real rule sets and synthetic ones, generated with tools such as ClassBench, has boosted research in the IPv4 world. Starting from an analysis of rule sets taken from operational environments, we present ClassBench-ng, a new open source tool for the generation of synthetic IPv4, IPv6, and OpenFlow 1.0 rule sets exposing the same properties of real ones. We feel this tool can meet the requirements of nowadays researchers, boosting the rule matching research as ClassBench has done since ten years ago.\n
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\n\n \n \n \n \n \n Research data and software supporting PTPmesh: Data Center Network Latency Measurements Using PTP.\n \n \n \n\n\n \n Popescu, D.; and Moore, A.\n\n\n \n\n\n\n 2017.\n
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@Misc{Popescu2017Research,\n author = {Popescu, Diana and Moore, Andrew},\n title = {{Research data and software supporting PTPmesh: Data Center Network Latency Measurements Using PTP}},\n year = {2017},\n abstract = {Dataset collected for the publication PTPmesh: Data Center Network Latency\nMeasurements Using PTP},\n keyword = {Network Latency Measurements},\n}\n\n
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\n Dataset collected for the publication PTPmesh: Data Center Network Latency Measurements Using PTP\n
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\n\n \n \n \n \n \n Where Has My Time Gone? Reproduction Environment and Dataset.\n \n \n \n\n\n \n Zilberman, N.; Grosvenor, M.; Popescu, D.; Manihatty Bojan, N; Antichi, G.; Wojcik, M.; and Moore, A.\n\n\n \n\n\n\n 2017.\n
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@Misc{Zilberman2017Where,\n author = {Zilberman, Noa and Grosvenor, MP and Popescu, Diana and Manihatty Bojan, N and Antichi, Gianni and Wojcik, Marcin and Moore, Andrew},\n title = {Where Has My Time Gone? Reproduction Environment and Dataset},\n year = {2017},\n abstract = {A dataset accompanying the PAM 2017 paper "Where Has My Time Gone?". This dataset includes both the scripts used for the measurements, and the results files.},\n doi = {10.17863/CAM.7418},\n keyword = {computer networks},\n}\n\n
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\n A dataset accompanying the PAM 2017 paper \"Where Has My Time Gone?\". This dataset includes both the scripts used for the measurements, and the results files.\n
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\n\n \n \n \n \n \n ENDEAVOUR: A scalable SDN architecture for real-world IXPs.\n \n \n \n\n\n \n Antichi, G.; Castro, I.; Chiesa, M.; Fernandes, E. L.; Lapeyrade, R.; Kopp, D.; Han, J. H.; Bruyere, M.; Dietzel, C.; Gusat, M.; and others\n\n\n \n\n\n\n
IEEE Journal on Selected Areas in Communications, 35(11): 2553–2562. 2017.\n
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@Article{Antichi2017ENDEAVOUR,\n author = {Antichi, Gianni and Castro, Ignacio and Chiesa, Marco and Fernandes, Eder L. and Lapeyrade, Remy and Kopp, Daniel and Han, Jong Hun and Bruyere, Marc and Dietzel, Christoph and Gusat, Mitchell and others},\n journal = {IEEE Journal on Selected Areas in Communications},\n title = {{ENDEAVOUR: A scalable SDN architecture for real-world IXPs}},\n year = {2017},\n issn = {1558-0008},\n number = {11},\n pages = {2553--2562},\n volume = {35},\n abstract = {Innovation in interdomain routing has remained stagnant for over a decade. Recently, Internet eXchange Points (IXPs) have emerged as economically-advantageous interconnection points for reducing path latencies and exchanging ever increasing traffic volumes among, possibly, hundreds of networks. Given their far-reaching implications on interdomain routing, IXPs are the ideal place to foster network innovation and extend the benefits of software defined networking (SDN) to the interdomain level. In this paper, we present, evaluate, and demonstrate ENDEAVOUR, an SDN platform for IXPs. ENDEAVOUR can be deployed on a multi-hop IXP fabric, supports a large number of use cases, and is highly scalable, while avoiding broadcast storms. Our evaluation with real data from one of the largest IXPs, demonstrates the benefits and scalability of our solution: ENDEAVOUR requires around 70% fewer rules than alternative SDN solutions thanks to our rule partitioning mechanism. In addition, by providing an open source solution, we invite everyone from the community to experiment (and improve) our implementation as well as adapt it to new use cases.},\n date = {Nov. 2017},\n doi = {10.1109/JSAC.2017.2760398},\n file = {:https\\://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8068192:PDF},\n issue = {11},\n journaltitle = {IEEE Journal on Selected Areas in Communications},\n keywords = {Software defined networking, Routing, Topology, Internet, Ports (Computers), Scalability, Servers, Internet eXchange points, inter-domain routing, peering},\n publisher = {IEEE},\n}\n\n
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\n Innovation in interdomain routing has remained stagnant for over a decade. Recently, Internet eXchange Points (IXPs) have emerged as economically-advantageous interconnection points for reducing path latencies and exchanging ever increasing traffic volumes among, possibly, hundreds of networks. Given their far-reaching implications on interdomain routing, IXPs are the ideal place to foster network innovation and extend the benefits of software defined networking (SDN) to the interdomain level. In this paper, we present, evaluate, and demonstrate ENDEAVOUR, an SDN platform for IXPs. ENDEAVOUR can be deployed on a multi-hop IXP fabric, supports a large number of use cases, and is highly scalable, while avoiding broadcast storms. Our evaluation with real data from one of the largest IXPs, demonstrates the benefits and scalability of our solution: ENDEAVOUR requires around 70% fewer rules than alternative SDN solutions thanks to our rule partitioning mechanism. In addition, by providing an open source solution, we invite everyone from the community to experiment (and improve) our implementation as well as adapt it to new use cases.\n
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