@article{DBLP:journals/corr/abs-2001-05400,
  author       = {James Timothy Meech and
                  Phillip Stanley{-}Marbell},
  title        = {Efficient Programmable Random Variate Generation Accelerator from
                  Sensor Noise},
  journal      = {CoRR},
  volume       = {abs/2001.05400},
  year         = {2020},
  url          = {https://arxiv.org/abs/2001.05400},
  eprinttype   = {arXiv},
  eprint       = {2001.05400},
  timestamp    = {Fri, 17 Jan 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/corr/abs-2001-05400.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/corr/abs-2007-00494,
  author       = {Chatura Samarakoon and
                  Gehan Amaratunga and
                  Phillip Stanley{-}Marbell},
  title        = {Content-Aware Automated Parameter Tuning for Approximate Color Transforms},
  journal      = {CoRR},
  volume       = {abs/2007.00494},
  year         = {2020},
  url          = {https://arxiv.org/abs/2007.00494},
  eprinttype   = {arXiv},
  eprint       = {2007.00494},
  timestamp    = {Mon, 06 Jul 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/corr/abs-2007-00494.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/corr/abs-2004-14111,
  author       = {Nathaniel Joseph Tye and
                  James Timothy Meech and
                  Bilgesu Arif Bilgin and
                  Phillip Stanley{-}Marbell},
  title        = {A System for Generating Non-Uniform Random Variates using Graphene
                  Field-Effect Transistors},
  journal      = {CoRR},
  volume       = {abs/2004.14111},
  year         = {2020},
  url          = {https://arxiv.org/abs/2004.14111},
  eprinttype   = {arXiv},
  eprint       = {2004.14111},
  timestamp    = {Sat, 02 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/corr/abs-2004-14111.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@misc{psm_exabounds,
    url       = {https://dominoweb.draco.res.ibm.com/b4d3883b485efdff85257d80003776c5.html},
    title     = {ExaBounds—Better-than-back-of-the-envelope Analysis for Large-Scale Computing Systems},
    author    = {Phillip Stanley-Marbell},
    journal   = {IBM Research Reports},
    year      = {2016},
    month     = {Sep},
    abstract  = {Large-scale computing systems such as supercomputers and commercial data centers pose many unique challenges in terms of power delivery and heat removal, performance at-scale, monetary cost of purchase and operation, and reliability during operation. Architectures to address these challenges must make appropriate hardware-level choices, in the context of the demands of target applications. Given the huge combinatorial space of choices of algorithms for solving various computational problems, hardware architectures, and technology for system implementation, it is necessary to have a mechanism to identify subsets of the algorithm, architecture, and technology design space worth more detailed study. EXABOUNDS is an analytic framework being developed for efficiently estimating coarse-grained bounds on, and growth rates of, compute performance, power dissipation, monetary cost, and reliability, of large-scale computing systems. While not intended to enable precise performance prediction as detailed processor or interconnect simulators do, it enables insight into the interaction between performance, power, cost, and reliability, by providing a meaningful yet simple model with complete visibility into the causal relations between system parameters and resulting system behavior. The framework incorporates a large body of empirical technology data, and its utility is demonstrated with a design study for a real future large-scale computing system.},
    url_link  = {https://dominoweb.draco.res.ibm.com/b4d3883b485efdff85257d80003776c5.html},
    url_paper = {https://physcomp.eng.cam.ac.uk/exabounds-better-than-back-of-the-envelope-analysis-for-large-scale-computing-systems/}
}

Large-scale computing systems such as supercomputers and commercial data centers pose many unique challenges in terms of power delivery and heat removal, performance at-scale, monetary cost of purchase and operation, and reliability during operation. Architectures to address these challenges must make appropriate hardware-level choices, in the context of the demands of target applications. Given the huge combinatorial space of choices of algorithms for solving various computational problems, hardware architectures, and technology for system implementation, it is necessary to have a mechanism to identify subsets of the algorithm, architecture, and technology design space worth more detailed study. EXABOUNDS is an analytic framework being developed for efficiently estimating coarse-grained bounds on, and growth rates of, compute performance, power dissipation, monetary cost, and reliability, of large-scale computing systems. While not intended to enable precise performance prediction as detailed processor or interconnect simulators do, it enables insight into the interaction between performance, power, cost, and reliability, by providing a meaningful yet simple model with complete visibility into the causal relations between system parameters and resulting system behavior. The framework incorporates a large body of empirical technology data, and its utility is demonstrated with a design study for a real future large-scale computing system.

@article{DBLP:journals/tecs/Stanley-Marbell13,
  author       = {Phillip Stanley{-}Marbell},
  title        = {{L24:} Parallelism, performance, energy efficiency, and cost trade-offs
                  in future sensor platforms},
  journal      = {{ACM} Trans. Embed. Comput. Syst.},
  volume       = {13},
  number       = {1},
  pages        = {7:1--7:27},
  year         = {2013},
  url          = {http://doi.acm.org/10.1145/2512465},
  doi          = {10.1145/2512465},
  timestamp    = {Tue, 08 Sep 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/tecs/Stanley-Marbell13.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

To sustain the improvements in transistor integration density, performance, and energy per operation witnessed over the last five decades, semiconductor device engineers are investigating several device alternatives. They are however hard-pressed to relate observed transistor-level properties of potential CMOS replacements with the performance which might be achieved when these devices are used to construct complete integrated circuits such as microprocessors. This article addresses this challenge by developing a model linking device properties to algorithm properties (parallelism and total computational work) and system operation conditions (degree of voltage and frequency scaling). This framework is then used to provide insight into which aspects of transistor operation most influence execution time, average power dissipation, and overall energy usage of parallel algorithms executing in the presence of hardware concurrency. For the often-encountered challenge of jointly optimizing execution time and energy usage, the framework enables the expression of the appropriate form of joint energy-delay metric as a function of device properties. The presented analysis is supported by empirical characterizations of a dozen large digital circuit designs, and is further validated using performance and power measurements of a parallel algorithm executing on a state-of-the-art low-power multicore processor.

@inproceedings{DBLP:conf/iiswc/JongeriusSC11,
  author       = {Rik Jongerius and
                  Phillip Stanley{-}Marbell and
                  Henk Corporaal},
  title        = {Quantifying the common computational problems in contemporary applications},
  booktitle    = {Proceedings of the 2011 {IEEE} International Symposium on Workload
                  Characterization, {IISWC} 2011, Austin, TX, USA, November 6-8, 2011},
  pages        = {74},
  publisher    = {{IEEE} Computer Society},
  year         = {2011},
  url          = {https://doi.org/10.1109/IISWC.2011.6114199},
  doi          = {10.1109/IISWC.2011.6114199},
  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/iiswc/JongeriusSC11.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/islped/Stanley-MarbellCL11,
  author       = {Phillip Stanley{-}Marbell and
                  Victoria Caparr{\'{o}}s Cabezas and
                  Ronald P. Luijten},
  editor       = {Naehyuck Chang and
                  Hiroshi Nakamura and
                  Koji Inoue and
                  Kenichi Osada and
                  Massimo Poncino},
  title        = {Pinned to the walls: impact of packaging and application properties
                  on the memory and power walls},
  booktitle    = {Proceedings of the 2011 International Symposium on Low Power Electronics
                  and Design, 2011, Fukuoka, Japan, August 1-3, 2011},
  pages        = {51--56},
  publisher    = {{IEEE/ACM}},
  year         = {2011},
  url          = {http://portal.acm.org/citation.cfm?id=2016815\&\#38;CFID=34981777\&\#38;CFTOKEN=25607807},
  timestamp    = {Mon, 13 Aug 2012 09:40:34 +0200},
  biburl       = {https://dblp.org/rec/conf/islped/Stanley-MarbellCL11.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/spe/SchoofsS11,
  author       = {Anthony Schoofs and
                  Phillip Stanley{-}Marbell},
  title        = {Portability in {MAC} protocol and transceiver software implementations
                  for {LR-WPAN} platforms},
  journal      = {Softw. Pract. Exp.},
  volume       = {41},
  number       = {4},
  pages        = {339--361},
  year         = {2011},
  url          = {https://doi.org/10.1002/spe.1008},
  doi          = {10.1002/SPE.1008},
  timestamp    = {Thu, 09 Apr 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/spe/SchoofsS11.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/cf/CabezasS11,
  author       = {Victoria Caparr{\'{o}}s Cabezas and
                  Phillip Stanley{-}Marbell},
  editor       = {Calin Cascaval and
                  Pedro Trancoso and
                  Viktor K. Prasanna},
  title        = {Quantitative analysis of parallelism and data movement properties
                  across the Berkeley computational motifs},
  booktitle    = {Proceedings of the 8th Conference on Computing Frontiers, 2011, Ischia,
                  Italy, May 3-5, 2011},
  pages        = {17},
  publisher    = {{ACM}},
  year         = {2011},
  url          = {https://doi.org/10.1145/2016604.2016625},
  doi          = {10.1145/2016604.2016625},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/cf/CabezasS11.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{10.1145/1989493.1989506,
    author    = {Caparr\'{o}s Cabezas, Victoria and Stanley-Marbell, Phillip},
    title     = {Parallelism and Data Movement Characterization of Contemporary Application Classes},
    year      = {2011},
    isbn      = {9781450307437},
    publisher = {Association for Computing Machinery},
    address   = {New York, NY, USA},
    url       = {https://doi.org/10.1145/1989493.1989506},
    doi       = {10.1145/1989493.1989506},
    pages     = {95–104},
    numpages  = {10},
    keywords  = {basic-block-level parallelism, berkeley computational motifs, instruction-level parallelism, data movement},
    location  = {San Jose, California, USA},
    series    = {SPAA '11},
    abstract  = {This paper presents a framework for characterizing the distribution of fine-grained parallelism, data movement, and communication-minimizing code partitions. Understanding the spectrum of parallelism available in applications, and how much data movement might result if such parallelism is exploited, is essential in the hardware design process because these properties will be the limiters to performance scaling of future computing systems. The framework is applied to characterizing 26 applications and kernels, classified according to their dominant components in the Berkeley dwarf/ computational motif classification.
	The distributions of ILP and TLP over execution time are studied, and it is shown that, though mean ILP is high, available ILP is significantly smaller for most of the execution. The results from this framework are complemented by hardware performance counter data on two RISC platforms (IBM Power7 and Freescale P2020) and one CISC platform (IntelAtom D510), spanning a broad range of real machine characteristics. Employing a combination of these new techniques, and building upon previous proposals, it is demonstrated that the similarity in available ideal-case parallelism and data movement within and across the dwarf classes, is limited.},
    url_link  = {https://dl.acm.org/doi/10.1145/1989493.1989506},
    url_paper = {https://physcomp.eng.cam.ac.uk/parallelism-and-data-movement-characterization-of-contemporary-application-classes}
}

This paper presents a framework for characterizing the distribution of fine-grained parallelism, data movement, and communication-minimizing code partitions. Understanding the spectrum of parallelism available in applications, and how much data movement might result if such parallelism is exploited, is essential in the hardware design process because these properties will be the limiters to performance scaling of future computing systems. The framework is applied to characterizing 26 applications and kernels, classified according to their dominant components in the Berkeley dwarf/ computational motif classification. The distributions of ILP and TLP over execution time are studied, and it is shown that, though mean ILP is high, available ILP is significantly smaller for most of the execution. The results from this framework are complemented by hardware performance counter data on two RISC platforms (IBM Power7 and Freescale P2020) and one CISC platform (IntelAtom D510), spanning a broad range of real machine characteristics. Employing a combination of these new techniques, and building upon previous proposals, it is demonstrated that the similarity in available ideal-case parallelism and data movement within and across the dwarf classes, is limited.

@inproceedings{DBLP:conf/ipps/Stanley-MarbellC11,
  author       = {Phillip Stanley{-}Marbell and
                  Victoria Caparr{\'{o}}s Cabezas},
  title        = {Performance, Power, and Thermal Analysis of Low-Power Processors for
                  Scale-Out Systems},
  booktitle    = {25th {IEEE} International Symposium on Parallel and Distributed Processing,
                  {IPDPS} 2011, Anchorage, Alaska, USA, 16-20 May 2011 - Workshop Proceedings},
  pages        = {863--870},
  publisher    = {{IEEE}},
  year         = {2011},
  url          = {https://doi.org/10.1109/IPDPS.2011.225},
  doi          = {10.1109/IPDPS.2011.225},
  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/ipps/Stanley-MarbellC11.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{10.1145/1773912.1773916,
author = {Van Hensbergen, Eric and Evans, Noah Paul and Stanley-Marbell, Phillip},
title = {A Unified Execution Model for Cloud Computing},
year = {2010},
journal = {SIGOPS Operating Systems Review},
publisher = {Association for Computing Machinery},
address = {New York, NY, USA},
volume = {44},
number = {2},
doi = {10.1145/1773912.1773916},
abstract = {This article presents the design goals and architecture for a unified execution model
(UEM) for cloud computing and clusters. The UEM combines interfaces for logical provisioning
and distributed command execution with integrated mechanisms for establishing and
maintaining communication, synchronization, and control. In this paper, the UEM architecture
is described, and an existing application which could benefit from its facilities
is used to illustrate its value.},
url_link = {https://doi.org/10.1145/1773912.1773916},
url_paper = {physcomp.eng.cam.ac.uk/a-unified-execution-model-for-cloud-computing}
}

This article presents the design goals and architecture for a unified execution model (UEM) for cloud computing and clusters. The UEM combines interfaces for logical provisioning and distributed command execution with integrated mechanisms for establishing and maintaining communication, synchronization, and control. In this paper, the UEM architecture is described, and an existing application which could benefit from its facilities is used to illustrate its value.

@inproceedings{DBLP:conf/oopsla/Stanley-Marbell10,
  author       = {Phillip Stanley{-}Marbell},
  editor       = {Hridesh Rajan and
                  Christoph Bockisch and
                  Michael Haupt and
                  Robert Dyer},
  title        = {Sal/Svm: an assembly language and virtual machine for computing with
                  non-enumerated sets},
  booktitle    = {VMIL@SPLASH 2010: Virtual Machines and Intermediate Languages, Reno,
                  Nevada, USA, October 17 - 21, 2010},
  pages        = {1:1--1:10},
  publisher    = {{ACM}},
  year         = {2010},
  url          = {https://doi.org/10.1145/1941054.1941055},
  doi          = {10.1145/1941054.1941055},
  timestamp    = {Wed, 29 Oct 2025 15:13:29 +0100},
  biburl       = {https://dblp.org/rec/conf/oopsla/Stanley-Marbell10.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{5351408,
    author    = {Stanley-Marbell, Phillip},
    booktitle = {2009 IEEE Information Theory Workshop},
    title     = {Encoding efficiency of digital number representations under deviation constraints},
    year      = {2009},
    volume    = {},
    number    = {},
    pages     = {203-207},
    doi       = {10.1109/ITW.2009.5351408},
    abstract  = {When logic upsets (faults) affect digital representations of numbers, it is possible to consider their effects in terms of the magnitude of the value deviation they induce. When some upper limit on such a change in value is tolerable, one may consider techniques for encoding to limit value deviations in the presence of faults. Examples of applications with tolerance to value deviation include computer graphics computations, and the computation, communication and storage of analog sensor values in sensor networks. This article presents upper bounds for the achievable efficiency of encoding under the constraint relaxation of a tolerable value deviation. Closed-form expressions and numerical evaluations for upper bounds on the achievable encoding efficiency under a maximum tolerable value deviation, for several different conditions under which logic upsets may occur, are presented. The bounds demonstrate the possibility of significant gains in encoding efficiency, when some semantic deviation of values is tolerable. Lower and upper bounds on the possible absolute value of deviation resulting from a given number of upsets in words of a known size are provided. It is shown that, if possible to bias the physical design of a system such that logic upsets in both high and low logic direction may occur simultaneously (versus only one or the other), the minimum values of the resulting deviations will be reduced.},
    url_link  = {https://ieeexplore.ieee.org/document/5351408},
    url_paper = {https://physcomp.eng.cam.ac.uk/encoding-efficiency-of-digital-number-representations-under-deviation-constraints/}
}

When logic upsets (faults) affect digital representations of numbers, it is possible to consider their effects in terms of the magnitude of the value deviation they induce. When some upper limit on such a change in value is tolerable, one may consider techniques for encoding to limit value deviations in the presence of faults. Examples of applications with tolerance to value deviation include computer graphics computations, and the computation, communication and storage of analog sensor values in sensor networks. This article presents upper bounds for the achievable efficiency of encoding under the constraint relaxation of a tolerable value deviation. Closed-form expressions and numerical evaluations for upper bounds on the achievable encoding efficiency under a maximum tolerable value deviation, for several different conditions under which logic upsets may occur, are presented. The bounds demonstrate the possibility of significant gains in encoding efficiency, when some semantic deviation of values is tolerable. Lower and upper bounds on the possible absolute value of deviation resulting from a given number of upsets in words of a known size are provided. It is shown that, if possible to bias the physical design of a system such that logic upsets in both high and low logic direction may occur simultaneously (versus only one or the other), the minimum values of the resulting deviations will be reduced.

@article{DBLP:journals/esl/SchoofsSS09,
  author       = {Anthony Schoofs and
                  Peter van der Stok and
                  Phillip Stanley{-}Marbell},
  title        = {Portability Versus Efficiency Tradeoffs in {MAC} Implementations for
                  Microsensor Platforms},
  journal      = {{IEEE} Embed. Syst. Lett.},
  volume       = {1},
  number       = {1},
  pages        = {24--27},
  year         = {2009},
  url          = {https://doi.org/10.1109/LES.2009.2028040},
  doi          = {10.1109/LES.2009.2028040},
  timestamp    = {Thu, 10 Sep 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/esl/SchoofsSS09.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@techreport{van2009service,
    title={Service Oriented File Systems},
    author={Van Hensbergen, Eric and Evans, Noah and Stanley-Marbell, Phillip},
    institution={IBM Research},
    year={2009},
    month={April},
    url_Link={https://dominoweb.draco.res.ibm.com/eb508fa066258c3d852575a70057baf0.html},
    url_Paper={https://dominoweb.draco.res.ibm.com/reports/rc24788.pdf}
}

@inproceedings{DBLP:conf/date/Stanley-MarbellM07,
  author    = {Phillip Stanley{-}Marbell and
               Diana Marculescu},
  editor    = {Rudy Lauwereins and
               Jan Madsen},
  title     = {An 0.9 {\texttimes} 1.2", low power, energy-harvesting system with
               custom multi-channel communication interface},
  booktitle = {2007 Design, Automation and Test in Europe Conference and Exposition,
               {DATE} 2007, Nice, France, April 16-20, 2007},
  pages     = {15--20},
  publisher = {{EDA} Consortium, San Jose, CA, {USA}},
  year      = {2007},
  url       = {https://doi.org/10.1109/DATE.2007.364560},
  doi       = {10.1109/DATE.2007.364560},
  timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
  biburl    = {https://dblp.org/rec/conf/date/Stanley-MarbellM07.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/dagstuhl/Stanley-Marbell07,
  author       = {Phillip Stanley{-}Marbell},
  editor       = {Luca Benini and
                  Naehyuck Chang and
                  Ulrich Kremer and
                  Christian W. Probst},
  title        = {The Sunflower Tool Suite - Hardware and Software Research Platforms
                  for Energy-Constrained and Failure-Prone Systems},
  booktitle    = {Power-aware Computing Systems, 21.01. - 26.01.2007},
  series       = {Dagstuhl Seminar Proceedings},
  publisher    = {Internationales Begegnungs- und Forschungszentrum fuer Informatik
                  (IBFI), Schloss Dagstuhl, Germany},
  year         = {2007},
  url          = {http://drops.dagstuhl.de/opus/volltexte/2007/1106},
  timestamp    = {Thu, 23 Aug 2018 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/dagstuhl/Stanley-Marbell07.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{10.5555/1762146.1762163,
    author    = {Stanley-Marbell, Phillip and Marculescu, Diana},
    title     = {Sunflower: Full-System, Embedded, Microarchitecture Evaluation},
    year      = {2007},
    isbn      = {9783540693376},
    publisher = {Springer-Verlag},
    address   = {Berlin, Heidelberg},
    booktitle = {Proceedings of the 2nd International Conference on High Performance Embedded Architectures and Compilers},
    pages     = {168–182},
    numpages  = {15},
    location  = {Ghent, Belgium},
    series    = {HiPEAC'07},
    abstract  = {This paper describes Sunflower, a full-system microarchitectural evaluation environment for embedded computing systems. The environment enables detailed microarchitectural simulation of multiple instances of complete embedded systems, their peripherals, and medium access control / physical layer communication between systems. The environment models the microarchitecture, computation and communication upset events under a variety of stochastic distributions, compute and communication power consumption, electrochemical battery systems, and power regulation circuitry, as well as analog signals external to the processing elements.
The simulation environment provides facilities for speeding up simulation performance, which tradeoff accuracy of simulated properties for simulation speed. Through the detailed simulation of benchmarks in which the effect of simulation speedup on correctness can be accurately quantified, it is demonstrated that traditional techniques proposed for simulation speedup can introduce significant error when simulating a combination of computation and analog physical phenomena external to a processor.},
    url_link  = {https://dl.acm.org/doi/10.5555/1762146.1762163},
    url_paper = {https://physcomp.eng.cam.ac.uk/sunflower-full-system-embedded-microarchitecture-evaluation}
}

This paper describes Sunflower, a full-system microarchitectural evaluation environment for embedded computing systems. The environment enables detailed microarchitectural simulation of multiple instances of complete embedded systems, their peripherals, and medium access control / physical layer communication between systems. The environment models the microarchitecture, computation and communication upset events under a variety of stochastic distributions, compute and communication power consumption, electrochemical battery systems, and power regulation circuitry, as well as analog signals external to the processing elements. The simulation environment provides facilities for speeding up simulation performance, which tradeoff accuracy of simulated properties for simulation speed. Through the detailed simulation of benchmarks in which the effect of simulation speedup on correctness can be accurately quantified, it is demonstrated that traditional techniques proposed for simulation speedup can introduce significant error when simulating a combination of computation and analog physical phenomena external to a processor.

@inproceedings{Stanley-marbell06aprogramming,
    author    = {Phillip Stanley-marbell and Diana Marculescu},
    title     = {A Programming Model and Language Implementation for Concurrent FailureProne Hardware},
    booktitle = {In Proceedings of the 2nd Workshop on Programming Models for Ubiquitous Parallelism, PMUP ’06},
    year      = {2006},
    abstract  = {We present a programming model and its embodiment in a language implementation, for systems composed of large numbers of failure-prone, resource-constrained elements, interconnected in error-prone networks. The programming model enables partitioning without replication, of applications, across multiple devices with constrained memory resources. It permits programs to specify the amount of error (value deviation) tolerable in individual variables, as well as tolerable latencies and erasures on communications. The value deviation constraints facilitate compile-time transformations for forward error correction; these transformations enable the value deviations in individual variables to be kept within program-specified bounds, in the presence of an assumed distribution of logic upsets in hardware. To account for situations in which such assumptions may be violated, language constructs enable the change of control-flow in response to tolerance constraint violations. The language model and implementation are targeted primarily at concurrent failure-prone embedded systems, such as sensor networks.},
    url_link  = {http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.121.9864},
    url_paper = {https://physcomp.eng.cam.ac.uk/a-programming-model-and-language-implementation-for-concurrent-failureprone-hardware/}
}

We present a programming model and its embodiment in a language implementation, for systems composed of large numbers of failure-prone, resource-constrained elements, interconnected in error-prone networks. The programming model enables partitioning without replication, of applications, across multiple devices with constrained memory resources. It permits programs to specify the amount of error (value deviation) tolerable in individual variables, as well as tolerable latencies and erasures on communications. The value deviation constraints facilitate compile-time transformations for forward error correction; these transformations enable the value deviations in individual variables to be kept within program-specified bounds, in the presence of an assumed distribution of logic upsets in hardware. To account for situations in which such assumptions may be violated, language constructs enable the change of control-flow in response to tolerance constraint violations. The language model and implementation are targeted primarily at concurrent failure-prone embedded systems, such as sensor networks.

@inproceedings{Server06implementationof,
    author    = {Phillip Stanley-marbell},
    title     = {Implementation of a distributed full-system simulation framework as a filesystem server},
    booktitle = {In Proceedings of the First International Workshop on Plan 9},
    year      = {2006},
    abstract  = {Full-system simulation of systems comprising hundreds of microcontrollers, at the level of in-struction execution, along with simulation of their peripherals, inter-device communication, power consumption and the like, can be tasking even on high-end workstations. To enable the partition-ing of these simulations, which have a high degree of coarse-grained parallelism, over a network of workstations, a multi-platform simulation environment was implemented using the Inferno system. The implementation enables the simulation engine, written in ANSI C, and compiled as a library, to be linked against the Inferno emulator with a custom device driver interface. Using a glue applica-tion written in Limbo, and harnessing ideas from parallel discrete-event simulation, the framework enables simulations of networks of embedded systems to be partitioned across workstations of het-erogeneous architectures. This paper presents the distributed simulation architecture, the design of the emulator device driver (the interface to the simulation engine), the graphical interface and glue application, and the packaging of the system as single-binary modules for multiple platforms. Also presented is a step-by-step guide for developers unfamiliar with Inferno for creating similar systems.},
    url_link  = {http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.566.3073},
    url_paper = {https://physcomp.eng.cam.ac.uk/implementation-of-a-distributed-full-system-simulation-framework-as-a-filesystem-server/}
}

Full-system simulation of systems comprising hundreds of microcontrollers, at the level of in-struction execution, along with simulation of their peripherals, inter-device communication, power consumption and the like, can be tasking even on high-end workstations. To enable the partition-ing of these simulations, which have a high degree of coarse-grained parallelism, over a network of workstations, a multi-platform simulation environment was implemented using the Inferno system. The implementation enables the simulation engine, written in ANSI C, and compiled as a library, to be linked against the Inferno emulator with a custom device driver interface. Using a glue applica-tion written in Limbo, and harnessing ideas from parallel discrete-event simulation, the framework enables simulations of networks of embedded systems to be partitioned across workstations of het-erogeneous architectures. This paper presents the distributed simulation architecture, the design of the emulator device driver (the interface to the simulation engine), the graphical interface and glue application, and the packaging of the system as single-binary modules for multiple platforms. Also presented is a step-by-step guide for developers unfamiliar with Inferno for creating similar systems.

@inproceedings{DBLP:conf/sensys/Stanley-Marbell05,
  author       = {Phillip Stanley{-}Marbell},
  editor       = {Jason Redi and
                  Hari Balakrishnan and
                  Feng Zhao},
  title        = {Full-system simulation for sensor networks},
  booktitle    = {Proceedings of the 3rd International Conference on Embedded Networked
                  Sensor Systems, SenSys 2005, San Diego, California, USA, November
                  2-4, 2005},
  pages        = {317},
  publisher    = {{ACM}},
  year         = {2005},
  url          = {https://doi.org/10.1145/1098918.1098982},
  doi          = {10.1145/1098918.1098982},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/sensys/Stanley-Marbell05.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}