Error-tolerant bit generation techniques for use with a hardware-embedded path delay PUF

Error-tolerant bit generation techniques for use with a hardware-embedded path delay PUF. Aarestad, J., Plusquellic, J., & Acharyya, D. In 2013 IEEE International Symposium on Hardware-Oriented Security and Trust, HOST 2013, Austin, TX, USA, June 2-3, 2013, pages 151--158, 2013.

Paper doi bibtex

@inproceedings{DBLP:conf/host/AarestadPA13,
  author    = {Jim Aarestad and
               Jim Plusquellic and
               Dhruva Acharyya},
  title     = {Error-tolerant bit generation techniques for use with a hardware-embedded
               path delay {PUF}},
  booktitle = {2013 {IEEE} International Symposium on Hardware-Oriented Security
               and Trust, {HOST} 2013, Austin, TX, USA, June 2-3, 2013},
  pages     = {151--158},
  year      = {2013},
  crossref  = {DBLP:conf/host/2013},
  url       = {http://dx.doi.org/10.1109/HST.2013.6581581},
  doi       = {10.1109/HST.2013.6581581},
  timestamp = {Thu, 23 Oct 2014 17:07:54 +0200},
  biburl    = {http://dblp.dagstuhl.de/rec/bib/conf/host/AarestadPA13},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}

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