@inProceedings{
 title = {Asynchronous BFT for low power networks on chip},
 type = {inProceedings},
 year = {2010},
 identifiers = {[object Object]},
 keywords = {BFT,GALS,Low power,NoC},
 id = {34d58e4d-6739-337d-9f50-7bcc334a4094},
 created = {2017-12-04T05:34:59.734Z},
 file_attached = {false},
 profile_id = {99d7e05e-a704-3549-ada2-dfc74a2d55ec},
 last_modified = {2017-12-04T05:34:59.734Z},
 read = {false},
 starred = {false},
 authored = {true},
 confirmed = {false},
 hidden = {false},
 private_publication = {false},
 abstract = {Asynchronous Butterfly Fat Tree (BFT) architecture is proposed to achieve low power Network on Chip (NoC). Asynchronous design could reduce the power dissipation of the network if the activity factor of the data transfer between two switches (α data  satisfies a certain condition. The area of Asynchronous BFT switch is increased by 25% as compared to Synchronous switch. However, the power dissipation of the Asynchronous architecture could be decreased by up to 33% as compared to the power dissipation of the conventional Synchronous architecture when the α data  equals 0.2 and the activity factor of the control signals is equal to 1/64 of the α data . The total metal resources required to implement Asynchronous design is decreased by 12%. ©2010 IEEE.},
 bibtype = {inProceedings},
 author = {Abd El Ghany, M.A. and El-Moursy, M.A. and Korzec, D. and Ismail, M.},
 booktitle = {ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems}
}

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