Power analysis for asynchronous network-on-chip. Abd El Ghany, M., Reehal, G., & Ismail, M. IEEJ Transactions on Electrical and Electronic Engineering, 2013.
abstract   bibtex   
An asynchronous architecture is proposed to achieve a low-power network-on-chip (NoC). The area of the asynchronous switch is increased by 25% as compared to the synchronous switch. However, the power dissipation of the asynchronous architecture could be decreased by up to 55%. Even though clock gating is used, the asynchronous design achieves significant power reduction of 28%. The total metal resource required to implement the asynchronous design is decreased by up to 12%. As technology advances and network density increases, the reduction in power dissipation reaches 22% for 256 IPs with the same chip size. The asynchronous butterfly fat tree (BFT) architecture dissipates the minimum power as compared to other NoC topologies. © 2013 Institute of Electrical Engineers of Japan.
@article{
 title = {Power analysis for asynchronous network-on-chip},
 type = {article},
 year = {2013},
 identifiers = {[object Object]},
 keywords = {GALS,Low power,NoC,Power analysis},
 volume = {8},
 id = {5c3b642d-e712-3a39-9891-0f92fb173a71},
 created = {2017-12-04T05:35:00.231Z},
 file_attached = {false},
 profile_id = {99d7e05e-a704-3549-ada2-dfc74a2d55ec},
 last_modified = {2017-12-04T05:35:00.231Z},
 read = {false},
 starred = {false},
 authored = {true},
 confirmed = {false},
 hidden = {false},
 private_publication = {false},
 abstract = {An asynchronous architecture is proposed to achieve a low-power network-on-chip (NoC). The area of the asynchronous switch is increased by 25% as compared to the synchronous switch. However, the power dissipation of the asynchronous architecture could be decreased by up to 55%. Even though clock gating is used, the asynchronous design achieves significant power reduction of 28%. The total metal resource required to implement the asynchronous design is decreased by up to 12%. As technology advances and network density increases, the reduction in power dissipation reaches 22% for 256 IPs with the same chip size. The asynchronous butterfly fat tree (BFT) architecture dissipates the minimum power as compared to other NoC topologies. © 2013 Institute of Electrical Engineers of Japan.},
 bibtype = {article},
 author = {Abd El Ghany, M.A. and Reehal, G. and Ismail, M.},
 journal = {IEEJ Transactions on Electrical and Electronic Engineering},
 number = {SUPL.1}
}

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