Power analysis for asynchronous network-on-chip. Abd El Ghany, M., Reehal, G., & Ismail, M. IEEJ Transactions on Electrical and Electronic Engineering, 2013. abstract bibtex An asynchronous architecture is proposed to achieve a low-power network-on-chip (NoC). The area of the asynchronous switch is increased by 25% as compared to the synchronous switch. However, the power dissipation of the asynchronous architecture could be decreased by up to 55%. Even though clock gating is used, the asynchronous design achieves significant power reduction of 28%. The total metal resource required to implement the asynchronous design is decreased by up to 12%. As technology advances and network density increases, the reduction in power dissipation reaches 22% for 256 IPs with the same chip size. The asynchronous butterfly fat tree (BFT) architecture dissipates the minimum power as compared to other NoC topologies. © 2013 Institute of Electrical Engineers of Japan.
@article{
title = {Power analysis for asynchronous network-on-chip},
type = {article},
year = {2013},
identifiers = {[object Object]},
keywords = {GALS,Low power,NoC,Power analysis},
volume = {8},
id = {5c3b642d-e712-3a39-9891-0f92fb173a71},
created = {2017-12-04T05:35:00.231Z},
file_attached = {false},
profile_id = {99d7e05e-a704-3549-ada2-dfc74a2d55ec},
last_modified = {2017-12-04T05:35:00.231Z},
read = {false},
starred = {false},
authored = {true},
confirmed = {false},
hidden = {false},
private_publication = {false},
abstract = {An asynchronous architecture is proposed to achieve a low-power network-on-chip (NoC). The area of the asynchronous switch is increased by 25% as compared to the synchronous switch. However, the power dissipation of the asynchronous architecture could be decreased by up to 55%. Even though clock gating is used, the asynchronous design achieves significant power reduction of 28%. The total metal resource required to implement the asynchronous design is decreased by up to 12%. As technology advances and network density increases, the reduction in power dissipation reaches 22% for 256 IPs with the same chip size. The asynchronous butterfly fat tree (BFT) architecture dissipates the minimum power as compared to other NoC topologies. © 2013 Institute of Electrical Engineers of Japan.},
bibtype = {article},
author = {Abd El Ghany, M.A. and Reehal, G. and Ismail, M.},
journal = {IEEJ Transactions on Electrical and Electronic Engineering},
number = {SUPL.1}
}
Downloads: 0
{"_id":"535JpmaWsiWfiL467","bibbaseid":"abdelghany-reehal-ismail-poweranalysisforasynchronousnetworkonchip-2013","downloads":0,"creationDate":"2018-11-02T20:16:34.685Z","title":"Power analysis for asynchronous network-on-chip","author_short":["Abd El Ghany, M.","Reehal, G.","Ismail, M."],"year":2013,"bibtype":"article","biburl":null,"bibdata":{"title":"Power analysis for asynchronous network-on-chip","type":"article","year":"2013","identifiers":"[object Object]","keywords":"GALS,Low power,NoC,Power analysis","volume":"8","id":"5c3b642d-e712-3a39-9891-0f92fb173a71","created":"2017-12-04T05:35:00.231Z","file_attached":false,"profile_id":"99d7e05e-a704-3549-ada2-dfc74a2d55ec","last_modified":"2017-12-04T05:35:00.231Z","read":false,"starred":false,"authored":"true","confirmed":false,"hidden":false,"private_publication":false,"abstract":"An asynchronous architecture is proposed to achieve a low-power network-on-chip (NoC). The area of the asynchronous switch is increased by 25% as compared to the synchronous switch. However, the power dissipation of the asynchronous architecture could be decreased by up to 55%. Even though clock gating is used, the asynchronous design achieves significant power reduction of 28%. The total metal resource required to implement the asynchronous design is decreased by up to 12%. As technology advances and network density increases, the reduction in power dissipation reaches 22% for 256 IPs with the same chip size. The asynchronous butterfly fat tree (BFT) architecture dissipates the minimum power as compared to other NoC topologies. © 2013 Institute of Electrical Engineers of Japan.","bibtype":"article","author":"Abd El Ghany, M.A. and Reehal, G. and Ismail, M.","journal":"IEEJ Transactions on Electrical and Electronic Engineering","number":"SUPL.1","bibtex":"@article{\n title = {Power analysis for asynchronous network-on-chip},\n type = {article},\n year = {2013},\n identifiers = {[object Object]},\n keywords = {GALS,Low power,NoC,Power analysis},\n volume = {8},\n id = {5c3b642d-e712-3a39-9891-0f92fb173a71},\n created = {2017-12-04T05:35:00.231Z},\n file_attached = {false},\n profile_id = {99d7e05e-a704-3549-ada2-dfc74a2d55ec},\n last_modified = {2017-12-04T05:35:00.231Z},\n read = {false},\n starred = {false},\n authored = {true},\n confirmed = {false},\n hidden = {false},\n private_publication = {false},\n abstract = {An asynchronous architecture is proposed to achieve a low-power network-on-chip (NoC). The area of the asynchronous switch is increased by 25% as compared to the synchronous switch. However, the power dissipation of the asynchronous architecture could be decreased by up to 55%. Even though clock gating is used, the asynchronous design achieves significant power reduction of 28%. The total metal resource required to implement the asynchronous design is decreased by up to 12%. As technology advances and network density increases, the reduction in power dissipation reaches 22% for 256 IPs with the same chip size. The asynchronous butterfly fat tree (BFT) architecture dissipates the minimum power as compared to other NoC topologies. © 2013 Institute of Electrical Engineers of Japan.},\n bibtype = {article},\n author = {Abd El Ghany, M.A. and Reehal, G. and Ismail, M.},\n journal = {IEEJ Transactions on Electrical and Electronic Engineering},\n number = {SUPL.1}\n}","author_short":["Abd El Ghany, M.","Reehal, G.","Ismail, M."],"bibbaseid":"abdelghany-reehal-ismail-poweranalysisforasynchronousnetworkonchip-2013","role":"author","urls":{},"keyword":["GALS","Low power","NoC","Power analysis"],"downloads":0,"html":""},"search_terms":["power","analysis","asynchronous","network","chip","abd el ghany","reehal","ismail"],"keywords":["gals","low power","noc","power analysis"],"authorIDs":[]}