High Speed Digital Filter Design Using Minimal Signed Digit Representation. Abed, K., Venugopalan, V., & Nerurkar, S. In Proceedings of IEEE SoutheastCon, pages 105–110, April, 2005. abstract bibtex This paper presents the design and implementation of novel decimation filter structure for high speed asymmetric digital subscriber line (ADSL). Existing ADSL circuits use comb-FIR-FIR decimation filter structures, which have low throughput, more hardware and high power consumption. Unlike existing ADSL circuits, we design a novel high speed filter architecture and implement it using the minimal signed digit (MSD) representation. The MSD representation is suitable for common subexpression elimination, and it significantly reduces the number of adders required for the filter synthesis. Each digital-filter structure is simulated using Matlab, and its complete architecture is captured using DSP Blockset and Simulink. The resulting filter architecture has higher throughput, less hardware and consumes less power than the comb-FIR-FIR and comb-IIR-FIR architectures. The filter has been implemented on Xilinx FPGA using Virtex-2 technology. Compared to the comb-FIR-FIR and the comb-IIR-FIR architectures, the designed decimation filter architecture contributes to a hardware saving of 82% and 74%, respectively; in addition, it reduces the power dissipation by 91% and 79%, respectively.
@inproceedings{Abed2005High-speed,
abstract = {This paper presents the design and implementation of novel decimation filter structure for high speed asymmetric digital subscriber line (ADSL). Existing ADSL circuits use comb-FIR-FIR decimation filter structures, which have low throughput, more hardware and high power consumption. Unlike existing ADSL circuits, we design a novel high speed filter architecture and implement it using the minimal signed digit (MSD) representation. The MSD representation is suitable for common subexpression elimination, and it significantly reduces the number of adders required for the filter synthesis. Each digital-filter structure is simulated using Matlab, and its complete architecture is captured using DSP Blockset and Simulink. The resulting filter architecture has higher throughput, less hardware and consumes less power than the comb-FIR-FIR and comb-IIR-FIR architectures. The filter has been implemented on Xilinx FPGA using Virtex-2 technology. Compared to the comb-FIR-FIR and the comb-IIR-FIR architectures, the designed decimation filter architecture contributes to a hardware saving of 82{\%} and 74{\%}, respectively; in addition, it reduces the power dissipation by 91{\%} and 79{\%}, respectively.},
author = {Abed, Khalid and Venugopalan, Vivek and Nerurkar, Shailesh},
booktitle = {Proceedings of IEEE SoutheastCon},
date-added = {2020-01-15 12:00:21 -0500},
date-modified = {2020-01-15 12:00:21 -0500},
keywords = {adders; digital filters; digital signal processing chips; digital subscriber lines; field programmable gate arrays; power consumption; signal representation; DSP Blockset; MSD representation; Matlab; Simulink; Virtex-2 technology; Xilinx FPGA; adders; asymmetric digital subscriber line; common subexpression elimination; decimation filter structure; filter synthesis; high speed ADSL; high speed digital filter; minimal signed digit representation; power consumption; throughput},
pages = {105--110},
title = {High Speed Digital Filter Design Using Minimal Signed Digit Representation},
ty = {CONF},
year = {2005},
month = apr,
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The resulting filter architecture has higher throughput, less hardware and consumes less power than the comb-FIR-FIR and comb-IIR-FIR architectures. The filter has been implemented on Xilinx FPGA using Virtex-2 technology. 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Existing ADSL circuits use comb-FIR-FIR decimation filter structures, which have low throughput, more hardware and high power consumption. Unlike existing ADSL circuits, we design a novel high speed filter architecture and implement it using the minimal signed digit (MSD) representation. The MSD representation is suitable for common subexpression elimination, and it significantly reduces the number of adders required for the filter synthesis. Each digital-filter structure is simulated using Matlab, and its complete architecture is captured using DSP Blockset and Simulink. The resulting filter architecture has higher throughput, less hardware and consumes less power than the comb-FIR-FIR and comb-IIR-FIR architectures. The filter has been implemented on Xilinx FPGA using Virtex-2 technology. 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