Temperature-Aware SoC Test Scheduling Considering Inter-Chip Process Variation. Aghaee, N., He, Z., Peng, Z., & Eles, P. In Asian Test Symposium, pages 395-398, 2010. IEEE Computer Society.
Temperature-Aware SoC Test Scheduling Considering Inter-Chip Process Variation. [link]Link  Temperature-Aware SoC Test Scheduling Considering Inter-Chip Process Variation. [link]Paper  bibtex   
@inproceedings{ conf/ats/AghaeeHPE10,
  added-at = {2011-01-31T00:00:00.000+0100},
  author = {Aghaee, Nima and He, Zhiyuan and Peng, Zebo and Eles, Petru},
  biburl = {http://www.bibsonomy.org/bibtex/23a1d067de8dde3de9df6b6b4a5391bc4/dblp},
  booktitle = {Asian Test Symposium},
  crossref = {conf/ats/2010},
  ee = {http://dx.doi.org/10.1109/ATS.2010.74},
  interhash = {935dd22ea1ee2c9d7812aff89dbd758c},
  intrahash = {3a1d067de8dde3de9df6b6b4a5391bc4},
  isbn = {978-0-7695-4248-5},
  keywords = {dblp},
  pages = {395-398},
  publisher = {IEEE Computer Society},
  title = {Temperature-Aware SoC Test Scheduling Considering Inter-Chip Process Variation.},
  url = {http://dblp.uni-trier.de/db/conf/ats/ats2010.html#AghaeeHPE10},
  year = {2010}
}

Downloads: 0