Low power ARM® Cortex™-M0 CPU and SRAM using Deeply Depleted Channel (DDC) transistors with Vdd scaling and body bias. Agrawal, V., Kepler, N., Kidd, D., Krishnan, G., Leshner, S., Bakishev, T., Zhao, D., Ranade, P., Roy, R., Wojko, M., Clark, L. T., Rogenmoser, R., Hori, M., Ema, T., Moriwaki, S., Tsuruta, T., Yamada, T., Mitani, J., & Wakayama, S. In CICC, pages 1-4, 2013. IEEE. Link Paper bibtex @inproceedings{conf/cicc/AgrawalKKKLBZRRWCRHEMTYMW13,
added-at = {2014-11-15T00:00:00.000+0100},
author = {Agrawal, Vineet and Kepler, N. and Kidd, David and Krishnan, Gokul and Leshner, Samuel and Bakishev, T. and Zhao, D. and Ranade, P. and Roy, R. and Wojko, M. and Clark, Lawrence T. and Rogenmoser, Robert and Hori, M. and Ema, T. and Moriwaki, S. and Tsuruta, T. and Yamada, T. and Mitani, J. and Wakayama, S.},
biburl = {http://www.bibsonomy.org/bibtex/218037edc4a9a29a1617185efc2d4f63e/dblp},
booktitle = {CICC},
crossref = {conf/cicc/2013},
ee = {http://dx.doi.org/10.1109/CICC.2013.6658514},
interhash = {89b1978744bd3e78ac9587cafea1c8f0},
intrahash = {18037edc4a9a29a1617185efc2d4f63e},
keywords = {dblp},
pages = {1-4},
publisher = {IEEE},
timestamp = {2015-06-18T19:50:44.000+0200},
title = {Low power ARM® Cortex™-M0 CPU and SRAM using Deeply Depleted Channel (DDC) transistors with Vdd scaling and body bias.},
url = {http://dblp.uni-trier.de/db/conf/cicc/cicc2013.html#AgrawalKKKLBZRRWCRHEMTYMW13},
year = 2013
}
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