@inproceedings{conf/isvlsi/AhmadC14,
  added-at = {2017-05-21T00:00:00.000+0200},
  author = {Ahmad, Tariq B. and Ciesielski, Maciej J.},
  biburl = {https://www.bibsonomy.org/bibtex/2f5ed6480dc39db71c2094e098c181f17/dblp},
  booktitle = {ISVLSI},
  crossref = {conf/isvlsi/2014},
  ee = {http://doi.ieeecomputersociety.org/10.1109/ISVLSI.2014.47},
  interhash = {2ace0f3ef3686d0f8aebaaac208d87e5},
  intrahash = {f5ed6480dc39db71c2094e098c181f17},
  isbn = {978-1-4799-3763-9},
  keywords = {dblp},
  pages = {619-624},
  publisher = {IEEE Computer Society},
  timestamp = {2019-10-17T13:45:51.000+0200},
  title = {Parallel Multi-core Verilog HDL Simulation Using Domain Partitioning.},
  url = {http://dblp.uni-trier.de/db/conf/isvlsi/isvlsi2014.html#AhmadC14},
  year = 2014
}

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