Runtime verification of nonlinear analog circuits using incremental time-augmented RRT algorithm. Ahmadyan, S. N., Kumar, J. A., & Vasudevan, S. In Design, Automation and Test in Europe, DATE 13, Grenoble, France, March 18-22, 2013, pages 21–26, 2013. EDA Consortium San Jose, CA, USA / ACM DL.
Runtime verification of nonlinear analog circuits using incremental time-augmented RRT algorithm [link]Paper  doi  bibtex   
@inproceedings{DBLP:conf/date/AhmadyanKV13,
  author    = {Seyed Nematollah Ahmadyan and
               Jayanand Asok Kumar and
               Shobha Vasudevan},
  editor    = {Enrico Macii},
  title     = {Runtime verification of nonlinear analog circuits using incremental
               time-augmented {RRT} algorithm},
  booktitle = {Design, Automation and Test in Europe, {DATE} 13, Grenoble, France,
               March 18-22, 2013},
  pages     = {21--26},
  publisher = {{EDA} Consortium San Jose, CA, {USA} / {ACM} {DL}},
  year      = {2013},
  url       = {https://doi.org/10.7873/DATE.2013.019},
  doi       = {10.7873/DATE.2013.019},
  timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
  biburl    = {https://dblp.org/rec/conf/date/AhmadyanKV13.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}

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