Process variation aware data management for magnetic skyrmions racetrack memory

Process variation aware data management for magnetic skyrmions racetrack memory. <a href="https://homes.luddy.indiana.edu/fc7/" target="_blank">Chen, Fan</a>, Li, Z., Kang, W., Zhao, W., Li, H., & Chen, Y. In 23rd Asia and South Pacific Design Automation Conference (ASP-DAC), pages 221–226, 2018. IEEE.

Paper doi abstract bibtex

Skyrmions racetrack memory (SKM) has been identified as a promising candidate for future on-chip cache. Similar to many other nanoscale technologies, process variations also adversely impact the reliability and performance of SKM cache. In this work, we propose the first holistic solution for employing SKM as last-level caches. We first present a novel SKM cache architecture and a physical-to-logic mapping scheme based on our comprehensive analysis on working mechanism of SKM. We then model the impact of process variations on SKM cache performance. By leveraging the developed model, we propose a process variation aware data management technique to minimize the performance degradation of SKM cache incurred by process variations. Experimental results show that the proposed SKM cache can achieve a geometric mean of 1.28x IPC improvement, 2x density increase, and 23% energy reduction compared to Domain Wall racetrack memory (DWM) under the same area constraint across 15 workloads. In addition, our dynamic data management technique can further improve the system IPC by 25% w.r.t. the worst-case design.

@inproceedings{ASPDAC18dw,
  author    = {{<a href="https://homes.luddy.indiana.edu/fc7/" target="_blank">Chen, Fan</a></span>} and
               Zheng Li and
               Wang Kang and
               Weisheng Zhao and
               Hai Li and
               Yiran Chen},
  title     = {Process variation aware data management for magnetic skyrmions racetrack
               memory},
  booktitle = {23rd Asia and South Pacific Design Automation Conference (ASP-DAC)},
  pages     = {221--226},
  publisher = {{IEEE}},
  year      = {2018},
  url       = {https://doi.org/10.1109/ASPDAC.2018.8297309},
  doi       = {10.1109/ASPDAC.2018.8297309},
  abstract  = {Skyrmions racetrack memory (SKM) has been identified as a promising candidate for future on-chip cache. Similar to many other nanoscale technologies, process variations also adversely impact the reliability and performance of SKM cache. In this work, we propose the first holistic solution for employing SKM as last-level caches. We first present a novel SKM cache architecture and a physical-to-logic mapping scheme based on our comprehensive analysis on working mechanism of SKM. We then model the impact of process variations on SKM cache performance. By leveraging the developed model, we propose a process variation aware data management technique to minimize the performance degradation of SKM cache incurred by process variations. Experimental results show that the proposed SKM cache can achieve a geometric mean of 1.28x IPC improvement, 2x density increase, and 23\% energy reduction compared to Domain Wall racetrack memory (DWM) under the same area constraint across 15 workloads. In addition, our dynamic data management technique can further improve the system IPC by 25\% w.r.t. the worst-case design.},
}

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