Wrapper design for the reuse of a bus, network-on-chip, or other functional interconnect as test access mechanism. Amory, A. M., Goossens, K., Marinissen, E. J., Lubaszewski, M., & Moraes, F. G. IET Computers & Digital Techniques, 1(3):197–206, 2007.
Paper bibtex @article{DBLP:journals/iet-cdt/AmoryGMLM07,
author = {Alexandre M. Amory and
Kees Goossens and
Erik Jan Marinissen and
Marcelo Lubaszewski and
Fernando Gehm Moraes},
title = {Wrapper design for the reuse of a bus, network-on-chip, or other functional
interconnect as test access mechanism},
journal = {{IET} Computers {\&} Digital Techniques},
volume = {1},
number = {3},
pages = {197--206},
year = {2007},
url = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=4205035},
timestamp = {Wed, 22 Jun 2011 01:00:00 +0200},
biburl = {http://dblp.uni-trier.de/rec/bib/journals/iet-cdt/AmoryGMLM07},
bibsource = {dblp computer science bibliography, http://dblp.org},
keywords = {noc,testing}
}
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