Test Time Reduction Reusing Multiple Processors in a Network-on-Chip Based Architecture. Amory, A. M., Lubaszewski, M., Moraes, F. G., & Moreno, E. I. CoRR, 2007.
Test Time Reduction Reusing Multiple Processors in a Network-on-Chip Based Architecture [link]Paper  bibtex   
@article{DBLP:journals/corr/abs-0710-4795,
  author       = {Alexandre M. Amory and
                  Marcelo Lubaszewski and
                  Fernando Gehm Moraes and
                  Edson I. Moreno},
  title        = {Test Time Reduction Reusing Multiple Processors in a Network-on-Chip
                  Based Architecture},
  journal      = {CoRR},
  volume       = {abs/0710.4795},
  year         = {2007},
  url          = {http://arxiv.org/abs/0710.4795},
  eprinttype    = {arXiv},
  eprint       = {0710.4795},
  timestamp    = {Mon, 13 Aug 2018 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/corr/abs-0710-4795.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

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