Test Time Reduction Reusing Multiple Processors in a Network-on-Chip Based Architecture. Amory, A. M., Lubaszewski, M., Moraes, F. G., & Moreno, E. I. CoRR, 2007.
Paper bibtex @article{DBLP:journals/corr/abs-0710-4795,
author = {Alexandre M. Amory and
Marcelo Lubaszewski and
Fernando Gehm Moraes and
Edson I. Moreno},
title = {Test Time Reduction Reusing Multiple Processors in a Network-on-Chip
Based Architecture},
journal = {CoRR},
volume = {abs/0710.4795},
year = {2007},
url = {http://arxiv.org/abs/0710.4795},
eprinttype = {arXiv},
eprint = {0710.4795},
timestamp = {Mon, 13 Aug 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-0710-4795.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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{"_id":"om6zs6eAsxZ2K6z8J","bibbaseid":"amory-lubaszewski-moraes-moreno-testtimereductionreusingmultipleprocessorsinanetworkonchipbasedarchitecture-2007","downloads":0,"creationDate":"2016-08-26T18:21:53.465Z","title":"Test Time Reduction Reusing Multiple Processors in a Network-on-Chip Based Architecture","author_short":["Amory, A. M.","Lubaszewski, M.","Moraes, F. G.","Moreno, E. I."],"year":2007,"bibtype":"article","biburl":"https://dblp.org/pid/m/FernandoGehmMoraes.bib","bibdata":{"bibtype":"article","type":"article","author":[{"firstnames":["Alexandre","M."],"propositions":[],"lastnames":["Amory"],"suffixes":[]},{"firstnames":["Marcelo"],"propositions":[],"lastnames":["Lubaszewski"],"suffixes":[]},{"firstnames":["Fernando","Gehm"],"propositions":[],"lastnames":["Moraes"],"suffixes":[]},{"firstnames":["Edson","I."],"propositions":[],"lastnames":["Moreno"],"suffixes":[]}],"title":"Test Time Reduction Reusing Multiple Processors in a Network-on-Chip Based Architecture","journal":"CoRR","volume":"abs/0710.4795","year":"2007","url":"http://arxiv.org/abs/0710.4795","eprinttype":"arXiv","eprint":"0710.4795","timestamp":"Mon, 13 Aug 2018 01:00:00 +0200","biburl":"https://dblp.org/rec/journals/corr/abs-0710-4795.bib","bibsource":"dblp computer science bibliography, https://dblp.org","bibtex":"@article{DBLP:journals/corr/abs-0710-4795,\n author = {Alexandre M. Amory and\n Marcelo Lubaszewski and\n Fernando Gehm Moraes and\n Edson I. Moreno},\n title = {Test Time Reduction Reusing Multiple Processors in a Network-on-Chip\n Based Architecture},\n journal = {CoRR},\n volume = {abs/0710.4795},\n year = {2007},\n url = {http://arxiv.org/abs/0710.4795},\n eprinttype = {arXiv},\n eprint = {0710.4795},\n timestamp = {Mon, 13 Aug 2018 01:00:00 +0200},\n biburl = {https://dblp.org/rec/journals/corr/abs-0710-4795.bib},\n bibsource = {dblp computer science bibliography, https://dblp.org}\n}\n\n","author_short":["Amory, A. M.","Lubaszewski, M.","Moraes, F. G.","Moreno, E. I."],"key":"DBLP:journals/corr/abs-0710-4795","id":"DBLP:journals/corr/abs-0710-4795","bibbaseid":"amory-lubaszewski-moraes-moreno-testtimereductionreusingmultipleprocessorsinanetworkonchipbasedarchitecture-2007","role":"author","urls":{"Paper":"http://arxiv.org/abs/0710.4795"},"metadata":{"authorlinks":{"moraes, f":"https://fgmoraes.github.io/frames/pub_bibbase.html"}},"downloads":0},"search_terms":["test","time","reduction","reusing","multiple","processors","network","chip","based","architecture","amory","lubaszewski","moraes","moreno"],"keywords":[],"authorIDs":["57c091645abfdd4d54000320","aZmE7qmCtnswuExac"],"dataSources":["pEib8arMvtjpTWFyZ","ZnKvBZN9FDvFao2cx"]}