Software-Based Test for Nonprogrammable Cores in Bus-Based System-On-Chip Architectures

Software-Based Test for Nonprogrammable Cores in Bus-Based System-On-Chip Architectures. Amory, A. M., Oliveira, L. A., & Moraes, F. G. In Glesner, M., da Luz Reis, R. A., Indrusiak, L. S., III, V. J. M., & Eveking, H., editors, VLSI-SOC: From Systems to Chips - IFIP TC 10/ WG 10.5 Twelfth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC 2003), December 1-3, 2003, Darmstadt, Germany, volume 200, of IFIP, pages 165–179, 2003. Springer.

Paper doi bibtex

@inproceedings{DBLP:conf/vlsi/AmoryOM03a,
  author       = {Alexandre M. Amory and
                  Leandro A. Oliveira and
                  Fernando Gehm Moraes},
  editor       = {Manfred Glesner and
                  Ricardo Augusto da Luz Reis and
                  Leandro Soares Indrusiak and
                  Vincent John Mooney III and
                  Hans Eveking},
  title        = {Software-Based Test for Nonprogrammable Cores in Bus-Based System-On-Chip
                  Architectures},
  booktitle    = {{VLSI-SOC:} From Systems to Chips - {IFIP} {TC} 10/ {WG} 10.5 Twelfth
                  International Conference on Very Large Scale Integration of System
                  on Chip (VLSI-SoC 2003), December 1-3, 2003, Darmstadt, Germany},
  series       = {{IFIP}},
  volume       = {200},
  pages        = {165--179},
  publisher    = {Springer},
  year         = {2003},
  url          = {https://doi.org/10.1007/0-387-33403-3\_11},
  doi          = {10.1007/0-387-33403-3\_11},
  timestamp    = {Wed, 25 Sep 2019 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/vlsi/AmoryOM03a.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

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