{"_id":"HgjegbmatMQaDFY45","bibbaseid":"andraus-liffiton-sakallah-revealaformalverificationtoolforverilogdesigns-2008","authorIDs":["2A54n82RLui3DP6wP","2e3wBxbR54jNNzizE","4aNcyxEg4ftuNSsaj","4gdthdEfvkFauifZf","58ggzMh94vktbZgLD","5K3DrmPuzFQkm7Mao","5d1ca3b659fe2fda01000020","5de76e32179cbdde01000158","5e01698f219bd5df01000062","5e14c31ee55ed8de01000123","5e1f7edc08195af30100007d","5e399082d14579de010001b7","5e3d9802f33211df01000055","5e5d058b342171f301000093","5e5ece2a8c261adf010000ca","5e5ed0648c261adf01000101","6gRo3HNBCyPc4x2tE","78zghoXffPeSigRcS","7Er9ECfumNZ9Tx7zP","7WdeScG3KXCpjHymh","89qMihECpRRWWyFkY","8Scex5wFP2m5WqrNm","9reHcTXwN9LWaskcF","A5488F9AoWmk8qbcd","CCXLwWMqAsRK8XkP3","CTMnmJ2FT5X3o2dt6","DnyyYXDJrA4YcnFut","DyNvt8RRvSYuDtp4H","EvzyWsDjCchvN8r9W","Fuw6YbxyzPv64d4oz","Hegw9jgkkSqLYJpCs","LC6adHEfDkmH63Db3","MeFQDLkpfxLC4F6iD","NQyf7Hh3HuMggYif7","NZQc6xvT9aa2rbkPF","QG7t9hm6rKCbkWpw4","QT9sJuhXJYhgiCbbP","S82QTbwajuiwoPLtM","SSY46YraYDnEZ8j35","SbhHiDFf7kNQMXyTw","TGzEJy5rj4cMrvLaF","TdoMPd7r7jW4PzqfB","WEMsDvNfiLSN3nM9P","WPLDufsuBHpqtRscS","X2b5tEpaJowqtbAKb","XNGQ6BdxRkddPkcDW","XcWuJQmWvotMnc8YA","YcAeLPsxPrnmvk3AQ","YgnWwStEzHtnChSnw","ci6eqpfrfcwfxHJeM","dTh6pHKqGWGchnbaL","efWMWCByZJW6uHj9a","hmfBnbuF4YmbpmC5J","iLTY6YXJF6THy9Lyc","it4tcbLoXrHNFam9f","jbE52xarsJTXAD8ma","koH6hayagychucm5f","m99WHWDWEst645cN7","oaAAqRsRz4HbWumXj","oqxgYgKwShbabAPDg","pBbKC63DknjWpXv6f","pgcvBWkwJHeWDSePe","qeWoMcKfQEvNqnkct","uxQRXFz86d3WXaut2","vAj2ZYa4B6YQCJqPY","vepX2hk9vhCZqMmur","wfRrXWqYC8yynYHdz","yNHRpnaKGh5K9w3Y4","yXMoKynEJwXBrgPgg"],"author_short":["Andraus, Z. S.","Liffiton, M. H.","Sakallah, K. A."],"bibdata":{"bibtype":"inproceedings","type":"inproceedings","author":[{"propositions":[],"lastnames":["Andraus"],"firstnames":["Zaher","S."],"suffixes":[]},{"propositions":[],"lastnames":["Liffiton"],"firstnames":["Mark","H."],"suffixes":[]},{"propositions":[],"lastnames":["Sakallah"],"firstnames":["Karem","A."],"suffixes":[]}],"title":"Reveal: A Formal Verification Tool for Verilog Designs","booktitle":"International Conference on Logic for Programming, Artificial Intelligence, and Reasoning (LPAR'08)","address":"Doha, Qatar","publisher":"Springer","volume":"LNCS 5330","pages":"343-352","month":"November","year":"2008","bibtex":"@inproceedings{andraus2008reveal,\n author = {Andraus, Zaher S. and Liffiton, Mark H. and Sakallah, Karem A.},\n title = {{Reveal: A Formal Verification Tool for Verilog Designs}},\n booktitle = {International Conference on Logic for Programming, Artificial Intelligence, and Reasoning (LPAR'08)},\n address = {Doha, Qatar},\n publisher = {Springer},\n volume = {LNCS 5330},\n pages = {343-352},\n month = {November},\n year = {2008}\n}\n\n","author_short":["Andraus, Z. S.","Liffiton, M. H.","Sakallah, K. A."],"key":"andraus2008reveal","id":"andraus2008reveal","bibbaseid":"andraus-liffiton-sakallah-revealaformalverificationtoolforverilogdesigns-2008","role":"author","urls":{},"metadata":{"authorlinks":{"sakallah, k":"https://web.eecs.umich.edu/~karem/publications/"}},"downloads":0},"bibtype":"inproceedings","biburl":"http://web.eecs.umich.edu/~karem/publications/Sakallah-Publications.bib","creationDate":"2019-07-03T12:46:46.314Z","downloads":0,"keywords":[],"search_terms":["reveal","formal","verification","tool","verilog","designs","andraus","liffiton","sakallah"],"title":"Reveal: A Formal Verification Tool for Verilog Designs","year":2008,"dataSources":["dAWPbXiJP4ihEN4GZ"]}