From 1G to 10G: code reuse in action

From 1G to 10G: code reuse in action. Antichi, G., Shahbaz, M., Giordano, S., & Moore, A. In Proceedings of the first edition workshop on High performance and programmable networking, pages 31–38, Jul, 2013.
doi abstract bibtex

Ever increasing traffic quantities and link-bandwidths force network devices to meet ever-increasing demands; the march to 100G is well under way. The high-speed networking of today is no longer that of five years ago: Unfortunately, such growth contrasts with current financial forces and this leads organisations to find ways to save money. As a result many developers face the common problem: how to make existing, systems reusable in this new, higher-speed scenario? To attack this problem, we propose new, flexible, legacy support mechanics for designs built using System on a Chip (SoC) and System on FPGA (SoFPGA). We illustrate our approach using the widely used, open-source, NetFPGA platform presenting a migration path for existing 1G designs to plugin into the new NetFPGA 10G board without alteration to code structure. © 2013 ACM.

@InProceedings{Antichi20131G,
  author            = {Antichi, Gianni and Shahbaz, Muhammad and Giordano, Stefano and Moore, Andrew},
  booktitle         = {Proceedings of the first edition workshop on High performance and programmable networking},
  title             = {{From 1G to 10G: code reuse in action}},
  year              = {2013},
  month             = {Jul},
  pages             = {31--38},
  abstract          = {Ever increasing traffic quantities and link-bandwidths force network devices to meet ever-increasing demands; the march to 100G is well under way. The high-speed networking of today is no longer that of five years ago: Unfortunately, such growth contrasts with current financial forces and this leads organisations to find ways to save money. As a result many developers face the common problem: how to make existing, systems reusable in this new, higher-speed scenario? To attack this problem, we propose new, flexible, legacy support mechanics for designs built using System on a Chip (SoC) and System on FPGA (SoFPGA). We illustrate our approach using the widely used, open-source, NetFPGA platform presenting a migration path for existing 1G designs to plugin into the new NetFPGA 10G board without alteration to code structure. © 2013 ACM.},
  day               = {17},
  doi               = {10.1145/2465839.2465844},
  journal           = {HPPN 2013 - Proceedings of the 2013 ACM Workshop on High Performance and Programmable Networking},
  publicationstatus = {published},
}

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