Efficient arithmetic logic gates using double-gate silicon nanowire FETs

Efficient arithmetic logic gates using double-gate silicon nanowire FETs. Arnani, L., Gaillardon, P., & Micheli, G. D. In IEEE 11th International New Circuits and Systems Conference, NEWCAS 2013, Paris, France, June 16-19, 2013, pages 1–4, 2013.

Paper doi bibtex

@inproceedings{DBLP:conf/newcas/ArnaniGM13,
  author    = {Luca Arnani and
               Pierre{-}Emmanuel Gaillardon and
               Giovanni De Micheli},
  title     = {Efficient arithmetic logic gates using double-gate silicon nanowire
               FETs},
  booktitle = {{IEEE} 11th International New Circuits and Systems Conference, {NEWCAS}
               2013, Paris, France, June 16-19, 2013},
  pages     = {1--4},
  year      = {2013},
  crossref  = {DBLP:conf/newcas/2013},
  url       = {https://doi.org/10.1109/NEWCAS.2013.6573572},
  doi       = {10.1109/NEWCAS.2013.6573572},
  timestamp = {Wed, 16 Oct 2019 14:14:54 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/newcas/ArnaniGM13},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}

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