Verification of RTL generated from scheduled behavior in a high-level synthesis flow. Ashar, P., Bhattacharya, S., Raghunathan, A., & Mukaiyama, A. In Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1998, San Jose, CA, USA, November 8-12, 1998, pages 517–524, 1998.
Verification of RTL generated from scheduled behavior in a high-level synthesis flow [link]Paper  doi  bibtex   
@inproceedings{DBLP:conf/iccad/AsharBRM98,
  author    = {Pranav Ashar and
               Subhrajit Bhattacharya and
               Anand Raghunathan and
               Akira Mukaiyama},
  title     = {Verification of {RTL} generated from scheduled behavior in a high-level
               synthesis flow},
  booktitle = {Proceedings of the 1998 {IEEE/ACM} International Conference on Computer-Aided
               Design, {ICCAD} 1998, San Jose, CA, USA, November 8-12, 1998},
  pages     = {517--524},
  year      = {1998},
  crossref  = {DBLP:conf/iccad/1998},
  url       = {http://doi.acm.org/10.1145/288548.289080},
  doi       = {10.1145/288548.289080},
  timestamp = {Thu, 30 Apr 2015 18:34:30 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/iccad/AsharBRM98},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
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