Verification of Scheduling in the Presence of Loops Using Uninterpreted Symbolic Simulation. Ashar, P.; Raghunathan, A.; Gupta, A.; and Bhattacharya, S. In Proceedings of the IEEE International Conference On Computer Design, VLSI in Computers and Processors, ICCD '99, Austin, Texas, USA, October 10-13, 1999, pages 458–466, 1999.
Verification of Scheduling in the Presence of Loops Using Uninterpreted Symbolic Simulation [link]Paper  doi  bibtex   
@inproceedings{DBLP:conf/iccd/AsharRGB99,
  author    = {Pranav Ashar and
               Anand Raghunathan and
               Aarti Gupta and
               Subhrajit Bhattacharya},
  title     = {Verification of Scheduling in the Presence of Loops Using Uninterpreted
               Symbolic Simulation},
  booktitle = {Proceedings of the {IEEE} International Conference On Computer Design,
               {VLSI} in Computers and Processors, {ICCD} '99, Austin, Texas, USA,
               October 10-13, 1999},
  pages     = {458--466},
  year      = {1999},
  crossref  = {DBLP:conf/iccd/1999},
  url       = {https://doi.org/10.1109/ICCD.1999.808581},
  doi       = {10.1109/ICCD.1999.808581},
  timestamp = {Wed, 24 May 2017 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/iccd/AsharRGB99},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
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