@inproceedings{DBLP:conf/iccd/AsharRGB99,
  author    = {Pranav Ashar and
               Anand Raghunathan and
               Aarti Gupta and
               Subhrajit Bhattacharya},
  title     = {Verification of Scheduling in the Presence of Loops Using Uninterpreted
               Symbolic Simulation},
  booktitle = {Proceedings of the {IEEE} International Conference On Computer Design,
               {VLSI} in Computers and Processors, {ICCD} '99, Austin, Texas, USA,
               October 10-13, 1999},
  pages     = {458--466},
  year      = {1999},
  crossref  = {DBLP:conf/iccd/1999},
  url       = {https://doi.org/10.1109/ICCD.1999.808581},
  doi       = {10.1109/ICCD.1999.808581},
  timestamp = {Wed, 24 May 2017 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/iccd/AsharRGB99},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}

{"_id":"FYBFjPnw6vHanYb2d","bibbaseid":"ashar-raghunathan-gupta-bhattacharya-verificationofschedulinginthepresenceofloopsusinguninterpretedsymbolicsimulation-1999","downloads":0,"creationDate":"2018-06-20T07:11:31.784Z","title":"Verification of Scheduling in the Presence of Loops Using Uninterpreted Symbolic Simulation","author_short":["Ashar, P.","Raghunathan, A.","Gupta, A.","Bhattacharya, S."],"year":1999,"bibtype":"inproceedings","biburl":"https://dblp.org/pid/74/3747.bib","bibdata":{"bibtype":"inproceedings","type":"inproceedings","author":[{"firstnames":["Pranav"],"propositions":[],"lastnames":["Ashar"],"suffixes":[]},{"firstnames":["Anand"],"propositions":[],"lastnames":["Raghunathan"],"suffixes":[]},{"firstnames":["Aarti"],"propositions":[],"lastnames":["Gupta"],"suffixes":[]},{"firstnames":["Subhrajit"],"propositions":[],"lastnames":["Bhattacharya"],"suffixes":[]}],"title":"Verification of Scheduling in the Presence of Loops Using Uninterpreted Symbolic Simulation","booktitle":"Proceedings of the IEEE International Conference On Computer Design, VLSI in Computers and Processors, ICCD '99, Austin, Texas, USA, October 10-13, 1999","pages":"458–466","year":"1999","crossref":"DBLP:conf/iccd/1999","url":"https://doi.org/10.1109/ICCD.1999.808581","doi":"10.1109/ICCD.1999.808581","timestamp":"Wed, 24 May 2017 01:00:00 +0200","biburl":"https://dblp.org/rec/bib/conf/iccd/AsharRGB99","bibsource":"dblp computer science bibliography, https://dblp.org","bibtex":"@inproceedings{DBLP:conf/iccd/AsharRGB99,\n author = {Pranav Ashar and\n Anand Raghunathan and\n Aarti Gupta and\n Subhrajit Bhattacharya},\n title = {Verification of Scheduling in the Presence of Loops Using Uninterpreted\n Symbolic Simulation},\n booktitle = {Proceedings of the {IEEE} International Conference On Computer Design,\n {VLSI} in Computers and Processors, {ICCD} '99, Austin, Texas, USA,\n October 10-13, 1999},\n pages = {458--466},\n year = {1999},\n crossref = {DBLP:conf/iccd/1999},\n url = {https://doi.org/10.1109/ICCD.1999.808581},\n doi = {10.1109/ICCD.1999.808581},\n timestamp = {Wed, 24 May 2017 01:00:00 +0200},\n biburl = {https://dblp.org/rec/bib/conf/iccd/AsharRGB99},\n bibsource = {dblp computer science bibliography, https://dblp.org}\n}\n\n","author_short":["Ashar, P.","Raghunathan, A.","Gupta, A.","Bhattacharya, S."],"key":"DBLP:conf/iccd/AsharRGB99","id":"DBLP:conf/iccd/AsharRGB99","bibbaseid":"ashar-raghunathan-gupta-bhattacharya-verificationofschedulinginthepresenceofloopsusinguninterpretedsymbolicsimulation-1999","role":"author","urls":{"Paper":"https://doi.org/10.1109/ICCD.1999.808581"},"downloads":0},"search_terms":["verification","scheduling","presence","loops","using","uninterpreted","symbolic","simulation","ashar","raghunathan","gupta","bhattacharya"],"keywords":[],"authorIDs":[],"dataSources":["QATSsZPCAGgNRpLA3"]}