Scalable and Memory-Efficient Spin Locks for Embedded Tile-Based Many-Core Architectures. Awamoto, S., Chishiro, H., & Kato, S. In 21st IEEE International Symposium on Real-Time Distributed Computing, ISORC 2018, Singapore, Singapore, May 29-31, 2018, pages 25–32, 2018. IEEE Computer Society.
Scalable and Memory-Efficient Spin Locks for Embedded Tile-Based Many-Core Architectures [link]Paper  doi  bibtex   
@inproceedings{DBLP:conf/isorc/AwamotoCK18,
  author    = {Shinichi Awamoto and
               Hiroyuki Chishiro and
               Shinpei Kato},
  title     = {Scalable and Memory-Efficient Spin Locks for Embedded Tile-Based Many-Core
               Architectures},
  booktitle = {21st {IEEE} International Symposium on Real-Time Distributed Computing,
               {ISORC} 2018, Singapore, Singapore, May 29-31, 2018},
  pages     = {25--32},
  publisher = {{IEEE} Computer Society},
  year      = {2018},
  url       = {https://doi.org/10.1109/ISORC.2018.00012},
  doi       = {10.1109/ISORC.2018.00012},
  timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
  biburl    = {https://dblp.org/rec/conf/isorc/AwamotoCK18.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}

Downloads: 0