@article{ayav_towards_2010,
	title = {Towards test case generation for synthesizable {VHDL} programs using model checker},
	url = {https://core.ac.uk/display/324142051?recSetID=},
	doi = {10/cgptnw},
	abstract = {4th IEEE International Conference on Secure Software Integration and Reliability Improvement Companion, SSIRI-C 2010; Singapore; Singapore; 9 June 2010 through 11 June 2010VHDL programs are often tested by means of simulations, relying on test benches written intuitively. In this paper, we propose a formal approach to construct test benches from system specification. To consider the real-time properties of VHDL programs, we first transform them to timed automata and then perform model checking against the properties designated from the specification. Counterexamples returned from the model checker serve as a basis of test cases, i.e. they are used to form a test bench. The approach is demonstrated and complemented by a simple case study},
	language = {en-gb},
	urldate = {2021-01-27},
	author = {Ayav, Tolga and Tuğlular, Tuğkan and Belli, Fevzi},
	year = {2010},
}

{"_id":"HcZHLeWHnH3P52xxH","bibbaseid":"ayav-tulular-belli-towardstestcasegenerationforsynthesizablevhdlprogramsusingmodelchecker-2010","author_short":["Ayav, T.","Tuğlular, T.","Belli, F."],"bibdata":{"bibtype":"article","type":"article","title":"Towards test case generation for synthesizable VHDL programs using model checker","url":"https://core.ac.uk/display/324142051?recSetID=","doi":"10/cgptnw","abstract":"4th IEEE International Conference on Secure Software Integration and Reliability Improvement Companion, SSIRI-C 2010; Singapore; Singapore; 9 June 2010 through 11 June 2010VHDL programs are often tested by means of simulations, relying on test benches written intuitively. In this paper, we propose a formal approach to construct test benches from system specification. To consider the real-time properties of VHDL programs, we first transform them to timed automata and then perform model checking against the properties designated from the specification. Counterexamples returned from the model checker serve as a basis of test cases, i.e. they are used to form a test bench. The approach is demonstrated and complemented by a simple case study","language":"en-gb","urldate":"2021-01-27","author":[{"propositions":[],"lastnames":["Ayav"],"firstnames":["Tolga"],"suffixes":[]},{"propositions":[],"lastnames":["Tuğlular"],"firstnames":["Tuğkan"],"suffixes":[]},{"propositions":[],"lastnames":["Belli"],"firstnames":["Fevzi"],"suffixes":[]}],"year":"2010","bibtex":"@article{ayav_towards_2010,\n\ttitle = {Towards test case generation for synthesizable {VHDL} programs using model checker},\n\turl = {https://core.ac.uk/display/324142051?recSetID=},\n\tdoi = {10/cgptnw},\n\tabstract = {4th IEEE International Conference on Secure Software Integration and Reliability Improvement Companion, SSIRI-C 2010; Singapore; Singapore; 9 June 2010 through 11 June 2010VHDL programs are often tested by means of simulations, relying on test benches written intuitively. In this paper, we propose a formal approach to construct test benches from system specification. To consider the real-time properties of VHDL programs, we first transform them to timed automata and then perform model checking against the properties designated from the specification. Counterexamples returned from the model checker serve as a basis of test cases, i.e. they are used to form a test bench. The approach is demonstrated and complemented by a simple case study},\n\tlanguage = {en-gb},\n\turldate = {2021-01-27},\n\tauthor = {Ayav, Tolga and Tuğlular, Tuğkan and Belli, Fevzi},\n\tyear = {2010},\n}\n\n","author_short":["Ayav, T.","Tuğlular, T.","Belli, F."],"key":"ayav_towards_2010","id":"ayav_towards_2010","bibbaseid":"ayav-tulular-belli-towardstestcasegenerationforsynthesizablevhdlprogramsusingmodelchecker-2010","role":"author","urls":{"Paper":"https://core.ac.uk/display/324142051?recSetID="},"metadata":{"authorlinks":{}},"html":""},"bibtype":"article","biburl":"https://bibbase.org/zotero/SilverSylvester","dataSources":["YCBcQPneB9oxahSnp"],"keywords":[],"search_terms":["towards","test","case","generation","synthesizable","vhdl","programs","using","model","checker","ayav","tuğlular","belli"],"title":"Towards test case generation for synthesizable VHDL programs using model checker","year":2010}