A 128∶2048/1536 point FFT hardware implementation with output pruning. Ayhan, T., Dehaene, W., & Verhelst, M. In 2014 22nd European Signal Processing Conference (EUSIPCO), pages 266-270, Sep., 2014. abstract bibtex In this work, an FFT architecture supporting variable FFT sizes, 128 2048/1536, is proposed. This implementation is a combination of a 2p point Common Factor FFT and a 3 point DFT. Various FFT output pruning techniques for this architecture are discussed in terms of memory and control logic overhead. It is shown that the used Prime Factor FFT as an FFT in the 1536 point FFT is able to increase throughput by exploiting single tone pruning with low control logic overhead. The proposed FFT processor is implemented on a Xilinx Virtex 5 FPGA. It occupies only 3148 LUTs and 612 kb memory in FGPA and calculates 1536 point FFT less than 3092 clock cycles with output pruned settings.
@InProceedings{6952032,
author = {T. Ayhan and W. Dehaene and M. Verhelst},
booktitle = {2014 22nd European Signal Processing Conference (EUSIPCO)},
title = {A 128∶2048/1536 point FFT hardware implementation with output pruning},
year = {2014},
pages = {266-270},
abstract = {In this work, an FFT architecture supporting variable FFT sizes, 128~2048/1536, is proposed. This implementation is a combination of a 2p point Common Factor FFT and a 3 point DFT. Various FFT output pruning techniques for this architecture are discussed in terms of memory and control logic overhead. It is shown that the used Prime Factor FFT as an FFT in the 1536 point FFT is able to increase throughput by exploiting single tone pruning with low control logic overhead. The proposed FFT processor is implemented on a Xilinx Virtex 5 FPGA. It occupies only 3148 LUTs and 612 kb memory in FGPA and calculates 1536 point FFT less than 3092 clock cycles with output pruned settings.},
keywords = {fast Fourier transforms;field programmable gate arrays;FFT hardware implementation;output pruning;FFT architecture;common factor FFT;FFT output pruning;control logic;memory logic;prime factor FFT;Xilinx Virtex 5 FPGA;Fast Fourier Transform;Discrete Fourier transforms;Computer architecture;Hardware;Throughput;Field programmable gate arrays;Indexes;Signal processing;FFT Pruning;FPGA Implementation;LTE;Variable size FFT;Prime Factor FFT},
issn = {2076-1465},
month = {Sep.},
}
Downloads: 0
{"_id":"BZWLPSDdtr38deNMw","bibbaseid":"ayhan-dehaene-verhelst-a12820481536pointffthardwareimplementationwithoutputpruning-2014","authorIDs":[],"author_short":["Ayhan, T.","Dehaene, W.","Verhelst, M."],"bibdata":{"bibtype":"inproceedings","type":"inproceedings","author":[{"firstnames":["T."],"propositions":[],"lastnames":["Ayhan"],"suffixes":[]},{"firstnames":["W."],"propositions":[],"lastnames":["Dehaene"],"suffixes":[]},{"firstnames":["M."],"propositions":[],"lastnames":["Verhelst"],"suffixes":[]}],"booktitle":"2014 22nd European Signal Processing Conference (EUSIPCO)","title":"A 128∶2048/1536 point FFT hardware implementation with output pruning","year":"2014","pages":"266-270","abstract":"In this work, an FFT architecture supporting variable FFT sizes, 128 2048/1536, is proposed. This implementation is a combination of a 2p point Common Factor FFT and a 3 point DFT. Various FFT output pruning techniques for this architecture are discussed in terms of memory and control logic overhead. It is shown that the used Prime Factor FFT as an FFT in the 1536 point FFT is able to increase throughput by exploiting single tone pruning with low control logic overhead. The proposed FFT processor is implemented on a Xilinx Virtex 5 FPGA. It occupies only 3148 LUTs and 612 kb memory in FGPA and calculates 1536 point FFT less than 3092 clock cycles with output pruned settings.","keywords":"fast Fourier transforms;field programmable gate arrays;FFT hardware implementation;output pruning;FFT architecture;common factor FFT;FFT output pruning;control logic;memory logic;prime factor FFT;Xilinx Virtex 5 FPGA;Fast Fourier Transform;Discrete Fourier transforms;Computer architecture;Hardware;Throughput;Field programmable gate arrays;Indexes;Signal processing;FFT Pruning;FPGA Implementation;LTE;Variable size FFT;Prime Factor FFT","issn":"2076-1465","month":"Sep.","bibtex":"@InProceedings{6952032,\n author = {T. Ayhan and W. Dehaene and M. Verhelst},\n booktitle = {2014 22nd European Signal Processing Conference (EUSIPCO)},\n title = {A 128∶2048/1536 point FFT hardware implementation with output pruning},\n year = {2014},\n pages = {266-270},\n abstract = {In this work, an FFT architecture supporting variable FFT sizes, 128~2048/1536, is proposed. This implementation is a combination of a 2p point Common Factor FFT and a 3 point DFT. Various FFT output pruning techniques for this architecture are discussed in terms of memory and control logic overhead. It is shown that the used Prime Factor FFT as an FFT in the 1536 point FFT is able to increase throughput by exploiting single tone pruning with low control logic overhead. The proposed FFT processor is implemented on a Xilinx Virtex 5 FPGA. It occupies only 3148 LUTs and 612 kb memory in FGPA and calculates 1536 point FFT less than 3092 clock cycles with output pruned settings.},\n keywords = {fast Fourier transforms;field programmable gate arrays;FFT hardware implementation;output pruning;FFT architecture;common factor FFT;FFT output pruning;control logic;memory logic;prime factor FFT;Xilinx Virtex 5 FPGA;Fast Fourier Transform;Discrete Fourier transforms;Computer architecture;Hardware;Throughput;Field programmable gate arrays;Indexes;Signal processing;FFT Pruning;FPGA Implementation;LTE;Variable size FFT;Prime Factor FFT},\n issn = {2076-1465},\n month = {Sep.},\n}\n\n","author_short":["Ayhan, T.","Dehaene, W.","Verhelst, M."],"key":"6952032","id":"6952032","bibbaseid":"ayhan-dehaene-verhelst-a12820481536pointffthardwareimplementationwithoutputpruning-2014","role":"author","urls":{},"keyword":["fast Fourier transforms;field programmable gate arrays;FFT hardware implementation;output pruning;FFT architecture;common factor FFT;FFT output pruning;control logic;memory logic;prime factor FFT;Xilinx Virtex 5 FPGA;Fast Fourier Transform;Discrete Fourier transforms;Computer architecture;Hardware;Throughput;Field programmable gate arrays;Indexes;Signal processing;FFT Pruning;FPGA Implementation;LTE;Variable size FFT;Prime Factor FFT"],"metadata":{"authorlinks":{}},"downloads":0},"bibtype":"inproceedings","biburl":"https://raw.githubusercontent.com/Roznn/EUSIPCO/main/eusipco2014url.bib","creationDate":"2021-02-13T17:43:41.588Z","downloads":0,"keywords":["fast fourier transforms;field programmable gate arrays;fft hardware implementation;output pruning;fft architecture;common factor fft;fft output pruning;control logic;memory logic;prime factor fft;xilinx virtex 5 fpga;fast fourier transform;discrete fourier transforms;computer architecture;hardware;throughput;field programmable gate arrays;indexes;signal processing;fft pruning;fpga implementation;lte;variable size fft;prime factor fft"],"search_terms":["128","2048","1536","point","fft","hardware","implementation","output","pruning","ayhan","dehaene","verhelst"],"title":"A 128∶2048/1536 point FFT hardware implementation with output pruning","year":2014,"dataSources":["A2ezyFL6GG6na7bbs","oZFG3eQZPXnykPgnE"]}