{"_id":"zFne8uRsQiEJhcRKK","bibbaseid":"bae-park-jaerhee-bumko-jeong-noh-son-youn-etal-a12v30nm16gbspin4gblpddr3sdramwithinputskewcalibrationandenhancedcontrolscheme-2012","downloads":0,"creationDate":"2016-02-10T20:02:42.835Z","title":"A 1.2V 30nm 1.6Gb/s/pin 4Gb LPDDR3 SDRAM with input skew calibration and enhanced control scheme","author_short":["Bae, Y.","Park, J.","Jae Rhee, S.","Bum Ko, S.","Jeong, Y.","Noh, K.","Son, Y.","Youn, J.","Chu, Y.","Cho, H.","Kim, M.","Yim, D.","Kim, H.","Jung, S.","Choi, H.","Yim, S.","Lee, J.","Choi, J.","Oh, K."],"year":2012,"bibtype":"inproceedings","biburl":"http://www.dblp.org/rec/bibtex/conf/isscc/BaePRKJNSYCCKYKJCYLCO12","bibdata":{"title":"A 1.2V 30nm 1.6Gb/s/pin 4Gb LPDDR3 SDRAM with input skew calibration and enhanced control scheme","author":["Yong-Cheol Bae","Joon-Young Park","Sang Jae Rhee","Seung Bum Ko","Yonggwon Jeong","Kwang-Sook Noh","Younghoon Son","Jaeyoun Youn","Yonggyu Chu","Hyunyoon Cho","Mijo Kim","Daesik Yim","Hyo-Chang Kim","Sang-Hoon Jung","Hye-In Choi","Sungmin Yim","Jung-Bae Lee","Joo-Sun Choi","Kyungseok Oh"],"author_short":["Bae, Y.","Park, J.","Jae Rhee, S.","Bum Ko, S.","Jeong, Y.","Noh, K.","Son, Y.","Youn, J.","Chu, Y.","Cho, H.","Kim, M.","Yim, D.","Kim, H.","Jung, S.","Choi, H.","Yim, S.","Lee, J.","Choi, J.","Oh, K."],"bibtype":"inproceedings","type":"inproceedings","year":"2012","key":"dblp2562145","id":"dblp2562145","biburl":"http://www.dblp.org/rec/bibtex/conf/isscc/BaePRKJNSYCCKYKJCYLCO12","url":"http://dx.doi.org/10.1109/ISSCC.2012.6176871","conference":"ISSCC","pages":"44-46","text":"ISSCC 2012:44-46","booktitle":"Proceedings of International Solid-State Circuits Conference (ISSCC)","bibtex":"@inproceedings{ dblp2562145,\n title = {A 1.2V 30nm 1.6Gb/s/pin 4Gb LPDDR3 SDRAM with input skew calibration and enhanced control scheme},\n author = {Yong-Cheol Bae and Joon-Young Park and Sang Jae Rhee and Seung Bum Ko and Yonggwon Jeong and Kwang-Sook Noh and Younghoon Son and Jaeyoun Youn and Yonggyu Chu and Hyunyoon Cho and Mijo Kim and Daesik Yim and Hyo-Chang Kim and Sang-Hoon Jung and Hye-In Choi and Sungmin Yim and Jung-Bae Lee and Joo-Sun Choi and Kyungseok Oh},\n author_short = {Bae, Y. and Park, J. and Jae Rhee, S. and Bum Ko, S. and Jeong, Y. and Noh, K. and Son, Y. and Youn, J. and Chu, Y. and Cho, H. and Kim, M. and Yim, D. and Kim, H. and Jung, S. and Choi, H. and Yim, S. and Lee, J. and Choi, J. and Oh, K.},\n bibtype = {inproceedings},\n type = {inproceedings},\n year = {2012},\n key = {dblp2562145},\n id = {dblp2562145},\n biburl = {http://www.dblp.org/rec/bibtex/conf/isscc/BaePRKJNSYCCKYKJCYLCO12},\n url = {http://dx.doi.org/10.1109/ISSCC.2012.6176871},\n conference = {ISSCC},\n pages = {44-46},\n text = {ISSCC 2012:44-46},\n booktitle = {Proceedings of International Solid-State Circuits Conference (ISSCC)}\n}","bibbaseid":"bae-park-jaerhee-bumko-jeong-noh-son-youn-etal-a12v30nm16gbspin4gblpddr3sdramwithinputskewcalibrationandenhancedcontrolscheme-2012","role":"author","urls":{"Paper":"http://dx.doi.org/10.1109/ISSCC.2012.6176871"},"downloads":0},"search_terms":["30nm","6gb","pin","4gb","lpddr3","sdram","input","skew","calibration","enhanced","control","scheme","bae","park","jae rhee","bum ko","jeong","noh","son","youn","chu","cho","kim","yim","kim","jung","choi","yim","lee","choi","oh"],"keywords":[],"authorIDs":[],"dataSources":["ebvKMLfyNrrREuwNk"]}