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In this paper, we introduce our CMOS block MAtrix Transform Imager Architecture (MATIA). This imager is capable of performing programmable matrix operations on an image. The imager architecture is both modular and programmable. The pixel used in this architecture performs matrix multiplication while maintaining a high fill factor (46%), comparable to active pixel sensors. Floating gates are used to store the arbitrary matrix coefficients on-chip. The chip operates in the subthreshold domain and thus has low power consumption (80 μW/frame). We present data for different convolutions and block transforms that were implemented using this architecture, and also present data from baseline JPEG and motion JPEG systems which we have implemented using MATIA.

@article{bandyopadhyay_matia:_2006, title = {{MATIA}: a programmable 80 mu;{W}/frame {CMOS} block matrix transform imager architecture}, volume = {41}, issn = {0018-9200}, shorttitle = {{MATIA}}, doi = {10.1109/JSSC.2005.864115}, abstract = {In this paper, we introduce our CMOS block MAtrix Transform Imager Architecture (MATIA). This imager is capable of performing programmable matrix operations on an image. The imager architecture is both modular and programmable. The pixel used in this architecture performs matrix multiplication while maintaining a high fill factor (46\%), comparable to active pixel sensors. Floating gates are used to store the arbitrary matrix coefficients on-chip. The chip operates in the subthreshold domain and thus has low power consumption (80 μW/frame). We present data for different convolutions and block transforms that were implemented using this architecture, and also present data from baseline JPEG and motion JPEG systems which we have implemented using MATIA.}, number = {3}, journal = {IEEE Journal of Solid-State Circuits}, author = {Bandyopadhyay, A. and Lee, Jungwon and Robucci, R. W. and Hasler, P.}, month = mar, year = {2006}, pages = {663--672} }

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