Automatic Power Modeling of Infrastructure IP for System-on-Chip Power Analysis

Automatic Power Modeling of Infrastructure IP for System-on-Chip Power Analysis. Bansal, N., Lahiri, K., & Raghunathan, A. In 20th International Conference on VLSI Design (VLSI Design 2007), Sixth International Conference on Embedded Systems (ICES 2007), 6-10 January 2007, Bangalore, India, pages 513–520, 2007.

Paper doi bibtex

@inproceedings{DBLP:conf/vlsid/BansalLR07,
  author    = {Nikhil Bansal and
               Kanishka Lahiri and
               Anand Raghunathan},
  title     = {Automatic Power Modeling of Infrastructure {IP} for System-on-Chip
               Power Analysis},
  booktitle = {20th International Conference on {VLSI} Design {(VLSI} Design 2007),
               Sixth International Conference on Embedded Systems {(ICES} 2007),
               6-10 January 2007, Bangalore, India},
  pages     = {513--520},
  year      = {2007},
  crossref  = {DBLP:conf/vlsid/2007},
  url       = {https://doi.org/10.1109/VLSID.2007.46},
  doi       = {10.1109/VLSID.2007.46},
  timestamp = {Tue, 23 May 2017 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/vlsid/BansalLR07},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}

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