Deterministic Shift Power Reduction in Test Compression. Basu, K., Kumar, R., Kulkarni, S., & Kapur, R. In Kaushik, B. K., Dasgupta, S., & Singh, V., editors, VLSI Design and Test - 21st International Symposium, VDAT 2017, Roorkee, India, June 29 - July 2, 2017, Revised Selected Papers, volume 711, of Communications in Computer and Information Science, pages 155–167, 2017. Springer.
Deterministic Shift Power Reduction in Test Compression [link]Paper  doi  bibtex   
@inproceedings{DBLP:conf/vdat/BasuKKK17,
  author    = {Kanad Basu and
               Rishi Kumar and
               Santosh Kulkarni and
               Rohit Kapur},
  editor    = {Brajesh Kumar Kaushik and
               Sudeb Dasgupta and
               Virendra Singh},
  title     = {Deterministic Shift Power Reduction in Test Compression},
  booktitle = {{VLSI} Design and Test - 21st International Symposium, {VDAT} 2017,
               Roorkee, India, June 29 - July 2, 2017, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {711},
  pages     = {155--167},
  publisher = {Springer},
  year      = {2017},
  url       = {https://doi.org/10.1007/978-981-10-7470-7\_17},
  doi       = {10.1007/978-981-10-7470-7\_17},
  timestamp = {Sun, 07 Jan 2018 00:00:00 +0100},
  biburl    = {https://dblp.org/rec/conf/vdat/BasuKKK17.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}

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