Constrained signal selection for post-silicon validation. Basu, K., Mishra, P., & Patra, P. In 2012 IEEE International High Level Design Validation and Test Workshop (HLDVT), pages 71–75, Huntington Beach, CA, USA, November, 2012. IEEE. ![Constrained signal selection for post-silicon validation [link]](https://bibbase.org/img/filetypes/link.svg "link")
Paper doi bibtex @inproceedings{basu_constrained_2012,
address = {Huntington Beach, CA, USA},
title = {Constrained signal selection for post-silicon validation},
isbn = {978-1-4673-2899-9 978-1-4673-2897-5 978-1-4673-2898-2},
url = {http://ieeexplore.ieee.org/document/6418245/},
doi = {10.1109/HLDVT.2012.6418245},
urldate = {2019-05-30},
booktitle = {2012 {IEEE} {International} {High} {Level} {Design} {Validation} and {Test} {Workshop} ({HLDVT})},
publisher = {IEEE},
author = {Basu, Kanad and Mishra, Prabhat and Patra, Priyadarsan},
month = nov,
year = {2012},
keywords = {\#nosource},
pages = {71--75},
}
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