System level fault-tolerance core mapping and FPGA-based verification of NoC. Becchu, N. K. R., Harishchandra, V. M., & Yernad Balachandra, N. K. Microelectronics Journal, 70:16–26, December, 2017.
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{"_id":"8swiw7YctFpkqKym3","bibbaseid":"becchu-harishchandra-yernadbalachandra-systemlevelfaulttolerancecoremappingandfpgabasedverificationofnoc-2017","author_short":["Becchu, N. K. R.","Harishchandra, V. M.","Yernad Balachandra, N. K."],"bibdata":{"bibtype":"article","type":"article","title":"System level fault-tolerance core mapping and FPGA-based verification of NoC","volume":"70","issn":"0026-2692","url":"https://www.sciencedirect.com/science/article/pii/S0026269217302884","doi":"10.1016/j.mejo.2017.09.010","language":"en","urldate":"2022-12-04","journal":"Microelectronics Journal","author":[{"propositions":[],"lastnames":["Becchu"],"firstnames":["Naresh","Kumar","Reddy"],"suffixes":[]},{"propositions":[],"lastnames":["Harishchandra"],"firstnames":["Vasantha","Moodabettu"],"suffixes":[]},{"propositions":[],"lastnames":["Yernad","Balachandra"],"firstnames":["Nithin","Kumar"],"suffixes":[]}],"month":"December","year":"2017","keywords":"Core, Kintex-7 FPGA KC705 evaluation kit, Network on Chip (NoC), Spare core placement","pages":"16–26","author_short":["Becchu, N. K. R.","Harishchandra, V. M.","Yernad Balachandra, N. K."],"key":"becchu_system_2017","id":"becchu_system_2017","bibbaseid":"becchu-harishchandra-yernadbalachandra-systemlevelfaulttolerancecoremappingandfpgabasedverificationofnoc-2017","role":"author","urls":{"Paper":"https://www.sciencedirect.com/science/article/pii/S0026269217302884"},"keyword":["Core","Kintex-7 FPGA KC705 evaluation kit","Network on Chip (NoC)","Spare core placement"],"metadata":{"authorlinks":{}},"html":""},"bibtype":"article","biburl":"https://bibbase.org/zotero/guptasonal","dataSources":["oirhNxAwKSWu4c3pk"],"keywords":["core","kintex-7 fpga kc705 evaluation kit","network on chip (noc)","spare core placement"],"search_terms":["system","level","fault","tolerance","core","mapping","fpga","based","verification","noc","becchu","harishchandra","yernad balachandra"],"title":"System level fault-tolerance core mapping and FPGA-based verification of NoC","year":2017}