Formal verification in the loop to enhance verification of safety-critical cyber-physical systems. Bernardeschi, C., Domenici, A., & Saponara, S. Electronic Communications of the EASST, 2019.
bibtex   
@article{bernardeschi_formal_2019,
	title = {Formal verification in the loop to enhance verification of safety-critical cyber-physical systems},
	volume = {77},
	journal = {Electronic Communications of the EASST},
	author = {Bernardeschi, Cinzia and Domenici, Andrea and Saponara, Sergio},
	year = {2019},
	keywords = {⛔ No DOI found},
}

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