New techniques for speeding-up fault-injection campaigns. Berrojo, L., González, I., Corno, F., Reorda, M. S., Squillero, G., Entrena, L., & Lopez, C. In Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition, pages 847–852. IEEE. bibtex @InProceedings{berrojo02new,
author = {Berrojo, Luis and Gonz{\'a}lez, Isabel and Corno, Fulvio and Reorda, Matteo Sonza and Squillero, Giovanni and Entrena, Luis and Lopez, Celia},
booktitle = {Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition},
date = {2002},
title = {New techniques for speeding-up fault-injection campaigns},
organization = {IEEE},
pages = {847--852},
comment = {* context: design circuits for fault-tolerance
* register transfer level (RTL)
* industry prefers simulated fault injection
* here, mainly aero and space
* pros
* maximum flexibility (e.g., regarding fault models)
* allows assessment during different stages in design process
* easy integration in existing workflows
* target inefficiency of simulated fault-injection
* fault model: single bit upsets
* fault-collapsing
* in order to reduce fault list, thus simulations
* by static analysis
* find equivalent faults
* same errors as others and vice versa
* find dominant faults
* same errors as other, but not vice versa
* by dynamic analysis
* log all read and write accesses to every bit
* collapsing as with static analysis (see above)
* collapsing via a set of rules
* e.g., ignore faults which are not read before being written
* since faults are masked
* e.g., bit n read at t=x and written at t=x+100, so do not
simulate faults to bit n between t=x and t=x+100
* optimize execution of simulation},
file = {:berrojo02new - New techniques for speeding-up fault-injection campaigns.pdf:PDF},
groups = {hardware},
timestamp = {2021-08-30},
}
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