The Dual Processor Platform Architecture: Demo Abstract. Beutel, J., Trüb, R., Forno, R. D., Wegmann, M., Gsell, T., Jacob, R., Keller, M., Sutton, F., & Thiele, L. In Proceedings of the 18th International Conference on Information Processing in Sensor Networks, of IPSN '19, pages 335–336, New York, NY, USA, 2019. ACM. event-place: Montreal, Quebec, Canada![The Dual Processor Platform Architecture: Demo Abstract [link]](https://bibbase.org/img/filetypes/link.svg "link")
Paper doi abstract bibtex The Dual Processor Platform (DPP) is a novel architecture template for networked embedded systems based on a strictly asynchronous processor interconnect that allows to minimize interference with a proven predictable behavior [7]. Contrary to traditional platforms [1, 5] DPP tries to mitigate interference by isolating different tasks and mapping them onto dedicated hardware resources. Typically, two different task sets - (i) sensing/actuation/data processing and (ii) communication - are mapped onto two different physically separated processing elements (usually low-power microcontrollers), allowing each to be optimized according to their individual requirements. Such hardware partitioning is a standard approach, frequently found in more complex sensor system implementations [2]. While the communication processor handles wireless packet transmission and reception, the application processor is dedicated to the sensor data acquisition, processing and actuation. But this strict separation of resources and function also requires a processor interconnect: BOLT [7], a stateful processor interconnect specifically designed based on this paradigm allows a strict decoupling of the power, clock and time domains of the two processing elements by allowing only asynchronous message passing between the two. The strict limitation to an asynchronous interface allows for predictable run-time behavior that, in addition to typical behavior observed from experiments, has been formally verified [7]. The most notable advantages of this approach are: Modularity Exchanging one of the components is hassle free and does not require a change to the other components. Simpler software The complexity of software development and validation is significantly reduced by task decoupling. Parallel development Development of the two separate entities can take place independently. Independent power management Each subsystem can take independent decisions on when to utilize low-power modes.
@inproceedings{beutel2019DPPdemo,
address = {New York, NY, USA},
series = {{IPSN} '19},
title = {The {Dual} {Processor} {Platform} {Architecture}: {Demo} {Abstract}},
isbn = {978-1-4503-6284-9},
shorttitle = {The {Dual} {Processor} {Platform} {Architecture}},
url = {http://doi.acm.org/10.1145/3302506.3312481},
doi = {10.1145/3302506.3312481},
abstract = {The Dual Processor Platform (DPP) is a novel architecture template for networked embedded systems based on a strictly asynchronous processor interconnect that allows to minimize interference with a proven predictable behavior [7]. Contrary to traditional platforms [1, 5] DPP tries to mitigate interference by isolating different tasks and mapping them onto dedicated hardware resources. Typically, two different task sets - (i) sensing/actuation/data processing and (ii) communication - are mapped onto two different physically separated processing elements (usually low-power microcontrollers), allowing each to be optimized according to their individual requirements. Such hardware partitioning is a standard approach, frequently found in more complex sensor system implementations [2]. While the communication processor handles wireless packet transmission and reception, the application processor is dedicated to the sensor data acquisition, processing and actuation. But this strict separation of resources and function also requires a processor interconnect: BOLT [7], a stateful processor interconnect specifically designed based on this paradigm allows a strict decoupling of the power, clock and time domains of the two processing elements by allowing only asynchronous message passing between the two. The strict limitation to an asynchronous interface allows for predictable run-time behavior that, in addition to typical behavior observed from experiments, has been formally verified [7]. The most notable advantages of this approach are: Modularity Exchanging one of the components is hassle free and does not require a change to the other components. Simpler software The complexity of software development and validation is significantly reduced by task decoupling. Parallel development Development of the two separate entities can take place independently. Independent power management Each subsystem can take independent decisions on when to utilize low-power modes.},
urldate = {2019-11-03},
booktitle = {Proceedings of the 18th {International} {Conference} on {Information} {Processing} in {Sensor} {Networks}},
publisher = {ACM},
author = {Beutel, Jan and Trüb, Roman and Forno, Reto Da and Wegmann, Markus and Gsell, Tonio and Jacob, Romain and Keller, Michael and Sutton, Felix and Thiele, Lothar},
year = {2019},
note = {event-place: Montreal, Quebec, Canada},
keywords = {low-power, modular architecture, sensor network platforms},
pages = {335--336}
}
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