Resource optimization for emulation of behavioral models of mixed signal circuits on FPGA: a case study of DC-DC buck converter. Bhattacharya, R., Kumar, S., & Biswas, S. Int. J. Circuit Theory Appl., 45(11):1701-1741, 2017.
Resource optimization for emulation of behavioral models of mixed signal circuits on FPGA: a case study of DC-DC buck converter. [link]Link  Resource optimization for emulation of behavioral models of mixed signal circuits on FPGA: a case study of DC-DC buck converter. [link]Paper  bibtex   
@article{journals/ijcta/BhattacharyaKB17,
  added-at = {2025-03-03T00:00:00.000+0100},
  author = {Bhattacharya, Rahul and Kumar, Subindu and Biswas, Santosh},
  biburl = {https://www.bibsonomy.org/bibtex/27f14cd6ec75cf51bcd27747ee512b49c/dblp},
  ee = {https://doi.org/10.1002/cta.2323},
  interhash = {39f314c8d610a4d785bf7827fa6bfbaa},
  intrahash = {7f14cd6ec75cf51bcd27747ee512b49c},
  journal = {Int. J. Circuit Theory Appl.},
  keywords = {dblp},
  number = 11,
  pages = {1701-1741},
  timestamp = {2025-04-01T18:09:13.000+0200},
  title = {Resource optimization for emulation of behavioral models of mixed signal circuits on FPGA: a case study of DC-DC buck converter.},
  url = {http://dblp.uni-trier.de/db/journals/ijcta/ijcta45.html#BhattacharyaKB17},
  volume = 45,
  year = 2017
}

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