LSTA: Learning-based static timing analysis for high-dimensional correlated on-chip variations. Bian, S., Hiromoto, M., Shintani, M., & Sato, T. In 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC), pages 1–6, June, 2017. doi abstract bibtex As the transistor process technology continues to scale, the aging effect posits new challenges to the already complex static timing analysis (STA) process. In this paper, we first observe that aging can be thought of a type of correlated dynamic on-chip variations (OCV), and identify the problem introduced by such type of OCV. In particular, we take the negative bias temperature instability (NBTI) as an example dynamic OCV mechanism. We then propose a learning-based STA (LSTA) library to “predict” the timing of gates by capturing the correlation between our designed predictors. In the experiment, we used a linear regressor, support vector regression, and a non-linear method, random forest, to create the prediction model. An ISCAS'89 benchmark circuit is used as a training sample to for the algorithms to learn the aging model of gates, and the accuracies of the model is then tested on two processor-scale designs using the library are evaluated, achieving a maximum absolute error of 3.42%.
@inproceedings{bian_lsta_2017,
title = {{LSTA}: {Learning}-based static timing analysis for high-dimensional correlated on-chip variations},
shorttitle = {{LSTA}},
doi = {10.1145/3061639.3062280},
abstract = {As the transistor process technology continues to scale, the aging effect posits new challenges to the already complex static timing analysis (STA) process. In this paper, we first observe that aging can be thought of a type of correlated dynamic on-chip variations (OCV), and identify the problem introduced by such type of OCV. In particular, we take the negative bias temperature instability (NBTI) as an example dynamic OCV mechanism. We then propose a learning-based STA (LSTA) library to “predict” the timing of gates by capturing the correlation between our designed predictors. In the experiment, we used a linear regressor, support vector regression, and a non-linear method, random forest, to create the prediction model. An ISCAS'89 benchmark circuit is used as a training sample to for the algorithms to learn the aging model of gates, and the accuracies of the model is then tested on two processor-scale designs using the library are evaluated, achieving a maximum absolute error of 3.42\%.},
booktitle = {2017 54th {ACM}/{EDAC}/{IEEE} {Design} {Automation} {Conference} ({DAC})},
author = {Bian, S. and Hiromoto, M. and Shintani, M. and Sato, T.},
month = jun,
year = {2017},
keywords = {\#broken, Correlation, Degradation, Jab/\#DAC, LSTA, Libraries, Logic gates, Negative bias temperature instability, STA library, Thermal variables control, Timing, aging effect, aging model, complex static timing analysis process, dynamic OCV mechanism, gates, high-dimensional correlated on-chip variations, learning (artificial intelligence), learning-based static timing analysis, linear regressor, logic gates, negative bias temperature instability, nonlinear method, prediction model, processor-scale designs, regression analysis, support vector machines, support vector regression, timing, transistor process technology},
pages = {1--6},
}
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We then propose a learning-based STA (LSTA) library to “predict” the timing of gates by capturing the correlation between our designed predictors. In the experiment, we used a linear regressor, support vector regression, and a non-linear method, random forest, to create the prediction model. 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