Bounded Model Checking. Biere, A. 185(1):457–481.
doi  abstract   bibtex   
One of the most important industrial applications of SAT is currently Bounded Model Checking (BMC). This technique is typically used for formal hardware verification in the context of Electronic Design Automation. But BMC has successfully been applied to many other domains as well. In practice, BMC is mainly used for falsification, which is concerned with violations of temporal properties. In addition, a considerable part of this chapter discusses complete extensions, including k-induction and interpolation. These extensions also allow to prove properties. © 2009 John Franco and John Martin and IOS Press.
@article{biereBoundedModelChecking2009,
  title = {Bounded Model Checking},
  volume = {185},
  issn = {09226389},
  doi = {10.3233/978-1-58603-929-5-457},
  abstract = {One of the most important industrial applications of SAT is currently Bounded Model Checking (BMC). This technique is typically used for formal hardware verification in the context of Electronic Design Automation. But BMC has successfully been applied to many other domains as well. In practice, BMC is mainly used for falsification, which is concerned with violations of temporal properties. In addition, a considerable part of this chapter discusses complete extensions, including k-induction and interpolation. These extensions also allow to prove properties. © 2009 John Franco and John Martin and IOS Press.},
  number = {1},
  journaltitle = {Frontiers in Artificial Intelligence and Applications},
  date = {2009},
  pages = {457--481},
  author = {Biere, Armin},
  file = {/home/dimitri/Nextcloud/Zotero/storage/SB4RYQKV/SATChapter14.pdf}
}
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