@inproceedings{DBLP:conf/nanoarch/BobbaGZMSLM12,
  author    = {Shashikanth Bobba and
               Pierre{-}Emmanuel Gaillardon and
               Jian Zhang and
               Michele De Marchi and
               Davide Sacchetto and
               Yusuf Leblebici and
               Giovanni De Micheli},
  title     = {Process/design co-optimization of regular logic tiles for double-gate
               silicon nanowire transistors},
  booktitle = {Proceedings of the 2012 {IEEE/ACM} International Symposium on Nanoscale
               Architectures, {NANOARCH} 2012, Amsterdam, The Netherlands, July 4-6,
               2012},
  pages     = {55--60},
  year      = {2012},
  crossref  = {DBLP:conf/nanoarch/2012},
  url       = {https://doi.org/10.1145/2765491.2765503},
  doi       = {10.1145/2765491.2765503},
  timestamp = {Wed, 16 Oct 2019 14:14:50 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/nanoarch/BobbaGZMSLM12},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}

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