A Fast ULV Logic Synthesis Flow in Many-V$_\mboxt$ CMOS Processes for Minimum Energy Under Timing Constraints

A Fast ULV Logic Synthesis Flow in Many-V$_\mboxt$ CMOS Processes for Minimum Energy Under Timing Constraints. Bol, D., Hocquet, C., & Regazzoni, F. IEEE Trans. Circuits Syst. II Express Briefs, 59-II(12):947–951, 2012.
$A Fast ULV Logic Synthesis Flow in Many-V$_\mboxt$ CMOS Processes for Minimum Energy Under Timing Constraints [link]$ Paper doi bibtex

@article{DBLP:journals/tcas/BolHR12,
  author    = {David Bol and
               C{\'{e}}dric Hocquet and
               Francesco Regazzoni},
  title     = {A Fast {ULV} Logic Synthesis Flow in Many-V\({}_{\mbox{t}}\) {CMOS}
               Processes for Minimum Energy Under Timing Constraints},
  journal   = {{IEEE} Trans. Circuits Syst. {II} Express Briefs},
  volume    = {59-II},
  number    = {12},
  pages     = {947--951},
  year      = {2012},
  url       = {https://doi.org/10.1109/TCSII.2012.2231034},
  doi       = {10.1109/TCSII.2012.2231034},
  timestamp = {Wed, 27 May 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/tcas/BolHR12.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}

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